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1/*
2 * Driver for Atmel Pulse Width Modulation Controller
3 *
4 * Copyright (C) 2013 Atmel Corporation
5 * Bo Shen <voice.shen@atmel.com>
6 *
7 * Licensed under GPLv2.
8 */
9
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/err.h>
13#include <linux/io.h>
14#include <linux/module.h>
15#include <linux/mutex.h>
16#include <linux/of.h>
17#include <linux/of_device.h>
18#include <linux/platform_device.h>
19#include <linux/pwm.h>
20#include <linux/slab.h>
21
22/* The following is global registers for PWM controller */
23#define PWM_ENA 0x04
24#define PWM_DIS 0x08
25#define PWM_SR 0x0C
26#define PWM_ISR 0x1C
27/* Bit field in SR */
28#define PWM_SR_ALL_CH_ON 0x0F
29
30/* The following register is PWM channel related registers */
31#define PWM_CH_REG_OFFSET 0x200
32#define PWM_CH_REG_SIZE 0x20
33
34#define PWM_CMR 0x0
35/* Bit field in CMR */
36#define PWM_CMR_CPOL (1 << 9)
37#define PWM_CMR_UPD_CDTY (1 << 10)
38#define PWM_CMR_CPRE_MSK 0xF
39
40/* The following registers for PWM v1 */
41#define PWMV1_CDTY 0x04
42#define PWMV1_CPRD 0x08
43#define PWMV1_CUPD 0x10
44
45/* The following registers for PWM v2 */
46#define PWMV2_CDTY 0x04
47#define PWMV2_CDTYUPD 0x08
48#define PWMV2_CPRD 0x0C
49#define PWMV2_CPRDUPD 0x10
50
51/*
52 * Max value for duty and period
53 *
54 * Although the duty and period register is 32 bit,
55 * however only the LSB 16 bits are significant.
56 */
57#define PWM_MAX_DTY 0xFFFF
58#define PWM_MAX_PRD 0xFFFF
59#define PRD_MAX_PRES 10
60
61struct atmel_pwm_registers {
62 u8 period;
63 u8 period_upd;
64 u8 duty;
65 u8 duty_upd;
66};
67
68struct atmel_pwm_chip {
69 struct pwm_chip chip;
70 struct clk *clk;
71 void __iomem *base;
72 const struct atmel_pwm_registers *regs;
73
74 unsigned int updated_pwms;
75 /* ISR is cleared when read, ensure only one thread does that */
76 struct mutex isr_lock;
77};
78
79static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip)
80{
81 return container_of(chip, struct atmel_pwm_chip, chip);
82}
83
84static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
85 unsigned long offset)
86{
87 return readl_relaxed(chip->base + offset);
88}
89
90static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
91 unsigned long offset, unsigned long val)
92{
93 writel_relaxed(val, chip->base + offset);
94}
95
96static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
97 unsigned int ch, unsigned long offset)
98{
99 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
100
101 return readl_relaxed(chip->base + base + offset);
102}
103
104static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
105 unsigned int ch, unsigned long offset,
106 unsigned long val)
107{
108 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
109
110 writel_relaxed(val, chip->base + base + offset);
111}
112
113static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip,
114 const struct pwm_state *state,
115 unsigned long *cprd, u32 *pres)
116{
117 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
118 unsigned long long cycles = state->period;
119
120 /* Calculate the period cycles and prescale value */
121 cycles *= clk_get_rate(atmel_pwm->clk);
122 do_div(cycles, NSEC_PER_SEC);
123
124 for (*pres = 0; cycles > PWM_MAX_PRD; cycles >>= 1)
125 (*pres)++;
126
127 if (*pres > PRD_MAX_PRES) {
128 dev_err(chip->dev, "pres exceeds the maximum value\n");
129 return -EINVAL;
130 }
131
132 *cprd = cycles;
133
134 return 0;
135}
136
137static void atmel_pwm_calculate_cdty(const struct pwm_state *state,
138 unsigned long cprd, unsigned long *cdty)
139{
140 unsigned long long cycles = state->duty_cycle;
141
142 cycles *= cprd;
143 do_div(cycles, state->period);
144 *cdty = cprd - cycles;
145}
146
147static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm,
148 unsigned long cdty)
149{
150 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
151 u32 val;
152
153 if (atmel_pwm->regs->duty_upd ==
154 atmel_pwm->regs->period_upd) {
155 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
156 val &= ~PWM_CMR_UPD_CDTY;
157 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
158 }
159
160 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
161 atmel_pwm->regs->duty_upd, cdty);
162}
163
164static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip,
165 struct pwm_device *pwm,
166 unsigned long cprd, unsigned long cdty)
167{
168 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
169
170 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
171 atmel_pwm->regs->duty, cdty);
172 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
173 atmel_pwm->regs->period, cprd);
174}
175
176static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm,
177 bool disable_clk)
178{
179 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
180 unsigned long timeout = jiffies + 2 * HZ;
181
182 /*
183 * Wait for at least a complete period to have passed before disabling a
184 * channel to be sure that CDTY has been updated
185 */
186 mutex_lock(&atmel_pwm->isr_lock);
187 atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
188
189 while (!(atmel_pwm->updated_pwms & (1 << pwm->hwpwm)) &&
190 time_before(jiffies, timeout)) {
191 usleep_range(10, 100);
192 atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
193 }
194
195 mutex_unlock(&atmel_pwm->isr_lock);
196 atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);
197
198 /*
199 * Wait for the PWM channel disable operation to be effective before
200 * stopping the clock.
201 */
202 timeout = jiffies + 2 * HZ;
203
204 while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) &&
205 time_before(jiffies, timeout))
206 usleep_range(10, 100);
207
208 if (disable_clk)
209 clk_disable(atmel_pwm->clk);
210}
211
212static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
213 struct pwm_state *state)
214{
215 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
216 struct pwm_state cstate;
217 unsigned long cprd, cdty;
218 u32 pres, val;
219 int ret;
220
221 pwm_get_state(pwm, &cstate);
222
223 if (state->enabled) {
224 if (cstate.enabled &&
225 cstate.polarity == state->polarity &&
226 cstate.period == state->period) {
227 cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
228 atmel_pwm->regs->period);
229 atmel_pwm_calculate_cdty(state, cprd, &cdty);
230 atmel_pwm_update_cdty(chip, pwm, cdty);
231 return 0;
232 }
233
234 ret = atmel_pwm_calculate_cprd_and_pres(chip, state, &cprd,
235 &pres);
236 if (ret) {
237 dev_err(chip->dev,
238 "failed to calculate cprd and prescaler\n");
239 return ret;
240 }
241
242 atmel_pwm_calculate_cdty(state, cprd, &cdty);
243
244 if (cstate.enabled) {
245 atmel_pwm_disable(chip, pwm, false);
246 } else {
247 ret = clk_enable(atmel_pwm->clk);
248 if (ret) {
249 dev_err(chip->dev, "failed to enable clock\n");
250 return ret;
251 }
252 }
253
254 /* It is necessary to preserve CPOL, inside CMR */
255 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
256 val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
257 if (state->polarity == PWM_POLARITY_NORMAL)
258 val &= ~PWM_CMR_CPOL;
259 else
260 val |= PWM_CMR_CPOL;
261 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
262 atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty);
263 mutex_lock(&atmel_pwm->isr_lock);
264 atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
265 atmel_pwm->updated_pwms &= ~(1 << pwm->hwpwm);
266 mutex_unlock(&atmel_pwm->isr_lock);
267 atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
268 } else if (cstate.enabled) {
269 atmel_pwm_disable(chip, pwm, true);
270 }
271
272 return 0;
273}
274
275static const struct pwm_ops atmel_pwm_ops = {
276 .apply = atmel_pwm_apply,
277 .owner = THIS_MODULE,
278};
279
280static const struct atmel_pwm_registers atmel_pwm_regs_v1 = {
281 .period = PWMV1_CPRD,
282 .period_upd = PWMV1_CUPD,
283 .duty = PWMV1_CDTY,
284 .duty_upd = PWMV1_CUPD,
285};
286
287static const struct atmel_pwm_registers atmel_pwm_regs_v2 = {
288 .period = PWMV2_CPRD,
289 .period_upd = PWMV2_CPRDUPD,
290 .duty = PWMV2_CDTY,
291 .duty_upd = PWMV2_CDTYUPD,
292};
293
294static const struct platform_device_id atmel_pwm_devtypes[] = {
295 {
296 .name = "at91sam9rl-pwm",
297 .driver_data = (kernel_ulong_t)&atmel_pwm_regs_v1,
298 }, {
299 .name = "sama5d3-pwm",
300 .driver_data = (kernel_ulong_t)&atmel_pwm_regs_v2,
301 }, {
302 /* sentinel */
303 },
304};
305MODULE_DEVICE_TABLE(platform, atmel_pwm_devtypes);
306
307static const struct of_device_id atmel_pwm_dt_ids[] = {
308 {
309 .compatible = "atmel,at91sam9rl-pwm",
310 .data = &atmel_pwm_regs_v1,
311 }, {
312 .compatible = "atmel,sama5d3-pwm",
313 .data = &atmel_pwm_regs_v2,
314 }, {
315 .compatible = "atmel,sama5d2-pwm",
316 .data = &atmel_pwm_regs_v2,
317 }, {
318 /* sentinel */
319 },
320};
321MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
322
323static inline const struct atmel_pwm_registers *
324atmel_pwm_get_driver_data(struct platform_device *pdev)
325{
326 const struct platform_device_id *id;
327
328 if (pdev->dev.of_node)
329 return of_device_get_match_data(&pdev->dev);
330
331 id = platform_get_device_id(pdev);
332
333 return (struct atmel_pwm_registers *)id->driver_data;
334}
335
336static int atmel_pwm_probe(struct platform_device *pdev)
337{
338 const struct atmel_pwm_registers *regs;
339 struct atmel_pwm_chip *atmel_pwm;
340 struct resource *res;
341 int ret;
342
343 regs = atmel_pwm_get_driver_data(pdev);
344 if (!regs)
345 return -ENODEV;
346
347 atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);
348 if (!atmel_pwm)
349 return -ENOMEM;
350
351 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
352 atmel_pwm->base = devm_ioremap_resource(&pdev->dev, res);
353 if (IS_ERR(atmel_pwm->base))
354 return PTR_ERR(atmel_pwm->base);
355
356 atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL);
357 if (IS_ERR(atmel_pwm->clk))
358 return PTR_ERR(atmel_pwm->clk);
359
360 ret = clk_prepare(atmel_pwm->clk);
361 if (ret) {
362 dev_err(&pdev->dev, "failed to prepare PWM clock\n");
363 return ret;
364 }
365
366 atmel_pwm->chip.dev = &pdev->dev;
367 atmel_pwm->chip.ops = &atmel_pwm_ops;
368
369 if (pdev->dev.of_node) {
370 atmel_pwm->chip.of_xlate = of_pwm_xlate_with_flags;
371 atmel_pwm->chip.of_pwm_n_cells = 3;
372 }
373
374 atmel_pwm->chip.base = -1;
375 atmel_pwm->chip.npwm = 4;
376 atmel_pwm->regs = regs;
377 atmel_pwm->updated_pwms = 0;
378 mutex_init(&atmel_pwm->isr_lock);
379
380 ret = pwmchip_add(&atmel_pwm->chip);
381 if (ret < 0) {
382 dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);
383 goto unprepare_clk;
384 }
385
386 platform_set_drvdata(pdev, atmel_pwm);
387
388 return ret;
389
390unprepare_clk:
391 clk_unprepare(atmel_pwm->clk);
392 return ret;
393}
394
395static int atmel_pwm_remove(struct platform_device *pdev)
396{
397 struct atmel_pwm_chip *atmel_pwm = platform_get_drvdata(pdev);
398
399 clk_unprepare(atmel_pwm->clk);
400 mutex_destroy(&atmel_pwm->isr_lock);
401
402 return pwmchip_remove(&atmel_pwm->chip);
403}
404
405static struct platform_driver atmel_pwm_driver = {
406 .driver = {
407 .name = "atmel-pwm",
408 .of_match_table = of_match_ptr(atmel_pwm_dt_ids),
409 },
410 .id_table = atmel_pwm_devtypes,
411 .probe = atmel_pwm_probe,
412 .remove = atmel_pwm_remove,
413};
414module_platform_driver(atmel_pwm_driver);
415
416MODULE_ALIAS("platform:atmel-pwm");
417MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>");
418MODULE_DESCRIPTION("Atmel PWM driver");
419MODULE_LICENSE("GPL v2");
1/*
2 * Driver for Atmel Pulse Width Modulation Controller
3 *
4 * Copyright (C) 2013 Atmel Corporation
5 * Bo Shen <voice.shen@atmel.com>
6 *
7 * Licensed under GPLv2.
8 */
9
10#include <linux/clk.h>
11#include <linux/err.h>
12#include <linux/io.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include <linux/pwm.h>
18#include <linux/slab.h>
19
20/* The following is global registers for PWM controller */
21#define PWM_ENA 0x04
22#define PWM_DIS 0x08
23#define PWM_SR 0x0C
24/* Bit field in SR */
25#define PWM_SR_ALL_CH_ON 0x0F
26
27/* The following register is PWM channel related registers */
28#define PWM_CH_REG_OFFSET 0x200
29#define PWM_CH_REG_SIZE 0x20
30
31#define PWM_CMR 0x0
32/* Bit field in CMR */
33#define PWM_CMR_CPOL (1 << 9)
34#define PWM_CMR_UPD_CDTY (1 << 10)
35#define PWM_CMR_CPRE_MSK 0xF
36
37/* The following registers for PWM v1 */
38#define PWMV1_CDTY 0x04
39#define PWMV1_CPRD 0x08
40#define PWMV1_CUPD 0x10
41
42/* The following registers for PWM v2 */
43#define PWMV2_CDTY 0x04
44#define PWMV2_CDTYUPD 0x08
45#define PWMV2_CPRD 0x0C
46#define PWMV2_CPRDUPD 0x10
47
48/*
49 * Max value for duty and period
50 *
51 * Although the duty and period register is 32 bit,
52 * however only the LSB 16 bits are significant.
53 */
54#define PWM_MAX_DTY 0xFFFF
55#define PWM_MAX_PRD 0xFFFF
56#define PRD_MAX_PRES 10
57
58struct atmel_pwm_chip {
59 struct pwm_chip chip;
60 struct clk *clk;
61 void __iomem *base;
62
63 void (*config)(struct pwm_chip *chip, struct pwm_device *pwm,
64 unsigned long dty, unsigned long prd);
65};
66
67static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip)
68{
69 return container_of(chip, struct atmel_pwm_chip, chip);
70}
71
72static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
73 unsigned long offset)
74{
75 return readl_relaxed(chip->base + offset);
76}
77
78static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
79 unsigned long offset, unsigned long val)
80{
81 writel_relaxed(val, chip->base + offset);
82}
83
84static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
85 unsigned int ch, unsigned long offset)
86{
87 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
88
89 return readl_relaxed(chip->base + base + offset);
90}
91
92static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
93 unsigned int ch, unsigned long offset,
94 unsigned long val)
95{
96 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
97
98 writel_relaxed(val, chip->base + base + offset);
99}
100
101static int atmel_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
102 int duty_ns, int period_ns)
103{
104 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
105 unsigned long clk_rate, prd, dty;
106 unsigned long long div;
107 unsigned int pres = 0;
108 u32 val;
109 int ret;
110
111 if (test_bit(PWMF_ENABLED, &pwm->flags) && (period_ns != pwm->period)) {
112 dev_err(chip->dev, "cannot change PWM period while enabled\n");
113 return -EBUSY;
114 }
115
116 clk_rate = clk_get_rate(atmel_pwm->clk);
117 div = clk_rate;
118
119 /* Calculate the period cycles */
120 while (div > PWM_MAX_PRD) {
121 div = clk_rate / (1 << pres);
122 div = div * period_ns;
123 /* 1/Hz = 100000000 ns */
124 do_div(div, 1000000000);
125
126 if (pres++ > PRD_MAX_PRES) {
127 dev_err(chip->dev, "pres exceeds the maximum value\n");
128 return -EINVAL;
129 }
130 }
131
132 /* Calculate the duty cycles */
133 prd = div;
134 div *= duty_ns;
135 do_div(div, period_ns);
136 dty = prd - div;
137
138 ret = clk_enable(atmel_pwm->clk);
139 if (ret) {
140 dev_err(chip->dev, "failed to enable PWM clock\n");
141 return ret;
142 }
143
144 /* It is necessary to preserve CPOL, inside CMR */
145 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
146 val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
147 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
148 atmel_pwm->config(chip, pwm, dty, prd);
149
150 clk_disable(atmel_pwm->clk);
151 return ret;
152}
153
154static void atmel_pwm_config_v1(struct pwm_chip *chip, struct pwm_device *pwm,
155 unsigned long dty, unsigned long prd)
156{
157 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
158 unsigned int val;
159
160 if (test_bit(PWMF_ENABLED, &pwm->flags)) {
161 /*
162 * If the PWM channel is enabled, using the update register,
163 * it needs to set bit 10 of CMR to 0
164 */
165 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CUPD, dty);
166
167 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
168 val &= ~PWM_CMR_UPD_CDTY;
169 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
170 } else {
171 /*
172 * If the PWM channel is disabled, write value to duty and
173 * period registers directly.
174 */
175 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CDTY, dty);
176 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CPRD, prd);
177 }
178}
179
180static void atmel_pwm_config_v2(struct pwm_chip *chip, struct pwm_device *pwm,
181 unsigned long dty, unsigned long prd)
182{
183 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
184
185 if (test_bit(PWMF_ENABLED, &pwm->flags)) {
186 /*
187 * If the PWM channel is enabled, using the duty update register
188 * to update the value.
189 */
190 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV2_CDTYUPD, dty);
191 } else {
192 /*
193 * If the PWM channel is disabled, write value to duty and
194 * period registers directly.
195 */
196 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV2_CDTY, dty);
197 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV2_CPRD, prd);
198 }
199}
200
201static int atmel_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
202 enum pwm_polarity polarity)
203{
204 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
205 u32 val;
206 int ret;
207
208 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
209
210 if (polarity == PWM_POLARITY_NORMAL)
211 val &= ~PWM_CMR_CPOL;
212 else
213 val |= PWM_CMR_CPOL;
214
215 ret = clk_enable(atmel_pwm->clk);
216 if (ret) {
217 dev_err(chip->dev, "failed to enable PWM clock\n");
218 return ret;
219 }
220
221 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
222
223 clk_disable(atmel_pwm->clk);
224
225 return 0;
226}
227
228static int atmel_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
229{
230 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
231 int ret;
232
233 ret = clk_enable(atmel_pwm->clk);
234 if (ret) {
235 dev_err(chip->dev, "failed to enable PWM clock\n");
236 return ret;
237 }
238
239 atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
240
241 return 0;
242}
243
244static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
245{
246 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
247
248 atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);
249
250 clk_disable(atmel_pwm->clk);
251}
252
253static const struct pwm_ops atmel_pwm_ops = {
254 .config = atmel_pwm_config,
255 .set_polarity = atmel_pwm_set_polarity,
256 .enable = atmel_pwm_enable,
257 .disable = atmel_pwm_disable,
258 .owner = THIS_MODULE,
259};
260
261struct atmel_pwm_data {
262 void (*config)(struct pwm_chip *chip, struct pwm_device *pwm,
263 unsigned long dty, unsigned long prd);
264};
265
266static const struct atmel_pwm_data atmel_pwm_data_v1 = {
267 .config = atmel_pwm_config_v1,
268};
269
270static const struct atmel_pwm_data atmel_pwm_data_v2 = {
271 .config = atmel_pwm_config_v2,
272};
273
274static const struct platform_device_id atmel_pwm_devtypes[] = {
275 {
276 .name = "at91sam9rl-pwm",
277 .driver_data = (kernel_ulong_t)&atmel_pwm_data_v1,
278 }, {
279 .name = "sama5d3-pwm",
280 .driver_data = (kernel_ulong_t)&atmel_pwm_data_v2,
281 }, {
282 /* sentinel */
283 },
284};
285MODULE_DEVICE_TABLE(platform, atmel_pwm_devtypes);
286
287static const struct of_device_id atmel_pwm_dt_ids[] = {
288 {
289 .compatible = "atmel,at91sam9rl-pwm",
290 .data = &atmel_pwm_data_v1,
291 }, {
292 .compatible = "atmel,sama5d3-pwm",
293 .data = &atmel_pwm_data_v2,
294 }, {
295 /* sentinel */
296 },
297};
298MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
299
300static inline const struct atmel_pwm_data *
301atmel_pwm_get_driver_data(struct platform_device *pdev)
302{
303 if (pdev->dev.of_node) {
304 const struct of_device_id *match;
305
306 match = of_match_device(atmel_pwm_dt_ids, &pdev->dev);
307 if (!match)
308 return NULL;
309
310 return match->data;
311 } else {
312 const struct platform_device_id *id;
313
314 id = platform_get_device_id(pdev);
315
316 return (struct atmel_pwm_data *)id->driver_data;
317 }
318}
319
320static int atmel_pwm_probe(struct platform_device *pdev)
321{
322 const struct atmel_pwm_data *data;
323 struct atmel_pwm_chip *atmel_pwm;
324 struct resource *res;
325 int ret;
326
327 data = atmel_pwm_get_driver_data(pdev);
328 if (!data)
329 return -ENODEV;
330
331 atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);
332 if (!atmel_pwm)
333 return -ENOMEM;
334
335 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
336 atmel_pwm->base = devm_ioremap_resource(&pdev->dev, res);
337 if (IS_ERR(atmel_pwm->base))
338 return PTR_ERR(atmel_pwm->base);
339
340 atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL);
341 if (IS_ERR(atmel_pwm->clk))
342 return PTR_ERR(atmel_pwm->clk);
343
344 ret = clk_prepare(atmel_pwm->clk);
345 if (ret) {
346 dev_err(&pdev->dev, "failed to prepare PWM clock\n");
347 return ret;
348 }
349
350 atmel_pwm->chip.dev = &pdev->dev;
351 atmel_pwm->chip.ops = &atmel_pwm_ops;
352
353 if (pdev->dev.of_node) {
354 atmel_pwm->chip.of_xlate = of_pwm_xlate_with_flags;
355 atmel_pwm->chip.of_pwm_n_cells = 3;
356 }
357
358 atmel_pwm->chip.base = -1;
359 atmel_pwm->chip.npwm = 4;
360 atmel_pwm->config = data->config;
361
362 ret = pwmchip_add(&atmel_pwm->chip);
363 if (ret < 0) {
364 dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);
365 goto unprepare_clk;
366 }
367
368 platform_set_drvdata(pdev, atmel_pwm);
369
370 return ret;
371
372unprepare_clk:
373 clk_unprepare(atmel_pwm->clk);
374 return ret;
375}
376
377static int atmel_pwm_remove(struct platform_device *pdev)
378{
379 struct atmel_pwm_chip *atmel_pwm = platform_get_drvdata(pdev);
380
381 clk_unprepare(atmel_pwm->clk);
382
383 return pwmchip_remove(&atmel_pwm->chip);
384}
385
386static struct platform_driver atmel_pwm_driver = {
387 .driver = {
388 .name = "atmel-pwm",
389 .of_match_table = of_match_ptr(atmel_pwm_dt_ids),
390 },
391 .id_table = atmel_pwm_devtypes,
392 .probe = atmel_pwm_probe,
393 .remove = atmel_pwm_remove,
394};
395module_platform_driver(atmel_pwm_driver);
396
397MODULE_ALIAS("platform:atmel-pwm");
398MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>");
399MODULE_DESCRIPTION("Atmel PWM driver");
400MODULE_LICENSE("GPL v2");