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1/****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10#include "net_driver.h"
11#include "ef10_regs.h"
12#include "io.h"
13#include "mcdi.h"
14#include "mcdi_pcol.h"
15#include "nic.h"
16#include "workarounds.h"
17#include "selftest.h"
18#include "ef10_sriov.h"
19#include <linux/in.h>
20#include <linux/jhash.h>
21#include <linux/wait.h>
22#include <linux/workqueue.h>
23
24/* Hardware control for EF10 architecture including 'Huntington'. */
25
26#define EFX_EF10_DRVGEN_EV 7
27enum {
28 EFX_EF10_TEST = 1,
29 EFX_EF10_REFILL,
30};
31/* The maximum size of a shared RSS context */
32/* TODO: this should really be from the mcdi protocol export */
33#define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
34
35/* The filter table(s) are managed by firmware and we have write-only
36 * access. When removing filters we must identify them to the
37 * firmware by a 64-bit handle, but this is too wide for Linux kernel
38 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
39 * be able to tell in advance whether a requested insertion will
40 * replace an existing filter. Therefore we maintain a software hash
41 * table, which should be at least as large as the hardware hash
42 * table.
43 *
44 * Huntington has a single 8K filter table shared between all filter
45 * types and both ports.
46 */
47#define HUNT_FILTER_TBL_ROWS 8192
48
49#define EFX_EF10_FILTER_ID_INVALID 0xffff
50
51#define EFX_EF10_FILTER_DEV_UC_MAX 32
52#define EFX_EF10_FILTER_DEV_MC_MAX 256
53
54/* VLAN list entry */
55struct efx_ef10_vlan {
56 struct list_head list;
57 u16 vid;
58};
59
60enum efx_ef10_default_filters {
61 EFX_EF10_BCAST,
62 EFX_EF10_UCDEF,
63 EFX_EF10_MCDEF,
64 EFX_EF10_VXLAN4_UCDEF,
65 EFX_EF10_VXLAN4_MCDEF,
66 EFX_EF10_VXLAN6_UCDEF,
67 EFX_EF10_VXLAN6_MCDEF,
68 EFX_EF10_NVGRE4_UCDEF,
69 EFX_EF10_NVGRE4_MCDEF,
70 EFX_EF10_NVGRE6_UCDEF,
71 EFX_EF10_NVGRE6_MCDEF,
72 EFX_EF10_GENEVE4_UCDEF,
73 EFX_EF10_GENEVE4_MCDEF,
74 EFX_EF10_GENEVE6_UCDEF,
75 EFX_EF10_GENEVE6_MCDEF,
76
77 EFX_EF10_NUM_DEFAULT_FILTERS
78};
79
80/* Per-VLAN filters information */
81struct efx_ef10_filter_vlan {
82 struct list_head list;
83 u16 vid;
84 u16 uc[EFX_EF10_FILTER_DEV_UC_MAX];
85 u16 mc[EFX_EF10_FILTER_DEV_MC_MAX];
86 u16 default_filters[EFX_EF10_NUM_DEFAULT_FILTERS];
87};
88
89struct efx_ef10_dev_addr {
90 u8 addr[ETH_ALEN];
91};
92
93struct efx_ef10_filter_table {
94/* The MCDI match masks supported by this fw & hw, in order of priority */
95 u32 rx_match_mcdi_flags[
96 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM * 2];
97 unsigned int rx_match_count;
98
99 struct rw_semaphore lock; /* Protects entries */
100 struct {
101 unsigned long spec; /* pointer to spec plus flag bits */
102/* AUTO_OLD is used to mark and sweep MAC filters for the device address lists. */
103/* unused flag 1UL */
104#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
105#define EFX_EF10_FILTER_FLAGS 3UL
106 u64 handle; /* firmware handle */
107 } *entry;
108/* Shadow of net_device address lists, guarded by mac_lock */
109 struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
110 struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
111 int dev_uc_count;
112 int dev_mc_count;
113 bool uc_promisc;
114 bool mc_promisc;
115/* Whether in multicast promiscuous mode when last changed */
116 bool mc_promisc_last;
117 bool mc_overflow; /* Too many MC addrs; should always imply mc_promisc */
118 bool vlan_filter;
119 struct list_head vlan_list;
120};
121
122/* An arbitrary search limit for the software hash table */
123#define EFX_EF10_FILTER_SEARCH_LIMIT 200
124
125static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
126static void efx_ef10_filter_table_remove(struct efx_nic *efx);
127static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid);
128static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
129 struct efx_ef10_filter_vlan *vlan);
130static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid);
131static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading);
132
133static u32 efx_ef10_filter_get_unsafe_id(u32 filter_id)
134{
135 WARN_ON_ONCE(filter_id == EFX_EF10_FILTER_ID_INVALID);
136 return filter_id & (HUNT_FILTER_TBL_ROWS - 1);
137}
138
139static unsigned int efx_ef10_filter_get_unsafe_pri(u32 filter_id)
140{
141 return filter_id / (HUNT_FILTER_TBL_ROWS * 2);
142}
143
144static u32 efx_ef10_make_filter_id(unsigned int pri, u16 idx)
145{
146 return pri * HUNT_FILTER_TBL_ROWS * 2 + idx;
147}
148
149static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
150{
151 efx_dword_t reg;
152
153 efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS);
154 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
155 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
156}
157
158/* On all EF10s up to and including SFC9220 (Medford1), all PFs use BAR 0 for
159 * I/O space and BAR 2(&3) for memory. On SFC9250 (Medford2), there is no I/O
160 * bar; PFs use BAR 0/1 for memory.
161 */
162static unsigned int efx_ef10_pf_mem_bar(struct efx_nic *efx)
163{
164 switch (efx->pci_dev->device) {
165 case 0x0b03: /* SFC9250 PF */
166 return 0;
167 default:
168 return 2;
169 }
170}
171
172/* All VFs use BAR 0/1 for memory */
173static unsigned int efx_ef10_vf_mem_bar(struct efx_nic *efx)
174{
175 return 0;
176}
177
178static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
179{
180 int bar;
181
182 bar = efx->type->mem_bar(efx);
183 return resource_size(&efx->pci_dev->resource[bar]);
184}
185
186static bool efx_ef10_is_vf(struct efx_nic *efx)
187{
188 return efx->type->is_vf;
189}
190
191static int efx_ef10_get_pf_index(struct efx_nic *efx)
192{
193 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
194 struct efx_ef10_nic_data *nic_data = efx->nic_data;
195 size_t outlen;
196 int rc;
197
198 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
199 sizeof(outbuf), &outlen);
200 if (rc)
201 return rc;
202 if (outlen < sizeof(outbuf))
203 return -EIO;
204
205 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
206 return 0;
207}
208
209#ifdef CONFIG_SFC_SRIOV
210static int efx_ef10_get_vf_index(struct efx_nic *efx)
211{
212 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
213 struct efx_ef10_nic_data *nic_data = efx->nic_data;
214 size_t outlen;
215 int rc;
216
217 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
218 sizeof(outbuf), &outlen);
219 if (rc)
220 return rc;
221 if (outlen < sizeof(outbuf))
222 return -EIO;
223
224 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
225 return 0;
226}
227#endif
228
229static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
230{
231 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V4_OUT_LEN);
232 struct efx_ef10_nic_data *nic_data = efx->nic_data;
233 size_t outlen;
234 int rc;
235
236 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
237
238 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
239 outbuf, sizeof(outbuf), &outlen);
240 if (rc)
241 return rc;
242 if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
243 netif_err(efx, drv, efx->net_dev,
244 "unable to read datapath firmware capabilities\n");
245 return -EIO;
246 }
247
248 nic_data->datapath_caps =
249 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
250
251 if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) {
252 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
253 GET_CAPABILITIES_V2_OUT_FLAGS2);
254 nic_data->piobuf_size = MCDI_WORD(outbuf,
255 GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF);
256 } else {
257 nic_data->datapath_caps2 = 0;
258 nic_data->piobuf_size = ER_DZ_TX_PIOBUF_SIZE;
259 }
260
261 /* record the DPCPU firmware IDs to determine VEB vswitching support.
262 */
263 nic_data->rx_dpcpu_fw_id =
264 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
265 nic_data->tx_dpcpu_fw_id =
266 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
267
268 if (!(nic_data->datapath_caps &
269 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
270 netif_err(efx, probe, efx->net_dev,
271 "current firmware does not support an RX prefix\n");
272 return -ENODEV;
273 }
274
275 if (outlen >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) {
276 u8 vi_window_mode = MCDI_BYTE(outbuf,
277 GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
278
279 switch (vi_window_mode) {
280 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K:
281 efx->vi_stride = 8192;
282 break;
283 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K:
284 efx->vi_stride = 16384;
285 break;
286 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K:
287 efx->vi_stride = 65536;
288 break;
289 default:
290 netif_err(efx, probe, efx->net_dev,
291 "Unrecognised VI window mode %d\n",
292 vi_window_mode);
293 return -EIO;
294 }
295 netif_dbg(efx, probe, efx->net_dev, "vi_stride = %u\n",
296 efx->vi_stride);
297 } else {
298 /* keep default VI stride */
299 netif_dbg(efx, probe, efx->net_dev,
300 "firmware did not report VI window mode, assuming vi_stride = %u\n",
301 efx->vi_stride);
302 }
303
304 if (outlen >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
305 efx->num_mac_stats = MCDI_WORD(outbuf,
306 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
307 netif_dbg(efx, probe, efx->net_dev,
308 "firmware reports num_mac_stats = %u\n",
309 efx->num_mac_stats);
310 } else {
311 /* leave num_mac_stats as the default value, MC_CMD_MAC_NSTATS */
312 netif_dbg(efx, probe, efx->net_dev,
313 "firmware did not report num_mac_stats, assuming %u\n",
314 efx->num_mac_stats);
315 }
316
317 return 0;
318}
319
320static void efx_ef10_read_licensed_features(struct efx_nic *efx)
321{
322 MCDI_DECLARE_BUF(inbuf, MC_CMD_LICENSING_V3_IN_LEN);
323 MCDI_DECLARE_BUF(outbuf, MC_CMD_LICENSING_V3_OUT_LEN);
324 struct efx_ef10_nic_data *nic_data = efx->nic_data;
325 size_t outlen;
326 int rc;
327
328 MCDI_SET_DWORD(inbuf, LICENSING_V3_IN_OP,
329 MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE);
330 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_LICENSING_V3, inbuf, sizeof(inbuf),
331 outbuf, sizeof(outbuf), &outlen);
332 if (rc || (outlen < MC_CMD_LICENSING_V3_OUT_LEN))
333 return;
334
335 nic_data->licensed_features = MCDI_QWORD(outbuf,
336 LICENSING_V3_OUT_LICENSED_FEATURES);
337}
338
339static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
340{
341 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
342 int rc;
343
344 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
345 outbuf, sizeof(outbuf), NULL);
346 if (rc)
347 return rc;
348 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
349 return rc > 0 ? rc : -ERANGE;
350}
351
352static int efx_ef10_get_timer_workarounds(struct efx_nic *efx)
353{
354 struct efx_ef10_nic_data *nic_data = efx->nic_data;
355 unsigned int implemented;
356 unsigned int enabled;
357 int rc;
358
359 nic_data->workaround_35388 = false;
360 nic_data->workaround_61265 = false;
361
362 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
363
364 if (rc == -ENOSYS) {
365 /* Firmware without GET_WORKAROUNDS - not a problem. */
366 rc = 0;
367 } else if (rc == 0) {
368 /* Bug61265 workaround is always enabled if implemented. */
369 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265)
370 nic_data->workaround_61265 = true;
371
372 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
373 nic_data->workaround_35388 = true;
374 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
375 /* Workaround is implemented but not enabled.
376 * Try to enable it.
377 */
378 rc = efx_mcdi_set_workaround(efx,
379 MC_CMD_WORKAROUND_BUG35388,
380 true, NULL);
381 if (rc == 0)
382 nic_data->workaround_35388 = true;
383 /* If we failed to set the workaround just carry on. */
384 rc = 0;
385 }
386 }
387
388 netif_dbg(efx, probe, efx->net_dev,
389 "workaround for bug 35388 is %sabled\n",
390 nic_data->workaround_35388 ? "en" : "dis");
391 netif_dbg(efx, probe, efx->net_dev,
392 "workaround for bug 61265 is %sabled\n",
393 nic_data->workaround_61265 ? "en" : "dis");
394
395 return rc;
396}
397
398static void efx_ef10_process_timer_config(struct efx_nic *efx,
399 const efx_dword_t *data)
400{
401 unsigned int max_count;
402
403 if (EFX_EF10_WORKAROUND_61265(efx)) {
404 efx->timer_quantum_ns = MCDI_DWORD(data,
405 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS);
406 efx->timer_max_ns = MCDI_DWORD(data,
407 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS);
408 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
409 efx->timer_quantum_ns = MCDI_DWORD(data,
410 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT);
411 max_count = MCDI_DWORD(data,
412 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT);
413 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
414 } else {
415 efx->timer_quantum_ns = MCDI_DWORD(data,
416 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT);
417 max_count = MCDI_DWORD(data,
418 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT);
419 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
420 }
421
422 netif_dbg(efx, probe, efx->net_dev,
423 "got timer properties from MC: quantum %u ns; max %u ns\n",
424 efx->timer_quantum_ns, efx->timer_max_ns);
425}
426
427static int efx_ef10_get_timer_config(struct efx_nic *efx)
428{
429 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN);
430 int rc;
431
432 rc = efx_ef10_get_timer_workarounds(efx);
433 if (rc)
434 return rc;
435
436 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0,
437 outbuf, sizeof(outbuf), NULL);
438
439 if (rc == 0) {
440 efx_ef10_process_timer_config(efx, outbuf);
441 } else if (rc == -ENOSYS || rc == -EPERM) {
442 /* Not available - fall back to Huntington defaults. */
443 unsigned int quantum;
444
445 rc = efx_ef10_get_sysclk_freq(efx);
446 if (rc < 0)
447 return rc;
448
449 quantum = 1536000 / rc; /* 1536 cycles */
450 efx->timer_quantum_ns = quantum;
451 efx->timer_max_ns = efx->type->timer_period_max * quantum;
452 rc = 0;
453 } else {
454 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES,
455 MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN,
456 NULL, 0, rc);
457 }
458
459 return rc;
460}
461
462static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
463{
464 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
465 size_t outlen;
466 int rc;
467
468 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
469
470 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
471 outbuf, sizeof(outbuf), &outlen);
472 if (rc)
473 return rc;
474 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
475 return -EIO;
476
477 ether_addr_copy(mac_address,
478 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
479 return 0;
480}
481
482static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
483{
484 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
485 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
486 size_t outlen;
487 int num_addrs, rc;
488
489 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
490 EVB_PORT_ID_ASSIGNED);
491 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
492 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
493
494 if (rc)
495 return rc;
496 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
497 return -EIO;
498
499 num_addrs = MCDI_DWORD(outbuf,
500 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
501
502 WARN_ON(num_addrs != 1);
503
504 ether_addr_copy(mac_address,
505 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
506
507 return 0;
508}
509
510static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
511 struct device_attribute *attr,
512 char *buf)
513{
514 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
515
516 return sprintf(buf, "%d\n",
517 ((efx->mcdi->fn_flags) &
518 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
519 ? 1 : 0);
520}
521
522static ssize_t efx_ef10_show_primary_flag(struct device *dev,
523 struct device_attribute *attr,
524 char *buf)
525{
526 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
527
528 return sprintf(buf, "%d\n",
529 ((efx->mcdi->fn_flags) &
530 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
531 ? 1 : 0);
532}
533
534static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid)
535{
536 struct efx_ef10_nic_data *nic_data = efx->nic_data;
537 struct efx_ef10_vlan *vlan;
538
539 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
540
541 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
542 if (vlan->vid == vid)
543 return vlan;
544 }
545
546 return NULL;
547}
548
549static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid)
550{
551 struct efx_ef10_nic_data *nic_data = efx->nic_data;
552 struct efx_ef10_vlan *vlan;
553 int rc;
554
555 mutex_lock(&nic_data->vlan_lock);
556
557 vlan = efx_ef10_find_vlan(efx, vid);
558 if (vlan) {
559 /* We add VID 0 on init. 8021q adds it on module init
560 * for all interfaces with VLAN filtring feature.
561 */
562 if (vid == 0)
563 goto done_unlock;
564 netif_warn(efx, drv, efx->net_dev,
565 "VLAN %u already added\n", vid);
566 rc = -EALREADY;
567 goto fail_exist;
568 }
569
570 rc = -ENOMEM;
571 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
572 if (!vlan)
573 goto fail_alloc;
574
575 vlan->vid = vid;
576
577 list_add_tail(&vlan->list, &nic_data->vlan_list);
578
579 if (efx->filter_state) {
580 mutex_lock(&efx->mac_lock);
581 down_write(&efx->filter_sem);
582 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
583 up_write(&efx->filter_sem);
584 mutex_unlock(&efx->mac_lock);
585 if (rc)
586 goto fail_filter_add_vlan;
587 }
588
589done_unlock:
590 mutex_unlock(&nic_data->vlan_lock);
591 return 0;
592
593fail_filter_add_vlan:
594 list_del(&vlan->list);
595 kfree(vlan);
596fail_alloc:
597fail_exist:
598 mutex_unlock(&nic_data->vlan_lock);
599 return rc;
600}
601
602static void efx_ef10_del_vlan_internal(struct efx_nic *efx,
603 struct efx_ef10_vlan *vlan)
604{
605 struct efx_ef10_nic_data *nic_data = efx->nic_data;
606
607 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
608
609 if (efx->filter_state) {
610 down_write(&efx->filter_sem);
611 efx_ef10_filter_del_vlan(efx, vlan->vid);
612 up_write(&efx->filter_sem);
613 }
614
615 list_del(&vlan->list);
616 kfree(vlan);
617}
618
619static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid)
620{
621 struct efx_ef10_nic_data *nic_data = efx->nic_data;
622 struct efx_ef10_vlan *vlan;
623 int rc = 0;
624
625 /* 8021q removes VID 0 on module unload for all interfaces
626 * with VLAN filtering feature. We need to keep it to receive
627 * untagged traffic.
628 */
629 if (vid == 0)
630 return 0;
631
632 mutex_lock(&nic_data->vlan_lock);
633
634 vlan = efx_ef10_find_vlan(efx, vid);
635 if (!vlan) {
636 netif_err(efx, drv, efx->net_dev,
637 "VLAN %u to be deleted not found\n", vid);
638 rc = -ENOENT;
639 } else {
640 efx_ef10_del_vlan_internal(efx, vlan);
641 }
642
643 mutex_unlock(&nic_data->vlan_lock);
644
645 return rc;
646}
647
648static void efx_ef10_cleanup_vlans(struct efx_nic *efx)
649{
650 struct efx_ef10_nic_data *nic_data = efx->nic_data;
651 struct efx_ef10_vlan *vlan, *next_vlan;
652
653 mutex_lock(&nic_data->vlan_lock);
654 list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list)
655 efx_ef10_del_vlan_internal(efx, vlan);
656 mutex_unlock(&nic_data->vlan_lock);
657}
658
659static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
660 NULL);
661static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
662
663static int efx_ef10_probe(struct efx_nic *efx)
664{
665 struct efx_ef10_nic_data *nic_data;
666 int i, rc;
667
668 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
669 if (!nic_data)
670 return -ENOMEM;
671 efx->nic_data = nic_data;
672
673 /* we assume later that we can copy from this buffer in dwords */
674 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
675
676 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
677 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
678 if (rc)
679 goto fail1;
680
681 /* Get the MC's warm boot count. In case it's rebooting right
682 * now, be prepared to retry.
683 */
684 i = 0;
685 for (;;) {
686 rc = efx_ef10_get_warm_boot_count(efx);
687 if (rc >= 0)
688 break;
689 if (++i == 5)
690 goto fail2;
691 ssleep(1);
692 }
693 nic_data->warm_boot_count = rc;
694
695 efx->rss_context.context_id = EFX_EF10_RSS_CONTEXT_INVALID;
696
697 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
698
699 /* In case we're recovering from a crash (kexec), we want to
700 * cancel any outstanding request by the previous user of this
701 * function. We send a special message using the least
702 * significant bits of the 'high' (doorbell) register.
703 */
704 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
705
706 rc = efx_mcdi_init(efx);
707 if (rc)
708 goto fail2;
709
710 mutex_init(&nic_data->udp_tunnels_lock);
711
712 /* Reset (most) configuration for this function */
713 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
714 if (rc)
715 goto fail3;
716
717 /* Enable event logging */
718 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
719 if (rc)
720 goto fail3;
721
722 rc = device_create_file(&efx->pci_dev->dev,
723 &dev_attr_link_control_flag);
724 if (rc)
725 goto fail3;
726
727 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
728 if (rc)
729 goto fail4;
730
731 rc = efx_ef10_get_pf_index(efx);
732 if (rc)
733 goto fail5;
734
735 rc = efx_ef10_init_datapath_caps(efx);
736 if (rc < 0)
737 goto fail5;
738
739 efx_ef10_read_licensed_features(efx);
740
741 /* We can have one VI for each vi_stride-byte region.
742 * However, until we use TX option descriptors we need two TX queues
743 * per channel.
744 */
745 efx->max_channels = min_t(unsigned int,
746 EFX_MAX_CHANNELS,
747 efx_ef10_mem_map_size(efx) /
748 (efx->vi_stride * EFX_TXQ_TYPES));
749 efx->max_tx_channels = efx->max_channels;
750 if (WARN_ON(efx->max_channels == 0)) {
751 rc = -EIO;
752 goto fail5;
753 }
754
755 efx->rx_packet_len_offset =
756 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
757
758 if (nic_data->datapath_caps &
759 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN))
760 efx->net_dev->hw_features |= NETIF_F_RXFCS;
761
762 rc = efx_mcdi_port_get_number(efx);
763 if (rc < 0)
764 goto fail5;
765 efx->port_num = rc;
766
767 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
768 if (rc)
769 goto fail5;
770
771 rc = efx_ef10_get_timer_config(efx);
772 if (rc < 0)
773 goto fail5;
774
775 rc = efx_mcdi_mon_probe(efx);
776 if (rc && rc != -EPERM)
777 goto fail5;
778
779 efx_ptp_defer_probe_with_channel(efx);
780
781#ifdef CONFIG_SFC_SRIOV
782 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
783 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
784 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
785
786 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
787 } else
788#endif
789 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
790
791 INIT_LIST_HEAD(&nic_data->vlan_list);
792 mutex_init(&nic_data->vlan_lock);
793
794 /* Add unspecified VID to support VLAN filtering being disabled */
795 rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
796 if (rc)
797 goto fail_add_vid_unspec;
798
799 /* If VLAN filtering is enabled, we need VID 0 to get untagged
800 * traffic. It is added automatically if 8021q module is loaded,
801 * but we can't rely on it since module may be not loaded.
802 */
803 rc = efx_ef10_add_vlan(efx, 0);
804 if (rc)
805 goto fail_add_vid_0;
806
807 return 0;
808
809fail_add_vid_0:
810 efx_ef10_cleanup_vlans(efx);
811fail_add_vid_unspec:
812 mutex_destroy(&nic_data->vlan_lock);
813 efx_ptp_remove(efx);
814 efx_mcdi_mon_remove(efx);
815fail5:
816 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
817fail4:
818 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
819fail3:
820 efx_mcdi_detach(efx);
821
822 mutex_lock(&nic_data->udp_tunnels_lock);
823 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels));
824 (void)efx_ef10_set_udp_tnl_ports(efx, true);
825 mutex_unlock(&nic_data->udp_tunnels_lock);
826 mutex_destroy(&nic_data->udp_tunnels_lock);
827
828 efx_mcdi_fini(efx);
829fail2:
830 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
831fail1:
832 kfree(nic_data);
833 efx->nic_data = NULL;
834 return rc;
835}
836
837static int efx_ef10_free_vis(struct efx_nic *efx)
838{
839 MCDI_DECLARE_BUF_ERR(outbuf);
840 size_t outlen;
841 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
842 outbuf, sizeof(outbuf), &outlen);
843
844 /* -EALREADY means nothing to free, so ignore */
845 if (rc == -EALREADY)
846 rc = 0;
847 if (rc)
848 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
849 rc);
850 return rc;
851}
852
853#ifdef EFX_USE_PIO
854
855static void efx_ef10_free_piobufs(struct efx_nic *efx)
856{
857 struct efx_ef10_nic_data *nic_data = efx->nic_data;
858 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
859 unsigned int i;
860 int rc;
861
862 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
863
864 for (i = 0; i < nic_data->n_piobufs; i++) {
865 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
866 nic_data->piobuf_handle[i]);
867 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
868 NULL, 0, NULL);
869 WARN_ON(rc);
870 }
871
872 nic_data->n_piobufs = 0;
873}
874
875static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
876{
877 struct efx_ef10_nic_data *nic_data = efx->nic_data;
878 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
879 unsigned int i;
880 size_t outlen;
881 int rc = 0;
882
883 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
884
885 for (i = 0; i < n; i++) {
886 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
887 outbuf, sizeof(outbuf), &outlen);
888 if (rc) {
889 /* Don't display the MC error if we didn't have space
890 * for a VF.
891 */
892 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC))
893 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF,
894 0, outbuf, outlen, rc);
895 break;
896 }
897 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
898 rc = -EIO;
899 break;
900 }
901 nic_data->piobuf_handle[i] =
902 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
903 netif_dbg(efx, probe, efx->net_dev,
904 "allocated PIO buffer %u handle %x\n", i,
905 nic_data->piobuf_handle[i]);
906 }
907
908 nic_data->n_piobufs = i;
909 if (rc)
910 efx_ef10_free_piobufs(efx);
911 return rc;
912}
913
914static int efx_ef10_link_piobufs(struct efx_nic *efx)
915{
916 struct efx_ef10_nic_data *nic_data = efx->nic_data;
917 MCDI_DECLARE_BUF(inbuf, MC_CMD_LINK_PIOBUF_IN_LEN);
918 struct efx_channel *channel;
919 struct efx_tx_queue *tx_queue;
920 unsigned int offset, index;
921 int rc;
922
923 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
924 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
925
926 /* Link a buffer to each VI in the write-combining mapping */
927 for (index = 0; index < nic_data->n_piobufs; ++index) {
928 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
929 nic_data->piobuf_handle[index]);
930 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
931 nic_data->pio_write_vi_base + index);
932 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
933 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
934 NULL, 0, NULL);
935 if (rc) {
936 netif_err(efx, drv, efx->net_dev,
937 "failed to link VI %u to PIO buffer %u (%d)\n",
938 nic_data->pio_write_vi_base + index, index,
939 rc);
940 goto fail;
941 }
942 netif_dbg(efx, probe, efx->net_dev,
943 "linked VI %u to PIO buffer %u\n",
944 nic_data->pio_write_vi_base + index, index);
945 }
946
947 /* Link a buffer to each TX queue */
948 efx_for_each_channel(channel, efx) {
949 /* Extra channels, even those with TXQs (PTP), do not require
950 * PIO resources.
951 */
952 if (!channel->type->want_pio)
953 continue;
954 efx_for_each_channel_tx_queue(tx_queue, channel) {
955 /* We assign the PIO buffers to queues in
956 * reverse order to allow for the following
957 * special case.
958 */
959 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
960 tx_queue->channel->channel - 1) *
961 efx_piobuf_size);
962 index = offset / nic_data->piobuf_size;
963 offset = offset % nic_data->piobuf_size;
964
965 /* When the host page size is 4K, the first
966 * host page in the WC mapping may be within
967 * the same VI page as the last TX queue. We
968 * can only link one buffer to each VI.
969 */
970 if (tx_queue->queue == nic_data->pio_write_vi_base) {
971 BUG_ON(index != 0);
972 rc = 0;
973 } else {
974 MCDI_SET_DWORD(inbuf,
975 LINK_PIOBUF_IN_PIOBUF_HANDLE,
976 nic_data->piobuf_handle[index]);
977 MCDI_SET_DWORD(inbuf,
978 LINK_PIOBUF_IN_TXQ_INSTANCE,
979 tx_queue->queue);
980 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
981 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
982 NULL, 0, NULL);
983 }
984
985 if (rc) {
986 /* This is non-fatal; the TX path just
987 * won't use PIO for this queue
988 */
989 netif_err(efx, drv, efx->net_dev,
990 "failed to link VI %u to PIO buffer %u (%d)\n",
991 tx_queue->queue, index, rc);
992 tx_queue->piobuf = NULL;
993 } else {
994 tx_queue->piobuf =
995 nic_data->pio_write_base +
996 index * efx->vi_stride + offset;
997 tx_queue->piobuf_offset = offset;
998 netif_dbg(efx, probe, efx->net_dev,
999 "linked VI %u to PIO buffer %u offset %x addr %p\n",
1000 tx_queue->queue, index,
1001 tx_queue->piobuf_offset,
1002 tx_queue->piobuf);
1003 }
1004 }
1005 }
1006
1007 return 0;
1008
1009fail:
1010 /* inbuf was defined for MC_CMD_LINK_PIOBUF. We can use the same
1011 * buffer for MC_CMD_UNLINK_PIOBUF because it's shorter.
1012 */
1013 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_IN_LEN < MC_CMD_UNLINK_PIOBUF_IN_LEN);
1014 while (index--) {
1015 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
1016 nic_data->pio_write_vi_base + index);
1017 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
1018 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
1019 NULL, 0, NULL);
1020 }
1021 return rc;
1022}
1023
1024static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
1025{
1026 struct efx_channel *channel;
1027 struct efx_tx_queue *tx_queue;
1028
1029 /* All our existing PIO buffers went away */
1030 efx_for_each_channel(channel, efx)
1031 efx_for_each_channel_tx_queue(tx_queue, channel)
1032 tx_queue->piobuf = NULL;
1033}
1034
1035#else /* !EFX_USE_PIO */
1036
1037static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
1038{
1039 return n == 0 ? 0 : -ENOBUFS;
1040}
1041
1042static int efx_ef10_link_piobufs(struct efx_nic *efx)
1043{
1044 return 0;
1045}
1046
1047static void efx_ef10_free_piobufs(struct efx_nic *efx)
1048{
1049}
1050
1051static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
1052{
1053}
1054
1055#endif /* EFX_USE_PIO */
1056
1057static void efx_ef10_remove(struct efx_nic *efx)
1058{
1059 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1060 int rc;
1061
1062#ifdef CONFIG_SFC_SRIOV
1063 struct efx_ef10_nic_data *nic_data_pf;
1064 struct pci_dev *pci_dev_pf;
1065 struct efx_nic *efx_pf;
1066 struct ef10_vf *vf;
1067
1068 if (efx->pci_dev->is_virtfn) {
1069 pci_dev_pf = efx->pci_dev->physfn;
1070 if (pci_dev_pf) {
1071 efx_pf = pci_get_drvdata(pci_dev_pf);
1072 nic_data_pf = efx_pf->nic_data;
1073 vf = nic_data_pf->vf + nic_data->vf_index;
1074 vf->efx = NULL;
1075 } else
1076 netif_info(efx, drv, efx->net_dev,
1077 "Could not get the PF id from VF\n");
1078 }
1079#endif
1080
1081 efx_ef10_cleanup_vlans(efx);
1082 mutex_destroy(&nic_data->vlan_lock);
1083
1084 efx_ptp_remove(efx);
1085
1086 efx_mcdi_mon_remove(efx);
1087
1088 efx_ef10_rx_free_indir_table(efx);
1089
1090 if (nic_data->wc_membase)
1091 iounmap(nic_data->wc_membase);
1092
1093 rc = efx_ef10_free_vis(efx);
1094 WARN_ON(rc != 0);
1095
1096 if (!nic_data->must_restore_piobufs)
1097 efx_ef10_free_piobufs(efx);
1098
1099 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
1100 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
1101
1102 efx_mcdi_detach(efx);
1103
1104 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels));
1105 mutex_lock(&nic_data->udp_tunnels_lock);
1106 (void)efx_ef10_set_udp_tnl_ports(efx, true);
1107 mutex_unlock(&nic_data->udp_tunnels_lock);
1108
1109 mutex_destroy(&nic_data->udp_tunnels_lock);
1110
1111 efx_mcdi_fini(efx);
1112 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
1113 kfree(nic_data);
1114}
1115
1116static int efx_ef10_probe_pf(struct efx_nic *efx)
1117{
1118 return efx_ef10_probe(efx);
1119}
1120
1121int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id,
1122 u32 *port_flags, u32 *vadaptor_flags,
1123 unsigned int *vlan_tags)
1124{
1125 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1126 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN);
1127 MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN);
1128 size_t outlen;
1129 int rc;
1130
1131 if (nic_data->datapath_caps &
1132 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) {
1133 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID,
1134 port_id);
1135
1136 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf),
1137 outbuf, sizeof(outbuf), &outlen);
1138 if (rc)
1139 return rc;
1140
1141 if (outlen < sizeof(outbuf)) {
1142 rc = -EIO;
1143 return rc;
1144 }
1145 }
1146
1147 if (port_flags)
1148 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS);
1149 if (vadaptor_flags)
1150 *vadaptor_flags =
1151 MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS);
1152 if (vlan_tags)
1153 *vlan_tags =
1154 MCDI_DWORD(outbuf,
1155 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS);
1156
1157 return 0;
1158}
1159
1160int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
1161{
1162 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
1163
1164 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
1165 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
1166 NULL, 0, NULL);
1167}
1168
1169int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
1170{
1171 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
1172
1173 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
1174 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
1175 NULL, 0, NULL);
1176}
1177
1178int efx_ef10_vport_add_mac(struct efx_nic *efx,
1179 unsigned int port_id, u8 *mac)
1180{
1181 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
1182
1183 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
1184 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
1185
1186 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
1187 sizeof(inbuf), NULL, 0, NULL);
1188}
1189
1190int efx_ef10_vport_del_mac(struct efx_nic *efx,
1191 unsigned int port_id, u8 *mac)
1192{
1193 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
1194
1195 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
1196 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
1197
1198 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
1199 sizeof(inbuf), NULL, 0, NULL);
1200}
1201
1202#ifdef CONFIG_SFC_SRIOV
1203static int efx_ef10_probe_vf(struct efx_nic *efx)
1204{
1205 int rc;
1206 struct pci_dev *pci_dev_pf;
1207
1208 /* If the parent PF has no VF data structure, it doesn't know about this
1209 * VF so fail probe. The VF needs to be re-created. This can happen
1210 * if the PF driver is unloaded while the VF is assigned to a guest.
1211 */
1212 pci_dev_pf = efx->pci_dev->physfn;
1213 if (pci_dev_pf) {
1214 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
1215 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
1216
1217 if (!nic_data_pf->vf) {
1218 netif_info(efx, drv, efx->net_dev,
1219 "The VF cannot link to its parent PF; "
1220 "please destroy and re-create the VF\n");
1221 return -EBUSY;
1222 }
1223 }
1224
1225 rc = efx_ef10_probe(efx);
1226 if (rc)
1227 return rc;
1228
1229 rc = efx_ef10_get_vf_index(efx);
1230 if (rc)
1231 goto fail;
1232
1233 if (efx->pci_dev->is_virtfn) {
1234 if (efx->pci_dev->physfn) {
1235 struct efx_nic *efx_pf =
1236 pci_get_drvdata(efx->pci_dev->physfn);
1237 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
1238 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1239
1240 nic_data_p->vf[nic_data->vf_index].efx = efx;
1241 nic_data_p->vf[nic_data->vf_index].pci_dev =
1242 efx->pci_dev;
1243 } else
1244 netif_info(efx, drv, efx->net_dev,
1245 "Could not get the PF id from VF\n");
1246 }
1247
1248 return 0;
1249
1250fail:
1251 efx_ef10_remove(efx);
1252 return rc;
1253}
1254#else
1255static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
1256{
1257 return 0;
1258}
1259#endif
1260
1261static int efx_ef10_alloc_vis(struct efx_nic *efx,
1262 unsigned int min_vis, unsigned int max_vis)
1263{
1264 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
1265 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
1266 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1267 size_t outlen;
1268 int rc;
1269
1270 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
1271 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
1272 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
1273 outbuf, sizeof(outbuf), &outlen);
1274 if (rc != 0)
1275 return rc;
1276
1277 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
1278 return -EIO;
1279
1280 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
1281 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
1282
1283 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
1284 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
1285 return 0;
1286}
1287
1288/* Note that the failure path of this function does not free
1289 * resources, as this will be done by efx_ef10_remove().
1290 */
1291static int efx_ef10_dimension_resources(struct efx_nic *efx)
1292{
1293 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1294 unsigned int uc_mem_map_size, wc_mem_map_size;
1295 unsigned int min_vis = max(EFX_TXQ_TYPES,
1296 efx_separate_tx_channels ? 2 : 1);
1297 unsigned int channel_vis, pio_write_vi_base, max_vis;
1298 void __iomem *membase;
1299 int rc;
1300
1301 channel_vis = max(efx->n_channels,
1302 (efx->n_tx_channels + efx->n_extra_tx_channels) *
1303 EFX_TXQ_TYPES);
1304
1305#ifdef EFX_USE_PIO
1306 /* Try to allocate PIO buffers if wanted and if the full
1307 * number of PIO buffers would be sufficient to allocate one
1308 * copy-buffer per TX channel. Failure is non-fatal, as there
1309 * are only a small number of PIO buffers shared between all
1310 * functions of the controller.
1311 */
1312 if (efx_piobuf_size != 0 &&
1313 nic_data->piobuf_size / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
1314 efx->n_tx_channels) {
1315 unsigned int n_piobufs =
1316 DIV_ROUND_UP(efx->n_tx_channels,
1317 nic_data->piobuf_size / efx_piobuf_size);
1318
1319 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
1320 if (rc == -ENOSPC)
1321 netif_dbg(efx, probe, efx->net_dev,
1322 "out of PIO buffers; cannot allocate more\n");
1323 else if (rc == -EPERM)
1324 netif_dbg(efx, probe, efx->net_dev,
1325 "not permitted to allocate PIO buffers\n");
1326 else if (rc)
1327 netif_err(efx, probe, efx->net_dev,
1328 "failed to allocate PIO buffers (%d)\n", rc);
1329 else
1330 netif_dbg(efx, probe, efx->net_dev,
1331 "allocated %u PIO buffers\n", n_piobufs);
1332 }
1333#else
1334 nic_data->n_piobufs = 0;
1335#endif
1336
1337 /* PIO buffers should be mapped with write-combining enabled,
1338 * and we want to make single UC and WC mappings rather than
1339 * several of each (in fact that's the only option if host
1340 * page size is >4K). So we may allocate some extra VIs just
1341 * for writing PIO buffers through.
1342 *
1343 * The UC mapping contains (channel_vis - 1) complete VIs and the
1344 * first 4K of the next VI. Then the WC mapping begins with
1345 * the remainder of this last VI.
1346 */
1347 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * efx->vi_stride +
1348 ER_DZ_TX_PIOBUF);
1349 if (nic_data->n_piobufs) {
1350 /* pio_write_vi_base rounds down to give the number of complete
1351 * VIs inside the UC mapping.
1352 */
1353 pio_write_vi_base = uc_mem_map_size / efx->vi_stride;
1354 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
1355 nic_data->n_piobufs) *
1356 efx->vi_stride) -
1357 uc_mem_map_size);
1358 max_vis = pio_write_vi_base + nic_data->n_piobufs;
1359 } else {
1360 pio_write_vi_base = 0;
1361 wc_mem_map_size = 0;
1362 max_vis = channel_vis;
1363 }
1364
1365 /* In case the last attached driver failed to free VIs, do it now */
1366 rc = efx_ef10_free_vis(efx);
1367 if (rc != 0)
1368 return rc;
1369
1370 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
1371 if (rc != 0)
1372 return rc;
1373
1374 if (nic_data->n_allocated_vis < channel_vis) {
1375 netif_info(efx, drv, efx->net_dev,
1376 "Could not allocate enough VIs to satisfy RSS"
1377 " requirements. Performance may not be optimal.\n");
1378 /* We didn't get the VIs to populate our channels.
1379 * We could keep what we got but then we'd have more
1380 * interrupts than we need.
1381 * Instead calculate new max_channels and restart
1382 */
1383 efx->max_channels = nic_data->n_allocated_vis;
1384 efx->max_tx_channels =
1385 nic_data->n_allocated_vis / EFX_TXQ_TYPES;
1386
1387 efx_ef10_free_vis(efx);
1388 return -EAGAIN;
1389 }
1390
1391 /* If we didn't get enough VIs to map all the PIO buffers, free the
1392 * PIO buffers
1393 */
1394 if (nic_data->n_piobufs &&
1395 nic_data->n_allocated_vis <
1396 pio_write_vi_base + nic_data->n_piobufs) {
1397 netif_dbg(efx, probe, efx->net_dev,
1398 "%u VIs are not sufficient to map %u PIO buffers\n",
1399 nic_data->n_allocated_vis, nic_data->n_piobufs);
1400 efx_ef10_free_piobufs(efx);
1401 }
1402
1403 /* Shrink the original UC mapping of the memory BAR */
1404 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
1405 if (!membase) {
1406 netif_err(efx, probe, efx->net_dev,
1407 "could not shrink memory BAR to %x\n",
1408 uc_mem_map_size);
1409 return -ENOMEM;
1410 }
1411 iounmap(efx->membase);
1412 efx->membase = membase;
1413
1414 /* Set up the WC mapping if needed */
1415 if (wc_mem_map_size) {
1416 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
1417 uc_mem_map_size,
1418 wc_mem_map_size);
1419 if (!nic_data->wc_membase) {
1420 netif_err(efx, probe, efx->net_dev,
1421 "could not allocate WC mapping of size %x\n",
1422 wc_mem_map_size);
1423 return -ENOMEM;
1424 }
1425 nic_data->pio_write_vi_base = pio_write_vi_base;
1426 nic_data->pio_write_base =
1427 nic_data->wc_membase +
1428 (pio_write_vi_base * efx->vi_stride + ER_DZ_TX_PIOBUF -
1429 uc_mem_map_size);
1430
1431 rc = efx_ef10_link_piobufs(efx);
1432 if (rc)
1433 efx_ef10_free_piobufs(efx);
1434 }
1435
1436 netif_dbg(efx, probe, efx->net_dev,
1437 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
1438 &efx->membase_phys, efx->membase, uc_mem_map_size,
1439 nic_data->wc_membase, wc_mem_map_size);
1440
1441 return 0;
1442}
1443
1444static int efx_ef10_init_nic(struct efx_nic *efx)
1445{
1446 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1447 int rc;
1448
1449 if (nic_data->must_check_datapath_caps) {
1450 rc = efx_ef10_init_datapath_caps(efx);
1451 if (rc)
1452 return rc;
1453 nic_data->must_check_datapath_caps = false;
1454 }
1455
1456 if (nic_data->must_realloc_vis) {
1457 /* We cannot let the number of VIs change now */
1458 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
1459 nic_data->n_allocated_vis);
1460 if (rc)
1461 return rc;
1462 nic_data->must_realloc_vis = false;
1463 }
1464
1465 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
1466 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
1467 if (rc == 0) {
1468 rc = efx_ef10_link_piobufs(efx);
1469 if (rc)
1470 efx_ef10_free_piobufs(efx);
1471 }
1472
1473 /* Log an error on failure, but this is non-fatal.
1474 * Permission errors are less important - we've presumably
1475 * had the PIO buffer licence removed.
1476 */
1477 if (rc == -EPERM)
1478 netif_dbg(efx, drv, efx->net_dev,
1479 "not permitted to restore PIO buffers\n");
1480 else if (rc)
1481 netif_err(efx, drv, efx->net_dev,
1482 "failed to restore PIO buffers (%d)\n", rc);
1483 nic_data->must_restore_piobufs = false;
1484 }
1485
1486 /* don't fail init if RSS setup doesn't work */
1487 rc = efx->type->rx_push_rss_config(efx, false,
1488 efx->rss_context.rx_indir_table, NULL);
1489
1490 return 0;
1491}
1492
1493static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
1494{
1495 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1496#ifdef CONFIG_SFC_SRIOV
1497 unsigned int i;
1498#endif
1499
1500 /* All our allocations have been reset */
1501 nic_data->must_realloc_vis = true;
1502 nic_data->must_restore_rss_contexts = true;
1503 nic_data->must_restore_filters = true;
1504 nic_data->must_restore_piobufs = true;
1505 efx_ef10_forget_old_piobufs(efx);
1506 efx->rss_context.context_id = EFX_EF10_RSS_CONTEXT_INVALID;
1507
1508 /* Driver-created vswitches and vports must be re-created */
1509 nic_data->must_probe_vswitching = true;
1510 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1511#ifdef CONFIG_SFC_SRIOV
1512 if (nic_data->vf)
1513 for (i = 0; i < efx->vf_count; i++)
1514 nic_data->vf[i].vport_id = 0;
1515#endif
1516}
1517
1518static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1519{
1520 if (reason == RESET_TYPE_MC_FAILURE)
1521 return RESET_TYPE_DATAPATH;
1522
1523 return efx_mcdi_map_reset_reason(reason);
1524}
1525
1526static int efx_ef10_map_reset_flags(u32 *flags)
1527{
1528 enum {
1529 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1530 ETH_RESET_SHARED_SHIFT),
1531 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1532 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1533 ETH_RESET_PHY | ETH_RESET_MGMT) <<
1534 ETH_RESET_SHARED_SHIFT)
1535 };
1536
1537 /* We assume for now that our PCI function is permitted to
1538 * reset everything.
1539 */
1540
1541 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1542 *flags &= ~EF10_RESET_MC;
1543 return RESET_TYPE_WORLD;
1544 }
1545
1546 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1547 *flags &= ~EF10_RESET_PORT;
1548 return RESET_TYPE_ALL;
1549 }
1550
1551 /* no invisible reset implemented */
1552
1553 return -EINVAL;
1554}
1555
1556static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1557{
1558 int rc = efx_mcdi_reset(efx, reset_type);
1559
1560 /* Unprivileged functions return -EPERM, but need to return success
1561 * here so that the datapath is brought back up.
1562 */
1563 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1564 rc = 0;
1565
1566 /* If it was a port reset, trigger reallocation of MC resources.
1567 * Note that on an MC reset nothing needs to be done now because we'll
1568 * detect the MC reset later and handle it then.
1569 * For an FLR, we never get an MC reset event, but the MC has reset all
1570 * resources assigned to us, so we have to trigger reallocation now.
1571 */
1572 if ((reset_type == RESET_TYPE_ALL ||
1573 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
1574 efx_ef10_reset_mc_allocations(efx);
1575 return rc;
1576}
1577
1578#define EF10_DMA_STAT(ext_name, mcdi_name) \
1579 [EF10_STAT_ ## ext_name] = \
1580 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1581#define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
1582 [EF10_STAT_ ## int_name] = \
1583 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1584#define EF10_OTHER_STAT(ext_name) \
1585 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1586#define GENERIC_SW_STAT(ext_name) \
1587 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1588
1589static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
1590 EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1591 EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1592 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1593 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1594 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1595 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1596 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1597 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1598 EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1599 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1600 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1601 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1602 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1603 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1604 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1605 EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1606 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1607 EF10_OTHER_STAT(port_rx_good_bytes),
1608 EF10_OTHER_STAT(port_rx_bad_bytes),
1609 EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1610 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1611 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1612 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1613 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1614 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1615 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1616 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1617 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1618 EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1619 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1620 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1621 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1622 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1623 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1624 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1625 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1626 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1627 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1628 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1629 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1630 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
1631 GENERIC_SW_STAT(rx_nodesc_trunc),
1632 GENERIC_SW_STAT(rx_noskb_drops),
1633 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1634 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1635 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1636 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1637 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1638 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1639 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1640 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1641 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1642 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1643 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1644 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
1645 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1646 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1647 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1648 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1649 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1650 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1651 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1652 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1653 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1654 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1655 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1656 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1657 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1658 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1659 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1660 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1661 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1662 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
1663 EF10_DMA_STAT(fec_uncorrected_errors, FEC_UNCORRECTED_ERRORS),
1664 EF10_DMA_STAT(fec_corrected_errors, FEC_CORRECTED_ERRORS),
1665 EF10_DMA_STAT(fec_corrected_symbols_lane0, FEC_CORRECTED_SYMBOLS_LANE0),
1666 EF10_DMA_STAT(fec_corrected_symbols_lane1, FEC_CORRECTED_SYMBOLS_LANE1),
1667 EF10_DMA_STAT(fec_corrected_symbols_lane2, FEC_CORRECTED_SYMBOLS_LANE2),
1668 EF10_DMA_STAT(fec_corrected_symbols_lane3, FEC_CORRECTED_SYMBOLS_LANE3),
1669 EF10_DMA_STAT(ctpio_vi_busy_fallback, CTPIO_VI_BUSY_FALLBACK),
1670 EF10_DMA_STAT(ctpio_long_write_success, CTPIO_LONG_WRITE_SUCCESS),
1671 EF10_DMA_STAT(ctpio_missing_dbell_fail, CTPIO_MISSING_DBELL_FAIL),
1672 EF10_DMA_STAT(ctpio_overflow_fail, CTPIO_OVERFLOW_FAIL),
1673 EF10_DMA_STAT(ctpio_underflow_fail, CTPIO_UNDERFLOW_FAIL),
1674 EF10_DMA_STAT(ctpio_timeout_fail, CTPIO_TIMEOUT_FAIL),
1675 EF10_DMA_STAT(ctpio_noncontig_wr_fail, CTPIO_NONCONTIG_WR_FAIL),
1676 EF10_DMA_STAT(ctpio_frm_clobber_fail, CTPIO_FRM_CLOBBER_FAIL),
1677 EF10_DMA_STAT(ctpio_invalid_wr_fail, CTPIO_INVALID_WR_FAIL),
1678 EF10_DMA_STAT(ctpio_vi_clobber_fallback, CTPIO_VI_CLOBBER_FALLBACK),
1679 EF10_DMA_STAT(ctpio_unqualified_fallback, CTPIO_UNQUALIFIED_FALLBACK),
1680 EF10_DMA_STAT(ctpio_runt_fallback, CTPIO_RUNT_FALLBACK),
1681 EF10_DMA_STAT(ctpio_success, CTPIO_SUCCESS),
1682 EF10_DMA_STAT(ctpio_fallback, CTPIO_FALLBACK),
1683 EF10_DMA_STAT(ctpio_poison, CTPIO_POISON),
1684 EF10_DMA_STAT(ctpio_erase, CTPIO_ERASE),
1685};
1686
1687#define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1688 (1ULL << EF10_STAT_port_tx_packets) | \
1689 (1ULL << EF10_STAT_port_tx_pause) | \
1690 (1ULL << EF10_STAT_port_tx_unicast) | \
1691 (1ULL << EF10_STAT_port_tx_multicast) | \
1692 (1ULL << EF10_STAT_port_tx_broadcast) | \
1693 (1ULL << EF10_STAT_port_rx_bytes) | \
1694 (1ULL << \
1695 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1696 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1697 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1698 (1ULL << EF10_STAT_port_rx_packets) | \
1699 (1ULL << EF10_STAT_port_rx_good) | \
1700 (1ULL << EF10_STAT_port_rx_bad) | \
1701 (1ULL << EF10_STAT_port_rx_pause) | \
1702 (1ULL << EF10_STAT_port_rx_control) | \
1703 (1ULL << EF10_STAT_port_rx_unicast) | \
1704 (1ULL << EF10_STAT_port_rx_multicast) | \
1705 (1ULL << EF10_STAT_port_rx_broadcast) | \
1706 (1ULL << EF10_STAT_port_rx_lt64) | \
1707 (1ULL << EF10_STAT_port_rx_64) | \
1708 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1709 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1710 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1711 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1712 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1713 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1714 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1715 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1716 (1ULL << EF10_STAT_port_rx_overflow) | \
1717 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
1718 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1719 (1ULL << GENERIC_STAT_rx_noskb_drops))
1720
1721/* On 7000 series NICs, these statistics are only provided by the 10G MAC.
1722 * For a 10G/40G switchable port we do not expose these because they might
1723 * not include all the packets they should.
1724 * On 8000 series NICs these statistics are always provided.
1725 */
1726#define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1727 (1ULL << EF10_STAT_port_tx_lt64) | \
1728 (1ULL << EF10_STAT_port_tx_64) | \
1729 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1730 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1731 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1732 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1733 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1734 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
1735
1736/* These statistics are only provided by the 40G MAC. For a 10G/40G
1737 * switchable port we do expose these because the errors will otherwise
1738 * be silent.
1739 */
1740#define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1741 (1ULL << EF10_STAT_port_rx_length_error))
1742
1743/* These statistics are only provided if the firmware supports the
1744 * capability PM_AND_RXDP_COUNTERS.
1745 */
1746#define HUNT_PM_AND_RXDP_STAT_MASK ( \
1747 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1748 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1749 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1750 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1751 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1752 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1753 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1754 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1755 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1756 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1757 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1758 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
1759
1760/* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V2,
1761 * indicated by returning a value >= MC_CMD_MAC_NSTATS_V2 in
1762 * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS.
1763 * These bits are in the second u64 of the raw mask.
1764 */
1765#define EF10_FEC_STAT_MASK ( \
1766 (1ULL << (EF10_STAT_fec_uncorrected_errors - 64)) | \
1767 (1ULL << (EF10_STAT_fec_corrected_errors - 64)) | \
1768 (1ULL << (EF10_STAT_fec_corrected_symbols_lane0 - 64)) | \
1769 (1ULL << (EF10_STAT_fec_corrected_symbols_lane1 - 64)) | \
1770 (1ULL << (EF10_STAT_fec_corrected_symbols_lane2 - 64)) | \
1771 (1ULL << (EF10_STAT_fec_corrected_symbols_lane3 - 64)))
1772
1773/* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V3,
1774 * indicated by returning a value >= MC_CMD_MAC_NSTATS_V3 in
1775 * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS.
1776 * These bits are in the second u64 of the raw mask.
1777 */
1778#define EF10_CTPIO_STAT_MASK ( \
1779 (1ULL << (EF10_STAT_ctpio_vi_busy_fallback - 64)) | \
1780 (1ULL << (EF10_STAT_ctpio_long_write_success - 64)) | \
1781 (1ULL << (EF10_STAT_ctpio_missing_dbell_fail - 64)) | \
1782 (1ULL << (EF10_STAT_ctpio_overflow_fail - 64)) | \
1783 (1ULL << (EF10_STAT_ctpio_underflow_fail - 64)) | \
1784 (1ULL << (EF10_STAT_ctpio_timeout_fail - 64)) | \
1785 (1ULL << (EF10_STAT_ctpio_noncontig_wr_fail - 64)) | \
1786 (1ULL << (EF10_STAT_ctpio_frm_clobber_fail - 64)) | \
1787 (1ULL << (EF10_STAT_ctpio_invalid_wr_fail - 64)) | \
1788 (1ULL << (EF10_STAT_ctpio_vi_clobber_fallback - 64)) | \
1789 (1ULL << (EF10_STAT_ctpio_unqualified_fallback - 64)) | \
1790 (1ULL << (EF10_STAT_ctpio_runt_fallback - 64)) | \
1791 (1ULL << (EF10_STAT_ctpio_success - 64)) | \
1792 (1ULL << (EF10_STAT_ctpio_fallback - 64)) | \
1793 (1ULL << (EF10_STAT_ctpio_poison - 64)) | \
1794 (1ULL << (EF10_STAT_ctpio_erase - 64)))
1795
1796static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
1797{
1798 u64 raw_mask = HUNT_COMMON_STAT_MASK;
1799 u32 port_caps = efx_mcdi_phy_get_caps(efx);
1800 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1801
1802 if (!(efx->mcdi->fn_flags &
1803 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1804 return 0;
1805
1806 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) {
1807 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
1808 /* 8000 series have everything even at 40G */
1809 if (nic_data->datapath_caps2 &
1810 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN))
1811 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1812 } else {
1813 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1814 }
1815
1816 if (nic_data->datapath_caps &
1817 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1818 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1819
1820 return raw_mask;
1821}
1822
1823static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1824{
1825 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1826 u64 raw_mask[2];
1827
1828 raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1829
1830 /* Only show vadaptor stats when EVB capability is present */
1831 if (nic_data->datapath_caps &
1832 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1833 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1834 raw_mask[1] = (1ULL << (EF10_STAT_V1_COUNT - 64)) - 1;
1835 } else {
1836 raw_mask[1] = 0;
1837 }
1838 /* Only show FEC stats when NIC supports MC_CMD_MAC_STATS_V2 */
1839 if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V2)
1840 raw_mask[1] |= EF10_FEC_STAT_MASK;
1841
1842 /* CTPIO stats appear in V3. Only show them on devices that actually
1843 * support CTPIO. Although this driver doesn't use CTPIO others might,
1844 * and we may be reporting the stats for the underlying port.
1845 */
1846 if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V3 &&
1847 (nic_data->datapath_caps2 &
1848 (1 << MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_LBN)))
1849 raw_mask[1] |= EF10_CTPIO_STAT_MASK;
1850
1851#if BITS_PER_LONG == 64
1852 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2);
1853 mask[0] = raw_mask[0];
1854 mask[1] = raw_mask[1];
1855#else
1856 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3);
1857 mask[0] = raw_mask[0] & 0xffffffff;
1858 mask[1] = raw_mask[0] >> 32;
1859 mask[2] = raw_mask[1] & 0xffffffff;
1860#endif
1861}
1862
1863static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1864{
1865 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1866
1867 efx_ef10_get_stat_mask(efx, mask);
1868 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
1869 mask, names);
1870}
1871
1872static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1873 struct rtnl_link_stats64 *core_stats)
1874{
1875 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1876 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1877 u64 *stats = nic_data->stats;
1878 size_t stats_count = 0, index;
1879
1880 efx_ef10_get_stat_mask(efx, mask);
1881
1882 if (full_stats) {
1883 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1884 if (efx_ef10_stat_desc[index].name) {
1885 *full_stats++ = stats[index];
1886 ++stats_count;
1887 }
1888 }
1889 }
1890
1891 if (!core_stats)
1892 return stats_count;
1893
1894 if (nic_data->datapath_caps &
1895 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1896 /* Use vadaptor stats. */
1897 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1898 stats[EF10_STAT_rx_multicast] +
1899 stats[EF10_STAT_rx_broadcast];
1900 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1901 stats[EF10_STAT_tx_multicast] +
1902 stats[EF10_STAT_tx_broadcast];
1903 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1904 stats[EF10_STAT_rx_multicast_bytes] +
1905 stats[EF10_STAT_rx_broadcast_bytes];
1906 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1907 stats[EF10_STAT_tx_multicast_bytes] +
1908 stats[EF10_STAT_tx_broadcast_bytes];
1909 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
1910 stats[GENERIC_STAT_rx_noskb_drops];
1911 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1912 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1913 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1914 core_stats->rx_errors = core_stats->rx_crc_errors;
1915 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
1916 } else {
1917 /* Use port stats. */
1918 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1919 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1920 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1921 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1922 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1923 stats[GENERIC_STAT_rx_nodesc_trunc] +
1924 stats[GENERIC_STAT_rx_noskb_drops];
1925 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1926 core_stats->rx_length_errors =
1927 stats[EF10_STAT_port_rx_gtjumbo] +
1928 stats[EF10_STAT_port_rx_length_error];
1929 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1930 core_stats->rx_frame_errors =
1931 stats[EF10_STAT_port_rx_align_error];
1932 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1933 core_stats->rx_errors = (core_stats->rx_length_errors +
1934 core_stats->rx_crc_errors +
1935 core_stats->rx_frame_errors);
1936 }
1937
1938 return stats_count;
1939}
1940
1941static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
1942{
1943 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1944 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1945 __le64 generation_start, generation_end;
1946 u64 *stats = nic_data->stats;
1947 __le64 *dma_stats;
1948
1949 efx_ef10_get_stat_mask(efx, mask);
1950
1951 dma_stats = efx->stats_buffer.addr;
1952
1953 generation_end = dma_stats[efx->num_mac_stats - 1];
1954 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1955 return 0;
1956 rmb();
1957 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1958 stats, efx->stats_buffer.addr, false);
1959 rmb();
1960 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1961 if (generation_end != generation_start)
1962 return -EAGAIN;
1963
1964 /* Update derived statistics */
1965 efx_nic_fix_nodesc_drop_stat(efx,
1966 &stats[EF10_STAT_port_rx_nodesc_drops]);
1967 stats[EF10_STAT_port_rx_good_bytes] =
1968 stats[EF10_STAT_port_rx_bytes] -
1969 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1970 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1971 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
1972 efx_update_sw_stats(efx, stats);
1973 return 0;
1974}
1975
1976
1977static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1978 struct rtnl_link_stats64 *core_stats)
1979{
1980 int retry;
1981
1982 /* If we're unlucky enough to read statistics during the DMA, wait
1983 * up to 10ms for it to finish (typically takes <500us)
1984 */
1985 for (retry = 0; retry < 100; ++retry) {
1986 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
1987 break;
1988 udelay(100);
1989 }
1990
1991 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1992}
1993
1994static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1995{
1996 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1997 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1998 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1999 __le64 generation_start, generation_end;
2000 u64 *stats = nic_data->stats;
2001 u32 dma_len = efx->num_mac_stats * sizeof(u64);
2002 struct efx_buffer stats_buf;
2003 __le64 *dma_stats;
2004 int rc;
2005
2006 spin_unlock_bh(&efx->stats_lock);
2007
2008 if (in_interrupt()) {
2009 /* If in atomic context, cannot update stats. Just update the
2010 * software stats and return so the caller can continue.
2011 */
2012 spin_lock_bh(&efx->stats_lock);
2013 efx_update_sw_stats(efx, stats);
2014 return 0;
2015 }
2016
2017 efx_ef10_get_stat_mask(efx, mask);
2018
2019 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
2020 if (rc) {
2021 spin_lock_bh(&efx->stats_lock);
2022 return rc;
2023 }
2024
2025 dma_stats = stats_buf.addr;
2026 dma_stats[efx->num_mac_stats - 1] = EFX_MC_STATS_GENERATION_INVALID;
2027
2028 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
2029 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
2030 MAC_STATS_IN_DMA, 1);
2031 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
2032 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
2033
2034 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
2035 NULL, 0, NULL);
2036 spin_lock_bh(&efx->stats_lock);
2037 if (rc) {
2038 /* Expect ENOENT if DMA queues have not been set up */
2039 if (rc != -ENOENT || atomic_read(&efx->active_queues))
2040 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
2041 sizeof(inbuf), NULL, 0, rc);
2042 goto out;
2043 }
2044
2045 generation_end = dma_stats[efx->num_mac_stats - 1];
2046 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
2047 WARN_ON_ONCE(1);
2048 goto out;
2049 }
2050 rmb();
2051 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
2052 stats, stats_buf.addr, false);
2053 rmb();
2054 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
2055 if (generation_end != generation_start) {
2056 rc = -EAGAIN;
2057 goto out;
2058 }
2059
2060 efx_update_sw_stats(efx, stats);
2061out:
2062 efx_nic_free_buffer(efx, &stats_buf);
2063 return rc;
2064}
2065
2066static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
2067 struct rtnl_link_stats64 *core_stats)
2068{
2069 if (efx_ef10_try_update_nic_stats_vf(efx))
2070 return 0;
2071
2072 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
2073}
2074
2075static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
2076{
2077 struct efx_nic *efx = channel->efx;
2078 unsigned int mode, usecs;
2079 efx_dword_t timer_cmd;
2080
2081 if (channel->irq_moderation_us) {
2082 mode = 3;
2083 usecs = channel->irq_moderation_us;
2084 } else {
2085 mode = 0;
2086 usecs = 0;
2087 }
2088
2089 if (EFX_EF10_WORKAROUND_61265(efx)) {
2090 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN);
2091 unsigned int ns = usecs * 1000;
2092
2093 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE,
2094 channel->channel);
2095 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns);
2096 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns);
2097 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode);
2098
2099 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR,
2100 inbuf, sizeof(inbuf), 0, NULL, 0);
2101 } else if (EFX_EF10_WORKAROUND_35388(efx)) {
2102 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
2103
2104 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
2105 EFE_DD_EVQ_IND_TIMER_FLAGS,
2106 ERF_DD_EVQ_IND_TIMER_MODE, mode,
2107 ERF_DD_EVQ_IND_TIMER_VAL, ticks);
2108 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
2109 channel->channel);
2110 } else {
2111 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
2112
2113 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
2114 ERF_DZ_TC_TIMER_VAL, ticks,
2115 ERF_FZ_TC_TMR_REL_VAL, ticks);
2116 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
2117 channel->channel);
2118 }
2119}
2120
2121static void efx_ef10_get_wol_vf(struct efx_nic *efx,
2122 struct ethtool_wolinfo *wol) {}
2123
2124static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
2125{
2126 return -EOPNOTSUPP;
2127}
2128
2129static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
2130{
2131 wol->supported = 0;
2132 wol->wolopts = 0;
2133 memset(&wol->sopass, 0, sizeof(wol->sopass));
2134}
2135
2136static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
2137{
2138 if (type != 0)
2139 return -EINVAL;
2140 return 0;
2141}
2142
2143static void efx_ef10_mcdi_request(struct efx_nic *efx,
2144 const efx_dword_t *hdr, size_t hdr_len,
2145 const efx_dword_t *sdu, size_t sdu_len)
2146{
2147 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2148 u8 *pdu = nic_data->mcdi_buf.addr;
2149
2150 memcpy(pdu, hdr, hdr_len);
2151 memcpy(pdu + hdr_len, sdu, sdu_len);
2152 wmb();
2153
2154 /* The hardware provides 'low' and 'high' (doorbell) registers
2155 * for passing the 64-bit address of an MCDI request to
2156 * firmware. However the dwords are swapped by firmware. The
2157 * least significant bits of the doorbell are then 0 for all
2158 * MCDI requests due to alignment.
2159 */
2160 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
2161 ER_DZ_MC_DB_LWRD);
2162 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
2163 ER_DZ_MC_DB_HWRD);
2164}
2165
2166static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
2167{
2168 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2169 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
2170
2171 rmb();
2172 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
2173}
2174
2175static void
2176efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
2177 size_t offset, size_t outlen)
2178{
2179 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2180 const u8 *pdu = nic_data->mcdi_buf.addr;
2181
2182 memcpy(outbuf, pdu + offset, outlen);
2183}
2184
2185static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
2186{
2187 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2188
2189 /* All our allocations have been reset */
2190 efx_ef10_reset_mc_allocations(efx);
2191
2192 /* The datapath firmware might have been changed */
2193 nic_data->must_check_datapath_caps = true;
2194
2195 /* MAC statistics have been cleared on the NIC; clear the local
2196 * statistic that we update with efx_update_diff_stat().
2197 */
2198 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
2199}
2200
2201static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
2202{
2203 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2204 int rc;
2205
2206 rc = efx_ef10_get_warm_boot_count(efx);
2207 if (rc < 0) {
2208 /* The firmware is presumably in the process of
2209 * rebooting. However, we are supposed to report each
2210 * reboot just once, so we must only do that once we
2211 * can read and store the updated warm boot count.
2212 */
2213 return 0;
2214 }
2215
2216 if (rc == nic_data->warm_boot_count)
2217 return 0;
2218
2219 nic_data->warm_boot_count = rc;
2220 efx_ef10_mcdi_reboot_detected(efx);
2221
2222 return -EIO;
2223}
2224
2225/* Handle an MSI interrupt
2226 *
2227 * Handle an MSI hardware interrupt. This routine schedules event
2228 * queue processing. No interrupt acknowledgement cycle is necessary.
2229 * Also, we never need to check that the interrupt is for us, since
2230 * MSI interrupts cannot be shared.
2231 */
2232static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
2233{
2234 struct efx_msi_context *context = dev_id;
2235 struct efx_nic *efx = context->efx;
2236
2237 netif_vdbg(efx, intr, efx->net_dev,
2238 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
2239
2240 if (likely(READ_ONCE(efx->irq_soft_enabled))) {
2241 /* Note test interrupts */
2242 if (context->index == efx->irq_level)
2243 efx->last_irq_cpu = raw_smp_processor_id();
2244
2245 /* Schedule processing of the channel */
2246 efx_schedule_channel_irq(efx->channel[context->index]);
2247 }
2248
2249 return IRQ_HANDLED;
2250}
2251
2252static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
2253{
2254 struct efx_nic *efx = dev_id;
2255 bool soft_enabled = READ_ONCE(efx->irq_soft_enabled);
2256 struct efx_channel *channel;
2257 efx_dword_t reg;
2258 u32 queues;
2259
2260 /* Read the ISR which also ACKs the interrupts */
2261 efx_readd(efx, ®, ER_DZ_BIU_INT_ISR);
2262 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
2263
2264 if (queues == 0)
2265 return IRQ_NONE;
2266
2267 if (likely(soft_enabled)) {
2268 /* Note test interrupts */
2269 if (queues & (1U << efx->irq_level))
2270 efx->last_irq_cpu = raw_smp_processor_id();
2271
2272 efx_for_each_channel(channel, efx) {
2273 if (queues & 1)
2274 efx_schedule_channel_irq(channel);
2275 queues >>= 1;
2276 }
2277 }
2278
2279 netif_vdbg(efx, intr, efx->net_dev,
2280 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
2281 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
2282
2283 return IRQ_HANDLED;
2284}
2285
2286static int efx_ef10_irq_test_generate(struct efx_nic *efx)
2287{
2288 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
2289
2290 if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true,
2291 NULL) == 0)
2292 return -ENOTSUPP;
2293
2294 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
2295
2296 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
2297 return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
2298 inbuf, sizeof(inbuf), NULL, 0, NULL);
2299}
2300
2301static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
2302{
2303 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
2304 (tx_queue->ptr_mask + 1) *
2305 sizeof(efx_qword_t),
2306 GFP_KERNEL);
2307}
2308
2309/* This writes to the TX_DESC_WPTR and also pushes data */
2310static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
2311 const efx_qword_t *txd)
2312{
2313 unsigned int write_ptr;
2314 efx_oword_t reg;
2315
2316 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2317 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
2318 reg.qword[0] = *txd;
2319 efx_writeo_page(tx_queue->efx, ®,
2320 ER_DZ_TX_DESC_UPD, tx_queue->queue);
2321}
2322
2323/* Add Firmware-Assisted TSO v2 option descriptors to a queue.
2324 */
2325static int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue,
2326 struct sk_buff *skb,
2327 bool *data_mapped)
2328{
2329 struct efx_tx_buffer *buffer;
2330 struct tcphdr *tcp;
2331 struct iphdr *ip;
2332
2333 u16 ipv4_id;
2334 u32 seqnum;
2335 u32 mss;
2336
2337 EFX_WARN_ON_ONCE_PARANOID(tx_queue->tso_version != 2);
2338
2339 mss = skb_shinfo(skb)->gso_size;
2340
2341 if (unlikely(mss < 4)) {
2342 WARN_ONCE(1, "MSS of %u is too small for TSO v2\n", mss);
2343 return -EINVAL;
2344 }
2345
2346 ip = ip_hdr(skb);
2347 if (ip->version == 4) {
2348 /* Modify IPv4 header if needed. */
2349 ip->tot_len = 0;
2350 ip->check = 0;
2351 ipv4_id = ntohs(ip->id);
2352 } else {
2353 /* Modify IPv6 header if needed. */
2354 struct ipv6hdr *ipv6 = ipv6_hdr(skb);
2355
2356 ipv6->payload_len = 0;
2357 ipv4_id = 0;
2358 }
2359
2360 tcp = tcp_hdr(skb);
2361 seqnum = ntohl(tcp->seq);
2362
2363 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2364
2365 buffer->flags = EFX_TX_BUF_OPTION;
2366 buffer->len = 0;
2367 buffer->unmap_len = 0;
2368 EFX_POPULATE_QWORD_5(buffer->option,
2369 ESF_DZ_TX_DESC_IS_OPT, 1,
2370 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2371 ESF_DZ_TX_TSO_OPTION_TYPE,
2372 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A,
2373 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
2374 ESF_DZ_TX_TSO_TCP_SEQNO, seqnum
2375 );
2376 ++tx_queue->insert_count;
2377
2378 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
2379
2380 buffer->flags = EFX_TX_BUF_OPTION;
2381 buffer->len = 0;
2382 buffer->unmap_len = 0;
2383 EFX_POPULATE_QWORD_4(buffer->option,
2384 ESF_DZ_TX_DESC_IS_OPT, 1,
2385 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO,
2386 ESF_DZ_TX_TSO_OPTION_TYPE,
2387 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B,
2388 ESF_DZ_TX_TSO_TCP_MSS, mss
2389 );
2390 ++tx_queue->insert_count;
2391
2392 return 0;
2393}
2394
2395static u32 efx_ef10_tso_versions(struct efx_nic *efx)
2396{
2397 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2398 u32 tso_versions = 0;
2399
2400 if (nic_data->datapath_caps &
2401 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))
2402 tso_versions |= BIT(1);
2403 if (nic_data->datapath_caps2 &
2404 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN))
2405 tso_versions |= BIT(2);
2406 return tso_versions;
2407}
2408
2409static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
2410{
2411 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2412 EFX_BUF_SIZE));
2413 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
2414 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
2415 struct efx_channel *channel = tx_queue->channel;
2416 struct efx_nic *efx = tx_queue->efx;
2417 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2418 bool tso_v2 = false;
2419 size_t inlen;
2420 dma_addr_t dma_addr;
2421 efx_qword_t *txd;
2422 int rc;
2423 int i;
2424 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
2425
2426 /* Only attempt to enable TX timestamping if we have the license for it,
2427 * otherwise TXQ init will fail
2428 */
2429 if (!(nic_data->licensed_features &
2430 (1 << LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN))) {
2431 tx_queue->timestamping = false;
2432 /* Disable sync events on this channel. */
2433 if (efx->type->ptp_set_ts_sync_events)
2434 efx->type->ptp_set_ts_sync_events(efx, false, false);
2435 }
2436
2437 /* TSOv2 is a limited resource that can only be configured on a limited
2438 * number of queues. TSO without checksum offload is not really a thing,
2439 * so we only enable it for those queues.
2440 * TSOv2 cannot be used with Hardware timestamping.
2441 */
2442 if (csum_offload && (nic_data->datapath_caps2 &
2443 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN)) &&
2444 !tx_queue->timestamping) {
2445 tso_v2 = true;
2446 netif_dbg(efx, hw, efx->net_dev, "Using TSOv2 for channel %u\n",
2447 channel->channel);
2448 }
2449
2450 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
2451 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
2452 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
2453 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
2454 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
2455 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
2456
2457 dma_addr = tx_queue->txd.buf.dma_addr;
2458
2459 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
2460 tx_queue->queue, entries, (u64)dma_addr);
2461
2462 for (i = 0; i < entries; ++i) {
2463 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
2464 dma_addr += EFX_BUF_SIZE;
2465 }
2466
2467 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
2468
2469 do {
2470 MCDI_POPULATE_DWORD_4(inbuf, INIT_TXQ_IN_FLAGS,
2471 /* This flag was removed from mcdi_pcol.h for
2472 * the non-_EXT version of INIT_TXQ. However,
2473 * firmware still honours it.
2474 */
2475 INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, tso_v2,
2476 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
2477 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload,
2478 INIT_TXQ_EXT_IN_FLAG_TIMESTAMP,
2479 tx_queue->timestamping);
2480
2481 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
2482 NULL, 0, NULL);
2483 if (rc == -ENOSPC && tso_v2) {
2484 /* Retry without TSOv2 if we're short on contexts. */
2485 tso_v2 = false;
2486 netif_warn(efx, probe, efx->net_dev,
2487 "TSOv2 context not available to segment in hardware. TCP performance may be reduced.\n");
2488 } else if (rc) {
2489 efx_mcdi_display_error(efx, MC_CMD_INIT_TXQ,
2490 MC_CMD_INIT_TXQ_EXT_IN_LEN,
2491 NULL, 0, rc);
2492 goto fail;
2493 }
2494 } while (rc);
2495
2496 /* A previous user of this TX queue might have set us up the
2497 * bomb by writing a descriptor to the TX push collector but
2498 * not the doorbell. (Each collector belongs to a port, not a
2499 * queue or function, so cannot easily be reset.) We must
2500 * attempt to push a no-op descriptor in its place.
2501 */
2502 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
2503 tx_queue->insert_count = 1;
2504 txd = efx_tx_desc(tx_queue, 0);
2505 EFX_POPULATE_QWORD_5(*txd,
2506 ESF_DZ_TX_DESC_IS_OPT, true,
2507 ESF_DZ_TX_OPTION_TYPE,
2508 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
2509 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
2510 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload,
2511 ESF_DZ_TX_TIMESTAMP, tx_queue->timestamping);
2512 tx_queue->write_count = 1;
2513
2514 if (tso_v2) {
2515 tx_queue->handle_tso = efx_ef10_tx_tso_desc;
2516 tx_queue->tso_version = 2;
2517 } else if (nic_data->datapath_caps &
2518 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) {
2519 tx_queue->tso_version = 1;
2520 }
2521
2522 wmb();
2523 efx_ef10_push_tx_desc(tx_queue, txd);
2524
2525 return;
2526
2527fail:
2528 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
2529 tx_queue->queue);
2530}
2531
2532static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
2533{
2534 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
2535 MCDI_DECLARE_BUF_ERR(outbuf);
2536 struct efx_nic *efx = tx_queue->efx;
2537 size_t outlen;
2538 int rc;
2539
2540 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
2541 tx_queue->queue);
2542
2543 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
2544 outbuf, sizeof(outbuf), &outlen);
2545
2546 if (rc && rc != -EALREADY)
2547 goto fail;
2548
2549 return;
2550
2551fail:
2552 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
2553 outbuf, outlen, rc);
2554}
2555
2556static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
2557{
2558 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
2559}
2560
2561/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
2562static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
2563{
2564 unsigned int write_ptr;
2565 efx_dword_t reg;
2566
2567 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2568 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
2569 efx_writed_page(tx_queue->efx, ®,
2570 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
2571}
2572
2573#define EFX_EF10_MAX_TX_DESCRIPTOR_LEN 0x3fff
2574
2575static unsigned int efx_ef10_tx_limit_len(struct efx_tx_queue *tx_queue,
2576 dma_addr_t dma_addr, unsigned int len)
2577{
2578 if (len > EFX_EF10_MAX_TX_DESCRIPTOR_LEN) {
2579 /* If we need to break across multiple descriptors we should
2580 * stop at a page boundary. This assumes the length limit is
2581 * greater than the page size.
2582 */
2583 dma_addr_t end = dma_addr + EFX_EF10_MAX_TX_DESCRIPTOR_LEN;
2584
2585 BUILD_BUG_ON(EFX_EF10_MAX_TX_DESCRIPTOR_LEN < EFX_PAGE_SIZE);
2586 len = (end & (~(EFX_PAGE_SIZE - 1))) - dma_addr;
2587 }
2588
2589 return len;
2590}
2591
2592static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
2593{
2594 unsigned int old_write_count = tx_queue->write_count;
2595 struct efx_tx_buffer *buffer;
2596 unsigned int write_ptr;
2597 efx_qword_t *txd;
2598
2599 tx_queue->xmit_more_available = false;
2600 if (unlikely(tx_queue->write_count == tx_queue->insert_count))
2601 return;
2602
2603 do {
2604 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2605 buffer = &tx_queue->buffer[write_ptr];
2606 txd = efx_tx_desc(tx_queue, write_ptr);
2607 ++tx_queue->write_count;
2608
2609 /* Create TX descriptor ring entry */
2610 if (buffer->flags & EFX_TX_BUF_OPTION) {
2611 *txd = buffer->option;
2612 if (EFX_QWORD_FIELD(*txd, ESF_DZ_TX_OPTION_TYPE) == 1)
2613 /* PIO descriptor */
2614 tx_queue->packet_write_count = tx_queue->write_count;
2615 } else {
2616 tx_queue->packet_write_count = tx_queue->write_count;
2617 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
2618 EFX_POPULATE_QWORD_3(
2619 *txd,
2620 ESF_DZ_TX_KER_CONT,
2621 buffer->flags & EFX_TX_BUF_CONT,
2622 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
2623 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
2624 }
2625 } while (tx_queue->write_count != tx_queue->insert_count);
2626
2627 wmb(); /* Ensure descriptors are written before they are fetched */
2628
2629 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
2630 txd = efx_tx_desc(tx_queue,
2631 old_write_count & tx_queue->ptr_mask);
2632 efx_ef10_push_tx_desc(tx_queue, txd);
2633 ++tx_queue->pushes;
2634 } else {
2635 efx_ef10_notify_tx_desc(tx_queue);
2636 }
2637}
2638
2639#define RSS_MODE_HASH_ADDRS (1 << RSS_MODE_HASH_SRC_ADDR_LBN |\
2640 1 << RSS_MODE_HASH_DST_ADDR_LBN)
2641#define RSS_MODE_HASH_PORTS (1 << RSS_MODE_HASH_SRC_PORT_LBN |\
2642 1 << RSS_MODE_HASH_DST_PORT_LBN)
2643#define RSS_CONTEXT_FLAGS_DEFAULT (1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN |\
2644 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN |\
2645 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN |\
2646 1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN |\
2647 (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN |\
2648 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN |\
2649 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN |\
2650 (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN |\
2651 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN |\
2652 RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN)
2653
2654static int efx_ef10_get_rss_flags(struct efx_nic *efx, u32 context, u32 *flags)
2655{
2656 /* Firmware had a bug (sfc bug 61952) where it would not actually
2657 * fill in the flags field in the response to MC_CMD_RSS_CONTEXT_GET_FLAGS.
2658 * This meant that it would always contain whatever was previously
2659 * in the MCDI buffer. Fortunately, all firmware versions with
2660 * this bug have the same default flags value for a newly-allocated
2661 * RSS context, and the only time we want to get the flags is just
2662 * after allocating. Moreover, the response has a 32-bit hole
2663 * where the context ID would be in the request, so we can use an
2664 * overlength buffer in the request and pre-fill the flags field
2665 * with what we believe the default to be. Thus if the firmware
2666 * has the bug, it will leave our pre-filled value in the flags
2667 * field of the response, and we will get the right answer.
2668 *
2669 * However, this does mean that this function should NOT be used if
2670 * the RSS context flags might not be their defaults - it is ONLY
2671 * reliably correct for a newly-allocated RSS context.
2672 */
2673 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2674 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2675 size_t outlen;
2676 int rc;
2677
2678 /* Check we have a hole for the context ID */
2679 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN != MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST);
2680 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID, context);
2681 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS,
2682 RSS_CONTEXT_FLAGS_DEFAULT);
2683 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_FLAGS, inbuf,
2684 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
2685 if (rc == 0) {
2686 if (outlen < MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN)
2687 rc = -EIO;
2688 else
2689 *flags = MCDI_DWORD(outbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS);
2690 }
2691 return rc;
2692}
2693
2694/* Attempt to enable 4-tuple UDP hashing on the specified RSS context.
2695 * If we fail, we just leave the RSS context at its default hash settings,
2696 * which is safe but may slightly reduce performance.
2697 * Defaults are 4-tuple for TCP and 2-tuple for UDP and other-IP, so we
2698 * just need to set the UDP ports flags (for both IP versions).
2699 */
2700static void efx_ef10_set_rss_flags(struct efx_nic *efx,
2701 struct efx_rss_context *ctx)
2702{
2703 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN);
2704 u32 flags;
2705
2706 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN != 0);
2707
2708 if (efx_ef10_get_rss_flags(efx, ctx->context_id, &flags) != 0)
2709 return;
2710 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID,
2711 ctx->context_id);
2712 flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN;
2713 flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN;
2714 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_FLAGS, flags);
2715 if (!efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_FLAGS, inbuf, sizeof(inbuf),
2716 NULL, 0, NULL))
2717 /* Succeeded, so UDP 4-tuple is now enabled */
2718 ctx->rx_hash_udp_4tuple = true;
2719}
2720
2721static int efx_ef10_alloc_rss_context(struct efx_nic *efx, bool exclusive,
2722 struct efx_rss_context *ctx,
2723 unsigned *context_size)
2724{
2725 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
2726 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
2727 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2728 size_t outlen;
2729 int rc;
2730 u32 alloc_type = exclusive ?
2731 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
2732 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
2733 unsigned rss_spread = exclusive ?
2734 efx->rss_spread :
2735 min(rounddown_pow_of_two(efx->rss_spread),
2736 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
2737
2738 if (!exclusive && rss_spread == 1) {
2739 ctx->context_id = EFX_EF10_RSS_CONTEXT_INVALID;
2740 if (context_size)
2741 *context_size = 1;
2742 return 0;
2743 }
2744
2745 if (nic_data->datapath_caps &
2746 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN)
2747 return -EOPNOTSUPP;
2748
2749 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
2750 nic_data->vport_id);
2751 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
2752 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
2753
2754 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
2755 outbuf, sizeof(outbuf), &outlen);
2756 if (rc != 0)
2757 return rc;
2758
2759 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
2760 return -EIO;
2761
2762 ctx->context_id = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
2763
2764 if (context_size)
2765 *context_size = rss_spread;
2766
2767 if (nic_data->datapath_caps &
2768 1 << MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN)
2769 efx_ef10_set_rss_flags(efx, ctx);
2770
2771 return 0;
2772}
2773
2774static int efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
2775{
2776 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
2777
2778 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
2779 context);
2780 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
2781 NULL, 0, NULL);
2782}
2783
2784static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
2785 const u32 *rx_indir_table, const u8 *key)
2786{
2787 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
2788 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
2789 int i, rc;
2790
2791 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
2792 context);
2793 BUILD_BUG_ON(ARRAY_SIZE(efx->rss_context.rx_indir_table) !=
2794 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
2795
2796 /* This iterates over the length of efx->rss_context.rx_indir_table, but
2797 * copies bytes from rx_indir_table. That's because the latter is a
2798 * pointer rather than an array, but should have the same length.
2799 * The efx->rss_context.rx_hash_key loop below is similar.
2800 */
2801 for (i = 0; i < ARRAY_SIZE(efx->rss_context.rx_indir_table); ++i)
2802 MCDI_PTR(tablebuf,
2803 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
2804 (u8) rx_indir_table[i];
2805
2806 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
2807 sizeof(tablebuf), NULL, 0, NULL);
2808 if (rc != 0)
2809 return rc;
2810
2811 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
2812 context);
2813 BUILD_BUG_ON(ARRAY_SIZE(efx->rss_context.rx_hash_key) !=
2814 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2815 for (i = 0; i < ARRAY_SIZE(efx->rss_context.rx_hash_key); ++i)
2816 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] = key[i];
2817
2818 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
2819 sizeof(keybuf), NULL, 0, NULL);
2820}
2821
2822static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
2823{
2824 int rc;
2825
2826 if (efx->rss_context.context_id != EFX_EF10_RSS_CONTEXT_INVALID) {
2827 rc = efx_ef10_free_rss_context(efx, efx->rss_context.context_id);
2828 WARN_ON(rc != 0);
2829 }
2830 efx->rss_context.context_id = EFX_EF10_RSS_CONTEXT_INVALID;
2831}
2832
2833static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
2834 unsigned *context_size)
2835{
2836 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2837 int rc = efx_ef10_alloc_rss_context(efx, false, &efx->rss_context,
2838 context_size);
2839
2840 if (rc != 0)
2841 return rc;
2842
2843 nic_data->rx_rss_context_exclusive = false;
2844 efx_set_default_rx_indir_table(efx, &efx->rss_context);
2845 return 0;
2846}
2847
2848static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
2849 const u32 *rx_indir_table,
2850 const u8 *key)
2851{
2852 u32 old_rx_rss_context = efx->rss_context.context_id;
2853 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2854 int rc;
2855
2856 if (efx->rss_context.context_id == EFX_EF10_RSS_CONTEXT_INVALID ||
2857 !nic_data->rx_rss_context_exclusive) {
2858 rc = efx_ef10_alloc_rss_context(efx, true, &efx->rss_context,
2859 NULL);
2860 if (rc == -EOPNOTSUPP)
2861 return rc;
2862 else if (rc != 0)
2863 goto fail1;
2864 }
2865
2866 rc = efx_ef10_populate_rss_table(efx, efx->rss_context.context_id,
2867 rx_indir_table, key);
2868 if (rc != 0)
2869 goto fail2;
2870
2871 if (efx->rss_context.context_id != old_rx_rss_context &&
2872 old_rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2873 WARN_ON(efx_ef10_free_rss_context(efx, old_rx_rss_context) != 0);
2874 nic_data->rx_rss_context_exclusive = true;
2875 if (rx_indir_table != efx->rss_context.rx_indir_table)
2876 memcpy(efx->rss_context.rx_indir_table, rx_indir_table,
2877 sizeof(efx->rss_context.rx_indir_table));
2878 if (key != efx->rss_context.rx_hash_key)
2879 memcpy(efx->rss_context.rx_hash_key, key,
2880 efx->type->rx_hash_key_size);
2881
2882 return 0;
2883
2884fail2:
2885 if (old_rx_rss_context != efx->rss_context.context_id) {
2886 WARN_ON(efx_ef10_free_rss_context(efx, efx->rss_context.context_id) != 0);
2887 efx->rss_context.context_id = old_rx_rss_context;
2888 }
2889fail1:
2890 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2891 return rc;
2892}
2893
2894static int efx_ef10_rx_push_rss_context_config(struct efx_nic *efx,
2895 struct efx_rss_context *ctx,
2896 const u32 *rx_indir_table,
2897 const u8 *key)
2898{
2899 int rc;
2900
2901 WARN_ON(!mutex_is_locked(&efx->rss_lock));
2902
2903 if (ctx->context_id == EFX_EF10_RSS_CONTEXT_INVALID) {
2904 rc = efx_ef10_alloc_rss_context(efx, true, ctx, NULL);
2905 if (rc)
2906 return rc;
2907 }
2908
2909 if (!rx_indir_table) /* Delete this context */
2910 return efx_ef10_free_rss_context(efx, ctx->context_id);
2911
2912 rc = efx_ef10_populate_rss_table(efx, ctx->context_id,
2913 rx_indir_table, key);
2914 if (rc)
2915 return rc;
2916
2917 memcpy(ctx->rx_indir_table, rx_indir_table,
2918 sizeof(efx->rss_context.rx_indir_table));
2919 memcpy(ctx->rx_hash_key, key, efx->type->rx_hash_key_size);
2920
2921 return 0;
2922}
2923
2924static int efx_ef10_rx_pull_rss_context_config(struct efx_nic *efx,
2925 struct efx_rss_context *ctx)
2926{
2927 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN);
2928 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN);
2929 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN);
2930 size_t outlen;
2931 int rc, i;
2932
2933 WARN_ON(!mutex_is_locked(&efx->rss_lock));
2934
2935 BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN !=
2936 MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN);
2937
2938 if (ctx->context_id == EFX_EF10_RSS_CONTEXT_INVALID)
2939 return -ENOENT;
2940
2941 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID,
2942 ctx->context_id);
2943 BUILD_BUG_ON(ARRAY_SIZE(ctx->rx_indir_table) !=
2944 MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN);
2945 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_TABLE, inbuf, sizeof(inbuf),
2946 tablebuf, sizeof(tablebuf), &outlen);
2947 if (rc != 0)
2948 return rc;
2949
2950 if (WARN_ON(outlen != MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN))
2951 return -EIO;
2952
2953 for (i = 0; i < ARRAY_SIZE(ctx->rx_indir_table); i++)
2954 ctx->rx_indir_table[i] = MCDI_PTR(tablebuf,
2955 RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE)[i];
2956
2957 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID,
2958 ctx->context_id);
2959 BUILD_BUG_ON(ARRAY_SIZE(ctx->rx_hash_key) !=
2960 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2961 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_KEY, inbuf, sizeof(inbuf),
2962 keybuf, sizeof(keybuf), &outlen);
2963 if (rc != 0)
2964 return rc;
2965
2966 if (WARN_ON(outlen != MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN))
2967 return -EIO;
2968
2969 for (i = 0; i < ARRAY_SIZE(ctx->rx_hash_key); ++i)
2970 ctx->rx_hash_key[i] = MCDI_PTR(
2971 keybuf, RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY)[i];
2972
2973 return 0;
2974}
2975
2976static int efx_ef10_rx_pull_rss_config(struct efx_nic *efx)
2977{
2978 int rc;
2979
2980 mutex_lock(&efx->rss_lock);
2981 rc = efx_ef10_rx_pull_rss_context_config(efx, &efx->rss_context);
2982 mutex_unlock(&efx->rss_lock);
2983 return rc;
2984}
2985
2986static void efx_ef10_rx_restore_rss_contexts(struct efx_nic *efx)
2987{
2988 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2989 struct efx_rss_context *ctx;
2990 int rc;
2991
2992 WARN_ON(!mutex_is_locked(&efx->rss_lock));
2993
2994 if (!nic_data->must_restore_rss_contexts)
2995 return;
2996
2997 list_for_each_entry(ctx, &efx->rss_context.list, list) {
2998 /* previous NIC RSS context is gone */
2999 ctx->context_id = EFX_EF10_RSS_CONTEXT_INVALID;
3000 /* so try to allocate a new one */
3001 rc = efx_ef10_rx_push_rss_context_config(efx, ctx,
3002 ctx->rx_indir_table,
3003 ctx->rx_hash_key);
3004 if (rc)
3005 netif_warn(efx, probe, efx->net_dev,
3006 "failed to restore RSS context %u, rc=%d"
3007 "; RSS filters may fail to be applied\n",
3008 ctx->user_id, rc);
3009 }
3010 nic_data->must_restore_rss_contexts = false;
3011}
3012
3013static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
3014 const u32 *rx_indir_table,
3015 const u8 *key)
3016{
3017 int rc;
3018
3019 if (efx->rss_spread == 1)
3020 return 0;
3021
3022 if (!key)
3023 key = efx->rss_context.rx_hash_key;
3024
3025 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table, key);
3026
3027 if (rc == -ENOBUFS && !user) {
3028 unsigned context_size;
3029 bool mismatch = false;
3030 size_t i;
3031
3032 for (i = 0;
3033 i < ARRAY_SIZE(efx->rss_context.rx_indir_table) && !mismatch;
3034 i++)
3035 mismatch = rx_indir_table[i] !=
3036 ethtool_rxfh_indir_default(i, efx->rss_spread);
3037
3038 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
3039 if (rc == 0) {
3040 if (context_size != efx->rss_spread)
3041 netif_warn(efx, probe, efx->net_dev,
3042 "Could not allocate an exclusive RSS"
3043 " context; allocated a shared one of"
3044 " different size."
3045 " Wanted %u, got %u.\n",
3046 efx->rss_spread, context_size);
3047 else if (mismatch)
3048 netif_warn(efx, probe, efx->net_dev,
3049 "Could not allocate an exclusive RSS"
3050 " context; allocated a shared one but"
3051 " could not apply custom"
3052 " indirection.\n");
3053 else
3054 netif_info(efx, probe, efx->net_dev,
3055 "Could not allocate an exclusive RSS"
3056 " context; allocated a shared one.\n");
3057 }
3058 }
3059 return rc;
3060}
3061
3062static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
3063 const u32 *rx_indir_table
3064 __attribute__ ((unused)),
3065 const u8 *key
3066 __attribute__ ((unused)))
3067{
3068 if (user)
3069 return -EOPNOTSUPP;
3070 if (efx->rss_context.context_id != EFX_EF10_RSS_CONTEXT_INVALID)
3071 return 0;
3072 return efx_ef10_rx_push_shared_rss_config(efx, NULL);
3073}
3074
3075static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
3076{
3077 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
3078 (rx_queue->ptr_mask + 1) *
3079 sizeof(efx_qword_t),
3080 GFP_KERNEL);
3081}
3082
3083static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
3084{
3085 MCDI_DECLARE_BUF(inbuf,
3086 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
3087 EFX_BUF_SIZE));
3088 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
3089 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
3090 struct efx_nic *efx = rx_queue->efx;
3091 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3092 size_t inlen;
3093 dma_addr_t dma_addr;
3094 int rc;
3095 int i;
3096 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
3097
3098 rx_queue->scatter_n = 0;
3099 rx_queue->scatter_len = 0;
3100
3101 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
3102 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
3103 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
3104 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
3105 efx_rx_queue_index(rx_queue));
3106 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
3107 INIT_RXQ_IN_FLAG_PREFIX, 1,
3108 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
3109 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
3110 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
3111
3112 dma_addr = rx_queue->rxd.buf.dma_addr;
3113
3114 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
3115 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
3116
3117 for (i = 0; i < entries; ++i) {
3118 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
3119 dma_addr += EFX_BUF_SIZE;
3120 }
3121
3122 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
3123
3124 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
3125 NULL, 0, NULL);
3126 if (rc)
3127 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
3128 efx_rx_queue_index(rx_queue));
3129}
3130
3131static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
3132{
3133 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
3134 MCDI_DECLARE_BUF_ERR(outbuf);
3135 struct efx_nic *efx = rx_queue->efx;
3136 size_t outlen;
3137 int rc;
3138
3139 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
3140 efx_rx_queue_index(rx_queue));
3141
3142 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
3143 outbuf, sizeof(outbuf), &outlen);
3144
3145 if (rc && rc != -EALREADY)
3146 goto fail;
3147
3148 return;
3149
3150fail:
3151 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
3152 outbuf, outlen, rc);
3153}
3154
3155static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
3156{
3157 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
3158}
3159
3160/* This creates an entry in the RX descriptor queue */
3161static inline void
3162efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
3163{
3164 struct efx_rx_buffer *rx_buf;
3165 efx_qword_t *rxd;
3166
3167 rxd = efx_rx_desc(rx_queue, index);
3168 rx_buf = efx_rx_buffer(rx_queue, index);
3169 EFX_POPULATE_QWORD_2(*rxd,
3170 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
3171 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
3172}
3173
3174static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
3175{
3176 struct efx_nic *efx = rx_queue->efx;
3177 unsigned int write_count;
3178 efx_dword_t reg;
3179
3180 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
3181 write_count = rx_queue->added_count & ~7;
3182 if (rx_queue->notified_count == write_count)
3183 return;
3184
3185 do
3186 efx_ef10_build_rx_desc(
3187 rx_queue,
3188 rx_queue->notified_count & rx_queue->ptr_mask);
3189 while (++rx_queue->notified_count != write_count);
3190
3191 wmb();
3192 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
3193 write_count & rx_queue->ptr_mask);
3194 efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD,
3195 efx_rx_queue_index(rx_queue));
3196}
3197
3198static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
3199
3200static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
3201{
3202 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
3203 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3204 efx_qword_t event;
3205
3206 EFX_POPULATE_QWORD_2(event,
3207 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3208 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
3209
3210 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3211
3212 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3213 * already swapped the data to little-endian order.
3214 */
3215 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3216 sizeof(efx_qword_t));
3217
3218 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
3219 inbuf, sizeof(inbuf), 0,
3220 efx_ef10_rx_defer_refill_complete, 0);
3221}
3222
3223static void
3224efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
3225 int rc, efx_dword_t *outbuf,
3226 size_t outlen_actual)
3227{
3228 /* nothing to do */
3229}
3230
3231static int efx_ef10_ev_probe(struct efx_channel *channel)
3232{
3233 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
3234 (channel->eventq_mask + 1) *
3235 sizeof(efx_qword_t),
3236 GFP_KERNEL);
3237}
3238
3239static void efx_ef10_ev_fini(struct efx_channel *channel)
3240{
3241 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
3242 MCDI_DECLARE_BUF_ERR(outbuf);
3243 struct efx_nic *efx = channel->efx;
3244 size_t outlen;
3245 int rc;
3246
3247 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
3248
3249 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
3250 outbuf, sizeof(outbuf), &outlen);
3251
3252 if (rc && rc != -EALREADY)
3253 goto fail;
3254
3255 return;
3256
3257fail:
3258 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
3259 outbuf, outlen, rc);
3260}
3261
3262static int efx_ef10_ev_init(struct efx_channel *channel)
3263{
3264 MCDI_DECLARE_BUF(inbuf,
3265 MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
3266 EFX_BUF_SIZE));
3267 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_V2_OUT_LEN);
3268 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
3269 struct efx_nic *efx = channel->efx;
3270 struct efx_ef10_nic_data *nic_data;
3271 size_t inlen, outlen;
3272 unsigned int enabled, implemented;
3273 dma_addr_t dma_addr;
3274 int rc;
3275 int i;
3276
3277 nic_data = efx->nic_data;
3278
3279 /* Fill event queue with all ones (i.e. empty events) */
3280 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
3281
3282 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
3283 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
3284 /* INIT_EVQ expects index in vector table, not absolute */
3285 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
3286 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
3287 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
3288 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
3289 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
3290 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
3291 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
3292 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
3293
3294 if (nic_data->datapath_caps2 &
3295 1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN) {
3296 /* Use the new generic approach to specifying event queue
3297 * configuration, requesting lower latency or higher throughput.
3298 * The options that actually get used appear in the output.
3299 */
3300 MCDI_POPULATE_DWORD_2(inbuf, INIT_EVQ_V2_IN_FLAGS,
3301 INIT_EVQ_V2_IN_FLAG_INTERRUPTING, 1,
3302 INIT_EVQ_V2_IN_FLAG_TYPE,
3303 MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO);
3304 } else {
3305 bool cut_thru = !(nic_data->datapath_caps &
3306 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
3307
3308 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
3309 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
3310 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
3311 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
3312 INIT_EVQ_IN_FLAG_CUT_THRU, cut_thru);
3313 }
3314
3315 dma_addr = channel->eventq.buf.dma_addr;
3316 for (i = 0; i < entries; ++i) {
3317 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
3318 dma_addr += EFX_BUF_SIZE;
3319 }
3320
3321 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
3322
3323 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
3324 outbuf, sizeof(outbuf), &outlen);
3325
3326 if (outlen >= MC_CMD_INIT_EVQ_V2_OUT_LEN)
3327 netif_dbg(efx, drv, efx->net_dev,
3328 "Channel %d using event queue flags %08x\n",
3329 channel->channel,
3330 MCDI_DWORD(outbuf, INIT_EVQ_V2_OUT_FLAGS));
3331
3332 /* IRQ return is ignored */
3333 if (channel->channel || rc)
3334 return rc;
3335
3336 /* Successfully created event queue on channel 0 */
3337 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
3338 if (rc == -ENOSYS) {
3339 /* GET_WORKAROUNDS was implemented before this workaround,
3340 * thus it must be unavailable in this firmware.
3341 */
3342 nic_data->workaround_26807 = false;
3343 rc = 0;
3344 } else if (rc) {
3345 goto fail;
3346 } else {
3347 nic_data->workaround_26807 =
3348 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
3349
3350 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
3351 !nic_data->workaround_26807) {
3352 unsigned int flags;
3353
3354 rc = efx_mcdi_set_workaround(efx,
3355 MC_CMD_WORKAROUND_BUG26807,
3356 true, &flags);
3357
3358 if (!rc) {
3359 if (flags &
3360 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
3361 netif_info(efx, drv, efx->net_dev,
3362 "other functions on NIC have been reset\n");
3363
3364 /* With MCFW v4.6.x and earlier, the
3365 * boot count will have incremented,
3366 * so re-read the warm_boot_count
3367 * value now to ensure this function
3368 * doesn't think it has changed next
3369 * time it checks.
3370 */
3371 rc = efx_ef10_get_warm_boot_count(efx);
3372 if (rc >= 0) {
3373 nic_data->warm_boot_count = rc;
3374 rc = 0;
3375 }
3376 }
3377 nic_data->workaround_26807 = true;
3378 } else if (rc == -EPERM) {
3379 rc = 0;
3380 }
3381 }
3382 }
3383
3384 if (!rc)
3385 return 0;
3386
3387fail:
3388 efx_ef10_ev_fini(channel);
3389 return rc;
3390}
3391
3392static void efx_ef10_ev_remove(struct efx_channel *channel)
3393{
3394 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
3395}
3396
3397static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
3398 unsigned int rx_queue_label)
3399{
3400 struct efx_nic *efx = rx_queue->efx;
3401
3402 netif_info(efx, hw, efx->net_dev,
3403 "rx event arrived on queue %d labeled as queue %u\n",
3404 efx_rx_queue_index(rx_queue), rx_queue_label);
3405
3406 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3407}
3408
3409static void
3410efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
3411 unsigned int actual, unsigned int expected)
3412{
3413 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
3414 struct efx_nic *efx = rx_queue->efx;
3415
3416 netif_info(efx, hw, efx->net_dev,
3417 "dropped %d events (index=%d expected=%d)\n",
3418 dropped, actual, expected);
3419
3420 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
3421}
3422
3423/* partially received RX was aborted. clean up. */
3424static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
3425{
3426 unsigned int rx_desc_ptr;
3427
3428 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
3429 "scattered RX aborted (dropping %u buffers)\n",
3430 rx_queue->scatter_n);
3431
3432 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
3433
3434 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
3435 0, EFX_RX_PKT_DISCARD);
3436
3437 rx_queue->removed_count += rx_queue->scatter_n;
3438 rx_queue->scatter_n = 0;
3439 rx_queue->scatter_len = 0;
3440 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
3441}
3442
3443static u16 efx_ef10_handle_rx_event_errors(struct efx_channel *channel,
3444 unsigned int n_packets,
3445 unsigned int rx_encap_hdr,
3446 unsigned int rx_l3_class,
3447 unsigned int rx_l4_class,
3448 const efx_qword_t *event)
3449{
3450 struct efx_nic *efx = channel->efx;
3451 bool handled = false;
3452
3453 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)) {
3454 if (!(efx->net_dev->features & NETIF_F_RXALL)) {
3455 if (!efx->loopback_selftest)
3456 channel->n_rx_eth_crc_err += n_packets;
3457 return EFX_RX_PKT_DISCARD;
3458 }
3459 handled = true;
3460 }
3461 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR)) {
3462 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
3463 rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3464 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
3465 rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
3466 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
3467 netdev_WARN(efx->net_dev,
3468 "invalid class for RX_IPCKSUM_ERR: event="
3469 EFX_QWORD_FMT "\n",
3470 EFX_QWORD_VAL(*event));
3471 if (!efx->loopback_selftest)
3472 *(rx_encap_hdr ?
3473 &channel->n_rx_outer_ip_hdr_chksum_err :
3474 &channel->n_rx_ip_hdr_chksum_err) += n_packets;
3475 return 0;
3476 }
3477 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
3478 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN &&
3479 ((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3480 rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
3481 (rx_l4_class != ESE_FZ_L4_CLASS_TCP &&
3482 rx_l4_class != ESE_FZ_L4_CLASS_UDP))))
3483 netdev_WARN(efx->net_dev,
3484 "invalid class for RX_TCPUDP_CKSUM_ERR: event="
3485 EFX_QWORD_FMT "\n",
3486 EFX_QWORD_VAL(*event));
3487 if (!efx->loopback_selftest)
3488 *(rx_encap_hdr ?
3489 &channel->n_rx_outer_tcp_udp_chksum_err :
3490 &channel->n_rx_tcp_udp_chksum_err) += n_packets;
3491 return 0;
3492 }
3493 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_IP_INNER_CHKSUM_ERR)) {
3494 if (unlikely(!rx_encap_hdr))
3495 netdev_WARN(efx->net_dev,
3496 "invalid encapsulation type for RX_IP_INNER_CHKSUM_ERR: event="
3497 EFX_QWORD_FMT "\n",
3498 EFX_QWORD_VAL(*event));
3499 else if (unlikely(rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3500 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG &&
3501 rx_l3_class != ESE_DZ_L3_CLASS_IP6 &&
3502 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG))
3503 netdev_WARN(efx->net_dev,
3504 "invalid class for RX_IP_INNER_CHKSUM_ERR: event="
3505 EFX_QWORD_FMT "\n",
3506 EFX_QWORD_VAL(*event));
3507 if (!efx->loopback_selftest)
3508 channel->n_rx_inner_ip_hdr_chksum_err += n_packets;
3509 return 0;
3510 }
3511 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR)) {
3512 if (unlikely(!rx_encap_hdr))
3513 netdev_WARN(efx->net_dev,
3514 "invalid encapsulation type for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
3515 EFX_QWORD_FMT "\n",
3516 EFX_QWORD_VAL(*event));
3517 else if (unlikely((rx_l3_class != ESE_DZ_L3_CLASS_IP4 &&
3518 rx_l3_class != ESE_DZ_L3_CLASS_IP6) ||
3519 (rx_l4_class != ESE_FZ_L4_CLASS_TCP &&
3520 rx_l4_class != ESE_FZ_L4_CLASS_UDP)))
3521 netdev_WARN(efx->net_dev,
3522 "invalid class for RX_TCP_UDP_INNER_CHKSUM_ERR: event="
3523 EFX_QWORD_FMT "\n",
3524 EFX_QWORD_VAL(*event));
3525 if (!efx->loopback_selftest)
3526 channel->n_rx_inner_tcp_udp_chksum_err += n_packets;
3527 return 0;
3528 }
3529
3530 WARN_ON(!handled); /* No error bits were recognised */
3531 return 0;
3532}
3533
3534static int efx_ef10_handle_rx_event(struct efx_channel *channel,
3535 const efx_qword_t *event)
3536{
3537 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label;
3538 unsigned int rx_l3_class, rx_l4_class, rx_encap_hdr;
3539 unsigned int n_descs, n_packets, i;
3540 struct efx_nic *efx = channel->efx;
3541 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3542 struct efx_rx_queue *rx_queue;
3543 efx_qword_t errors;
3544 bool rx_cont;
3545 u16 flags = 0;
3546
3547 if (unlikely(READ_ONCE(efx->reset_pending)))
3548 return 0;
3549
3550 /* Basic packet information */
3551 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
3552 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
3553 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
3554 rx_l3_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L3_CLASS);
3555 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_FZ_RX_L4_CLASS);
3556 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
3557 rx_encap_hdr =
3558 nic_data->datapath_caps &
3559 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) ?
3560 EFX_QWORD_FIELD(*event, ESF_EZ_RX_ENCAP_HDR) :
3561 ESE_EZ_ENCAP_HDR_NONE;
3562
3563 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
3564 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
3565 EFX_QWORD_FMT "\n",
3566 EFX_QWORD_VAL(*event));
3567
3568 rx_queue = efx_channel_get_rx_queue(channel);
3569
3570 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
3571 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
3572
3573 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
3574 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3575
3576 if (n_descs != rx_queue->scatter_n + 1) {
3577 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3578
3579 /* detect rx abort */
3580 if (unlikely(n_descs == rx_queue->scatter_n)) {
3581 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
3582 netdev_WARN(efx->net_dev,
3583 "invalid RX abort: scatter_n=%u event="
3584 EFX_QWORD_FMT "\n",
3585 rx_queue->scatter_n,
3586 EFX_QWORD_VAL(*event));
3587 efx_ef10_handle_rx_abort(rx_queue);
3588 return 0;
3589 }
3590
3591 /* Check that RX completion merging is valid, i.e.
3592 * the current firmware supports it and this is a
3593 * non-scattered packet.
3594 */
3595 if (!(nic_data->datapath_caps &
3596 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
3597 rx_queue->scatter_n != 0 || rx_cont) {
3598 efx_ef10_handle_rx_bad_lbits(
3599 rx_queue, next_ptr_lbits,
3600 (rx_queue->removed_count +
3601 rx_queue->scatter_n + 1) &
3602 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
3603 return 0;
3604 }
3605
3606 /* Merged completion for multiple non-scattered packets */
3607 rx_queue->scatter_n = 1;
3608 rx_queue->scatter_len = 0;
3609 n_packets = n_descs;
3610 ++channel->n_rx_merge_events;
3611 channel->n_rx_merge_packets += n_packets;
3612 flags |= EFX_RX_PKT_PREFIX_LEN;
3613 } else {
3614 ++rx_queue->scatter_n;
3615 rx_queue->scatter_len += rx_bytes;
3616 if (rx_cont)
3617 return 0;
3618 n_packets = 1;
3619 }
3620
3621 EFX_POPULATE_QWORD_5(errors, ESF_DZ_RX_ECRC_ERR, 1,
3622 ESF_DZ_RX_IPCKSUM_ERR, 1,
3623 ESF_DZ_RX_TCPUDP_CKSUM_ERR, 1,
3624 ESF_EZ_RX_IP_INNER_CHKSUM_ERR, 1,
3625 ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR, 1);
3626 EFX_AND_QWORD(errors, *event, errors);
3627 if (unlikely(!EFX_QWORD_IS_ZERO(errors))) {
3628 flags |= efx_ef10_handle_rx_event_errors(channel, n_packets,
3629 rx_encap_hdr,
3630 rx_l3_class, rx_l4_class,
3631 event);
3632 } else {
3633 bool tcpudp = rx_l4_class == ESE_FZ_L4_CLASS_TCP ||
3634 rx_l4_class == ESE_FZ_L4_CLASS_UDP;
3635
3636 switch (rx_encap_hdr) {
3637 case ESE_EZ_ENCAP_HDR_VXLAN: /* VxLAN or GENEVE */
3638 flags |= EFX_RX_PKT_CSUMMED; /* outer UDP csum */
3639 if (tcpudp)
3640 flags |= EFX_RX_PKT_CSUM_LEVEL; /* inner L4 */
3641 break;
3642 case ESE_EZ_ENCAP_HDR_GRE:
3643 case ESE_EZ_ENCAP_HDR_NONE:
3644 if (tcpudp)
3645 flags |= EFX_RX_PKT_CSUMMED;
3646 break;
3647 default:
3648 netdev_WARN(efx->net_dev,
3649 "unknown encapsulation type: event="
3650 EFX_QWORD_FMT "\n",
3651 EFX_QWORD_VAL(*event));
3652 }
3653 }
3654
3655 if (rx_l4_class == ESE_FZ_L4_CLASS_TCP)
3656 flags |= EFX_RX_PKT_TCP;
3657
3658 channel->irq_mod_score += 2 * n_packets;
3659
3660 /* Handle received packet(s) */
3661 for (i = 0; i < n_packets; i++) {
3662 efx_rx_packet(rx_queue,
3663 rx_queue->removed_count & rx_queue->ptr_mask,
3664 rx_queue->scatter_n, rx_queue->scatter_len,
3665 flags);
3666 rx_queue->removed_count += rx_queue->scatter_n;
3667 }
3668
3669 rx_queue->scatter_n = 0;
3670 rx_queue->scatter_len = 0;
3671
3672 return n_packets;
3673}
3674
3675static u32 efx_ef10_extract_event_ts(efx_qword_t *event)
3676{
3677 u32 tstamp;
3678
3679 tstamp = EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI);
3680 tstamp <<= 16;
3681 tstamp |= EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO);
3682
3683 return tstamp;
3684}
3685
3686static void
3687efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
3688{
3689 struct efx_nic *efx = channel->efx;
3690 struct efx_tx_queue *tx_queue;
3691 unsigned int tx_ev_desc_ptr;
3692 unsigned int tx_ev_q_label;
3693 unsigned int tx_ev_type;
3694 u64 ts_part;
3695
3696 if (unlikely(READ_ONCE(efx->reset_pending)))
3697 return;
3698
3699 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
3700 return;
3701
3702 /* Get the transmit queue */
3703 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
3704 tx_queue = efx_channel_get_tx_queue(channel,
3705 tx_ev_q_label % EFX_TXQ_TYPES);
3706
3707 if (!tx_queue->timestamping) {
3708 /* Transmit completion */
3709 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
3710 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
3711 return;
3712 }
3713
3714 /* Transmit timestamps are only available for 8XXX series. They result
3715 * in three events per packet. These occur in order, and are:
3716 * - the normal completion event
3717 * - the low part of the timestamp
3718 * - the high part of the timestamp
3719 *
3720 * Each part of the timestamp is itself split across two 16 bit
3721 * fields in the event.
3722 */
3723 tx_ev_type = EFX_QWORD_FIELD(*event, ESF_EZ_TX_SOFT1);
3724
3725 switch (tx_ev_type) {
3726 case TX_TIMESTAMP_EVENT_TX_EV_COMPLETION:
3727 /* In case of Queue flush or FLR, we might have received
3728 * the previous TX completion event but not the Timestamp
3729 * events.
3730 */
3731 if (tx_queue->completed_desc_ptr != tx_queue->ptr_mask)
3732 efx_xmit_done(tx_queue, tx_queue->completed_desc_ptr);
3733
3734 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event,
3735 ESF_DZ_TX_DESCR_INDX);
3736 tx_queue->completed_desc_ptr =
3737 tx_ev_desc_ptr & tx_queue->ptr_mask;
3738 break;
3739
3740 case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO:
3741 ts_part = efx_ef10_extract_event_ts(event);
3742 tx_queue->completed_timestamp_minor = ts_part;
3743 break;
3744
3745 case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI:
3746 ts_part = efx_ef10_extract_event_ts(event);
3747 tx_queue->completed_timestamp_major = ts_part;
3748
3749 efx_xmit_done(tx_queue, tx_queue->completed_desc_ptr);
3750 tx_queue->completed_desc_ptr = tx_queue->ptr_mask;
3751 break;
3752
3753 default:
3754 netif_err(efx, hw, efx->net_dev,
3755 "channel %d unknown tx event type %d (data "
3756 EFX_QWORD_FMT ")\n",
3757 channel->channel, tx_ev_type,
3758 EFX_QWORD_VAL(*event));
3759 break;
3760 }
3761}
3762
3763static void
3764efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
3765{
3766 struct efx_nic *efx = channel->efx;
3767 int subcode;
3768
3769 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
3770
3771 switch (subcode) {
3772 case ESE_DZ_DRV_TIMER_EV:
3773 case ESE_DZ_DRV_WAKE_UP_EV:
3774 break;
3775 case ESE_DZ_DRV_START_UP_EV:
3776 /* event queue init complete. ok. */
3777 break;
3778 default:
3779 netif_err(efx, hw, efx->net_dev,
3780 "channel %d unknown driver event type %d"
3781 " (data " EFX_QWORD_FMT ")\n",
3782 channel->channel, subcode,
3783 EFX_QWORD_VAL(*event));
3784
3785 }
3786}
3787
3788static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
3789 efx_qword_t *event)
3790{
3791 struct efx_nic *efx = channel->efx;
3792 u32 subcode;
3793
3794 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
3795
3796 switch (subcode) {
3797 case EFX_EF10_TEST:
3798 channel->event_test_cpu = raw_smp_processor_id();
3799 break;
3800 case EFX_EF10_REFILL:
3801 /* The queue must be empty, so we won't receive any rx
3802 * events, so efx_process_channel() won't refill the
3803 * queue. Refill it here
3804 */
3805 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
3806 break;
3807 default:
3808 netif_err(efx, hw, efx->net_dev,
3809 "channel %d unknown driver event type %u"
3810 " (data " EFX_QWORD_FMT ")\n",
3811 channel->channel, (unsigned) subcode,
3812 EFX_QWORD_VAL(*event));
3813 }
3814}
3815
3816static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
3817{
3818 struct efx_nic *efx = channel->efx;
3819 efx_qword_t event, *p_event;
3820 unsigned int read_ptr;
3821 int ev_code;
3822 int spent = 0;
3823
3824 if (quota <= 0)
3825 return spent;
3826
3827 read_ptr = channel->eventq_read_ptr;
3828
3829 for (;;) {
3830 p_event = efx_event(channel, read_ptr);
3831 event = *p_event;
3832
3833 if (!efx_event_present(&event))
3834 break;
3835
3836 EFX_SET_QWORD(*p_event);
3837
3838 ++read_ptr;
3839
3840 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
3841
3842 netif_vdbg(efx, drv, efx->net_dev,
3843 "processing event on %d " EFX_QWORD_FMT "\n",
3844 channel->channel, EFX_QWORD_VAL(event));
3845
3846 switch (ev_code) {
3847 case ESE_DZ_EV_CODE_MCDI_EV:
3848 efx_mcdi_process_event(channel, &event);
3849 break;
3850 case ESE_DZ_EV_CODE_RX_EV:
3851 spent += efx_ef10_handle_rx_event(channel, &event);
3852 if (spent >= quota) {
3853 /* XXX can we split a merged event to
3854 * avoid going over-quota?
3855 */
3856 spent = quota;
3857 goto out;
3858 }
3859 break;
3860 case ESE_DZ_EV_CODE_TX_EV:
3861 efx_ef10_handle_tx_event(channel, &event);
3862 break;
3863 case ESE_DZ_EV_CODE_DRIVER_EV:
3864 efx_ef10_handle_driver_event(channel, &event);
3865 if (++spent == quota)
3866 goto out;
3867 break;
3868 case EFX_EF10_DRVGEN_EV:
3869 efx_ef10_handle_driver_generated_event(channel, &event);
3870 break;
3871 default:
3872 netif_err(efx, hw, efx->net_dev,
3873 "channel %d unknown event type %d"
3874 " (data " EFX_QWORD_FMT ")\n",
3875 channel->channel, ev_code,
3876 EFX_QWORD_VAL(event));
3877 }
3878 }
3879
3880out:
3881 channel->eventq_read_ptr = read_ptr;
3882 return spent;
3883}
3884
3885static void efx_ef10_ev_read_ack(struct efx_channel *channel)
3886{
3887 struct efx_nic *efx = channel->efx;
3888 efx_dword_t rptr;
3889
3890 if (EFX_EF10_WORKAROUND_35388(efx)) {
3891 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
3892 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
3893 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
3894 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
3895
3896 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3897 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
3898 ERF_DD_EVQ_IND_RPTR,
3899 (channel->eventq_read_ptr &
3900 channel->eventq_mask) >>
3901 ERF_DD_EVQ_IND_RPTR_WIDTH);
3902 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3903 channel->channel);
3904 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3905 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
3906 ERF_DD_EVQ_IND_RPTR,
3907 channel->eventq_read_ptr &
3908 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
3909 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3910 channel->channel);
3911 } else {
3912 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
3913 channel->eventq_read_ptr &
3914 channel->eventq_mask);
3915 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
3916 }
3917}
3918
3919static void efx_ef10_ev_test_generate(struct efx_channel *channel)
3920{
3921 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3922 struct efx_nic *efx = channel->efx;
3923 efx_qword_t event;
3924 int rc;
3925
3926 EFX_POPULATE_QWORD_2(event,
3927 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3928 ESF_DZ_EV_DATA, EFX_EF10_TEST);
3929
3930 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3931
3932 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3933 * already swapped the data to little-endian order.
3934 */
3935 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3936 sizeof(efx_qword_t));
3937
3938 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
3939 NULL, 0, NULL);
3940 if (rc != 0)
3941 goto fail;
3942
3943 return;
3944
3945fail:
3946 WARN_ON(true);
3947 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
3948}
3949
3950void efx_ef10_handle_drain_event(struct efx_nic *efx)
3951{
3952 if (atomic_dec_and_test(&efx->active_queues))
3953 wake_up(&efx->flush_wq);
3954
3955 WARN_ON(atomic_read(&efx->active_queues) < 0);
3956}
3957
3958static int efx_ef10_fini_dmaq(struct efx_nic *efx)
3959{
3960 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3961 struct efx_channel *channel;
3962 struct efx_tx_queue *tx_queue;
3963 struct efx_rx_queue *rx_queue;
3964 int pending;
3965
3966 /* If the MC has just rebooted, the TX/RX queues will have already been
3967 * torn down, but efx->active_queues needs to be set to zero.
3968 */
3969 if (nic_data->must_realloc_vis) {
3970 atomic_set(&efx->active_queues, 0);
3971 return 0;
3972 }
3973
3974 /* Do not attempt to write to the NIC during EEH recovery */
3975 if (efx->state != STATE_RECOVERY) {
3976 efx_for_each_channel(channel, efx) {
3977 efx_for_each_channel_rx_queue(rx_queue, channel)
3978 efx_ef10_rx_fini(rx_queue);
3979 efx_for_each_channel_tx_queue(tx_queue, channel)
3980 efx_ef10_tx_fini(tx_queue);
3981 }
3982
3983 wait_event_timeout(efx->flush_wq,
3984 atomic_read(&efx->active_queues) == 0,
3985 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
3986 pending = atomic_read(&efx->active_queues);
3987 if (pending) {
3988 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
3989 pending);
3990 return -ETIMEDOUT;
3991 }
3992 }
3993
3994 return 0;
3995}
3996
3997static void efx_ef10_prepare_flr(struct efx_nic *efx)
3998{
3999 atomic_set(&efx->active_queues, 0);
4000}
4001
4002/* Decide whether a filter should be exclusive or else should allow
4003 * delivery to additional recipients. Currently we decide that
4004 * filters for specific local unicast MAC and IP addresses are
4005 * exclusive.
4006 */
4007static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
4008{
4009 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
4010 !is_multicast_ether_addr(spec->loc_mac))
4011 return true;
4012
4013 if ((spec->match_flags &
4014 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
4015 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
4016 if (spec->ether_type == htons(ETH_P_IP) &&
4017 !ipv4_is_multicast(spec->loc_host[0]))
4018 return true;
4019 if (spec->ether_type == htons(ETH_P_IPV6) &&
4020 ((const u8 *)spec->loc_host)[0] != 0xff)
4021 return true;
4022 }
4023
4024 return false;
4025}
4026
4027static struct efx_filter_spec *
4028efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
4029 unsigned int filter_idx)
4030{
4031 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
4032 ~EFX_EF10_FILTER_FLAGS);
4033}
4034
4035static unsigned int
4036efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
4037 unsigned int filter_idx)
4038{
4039 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
4040}
4041
4042static void
4043efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
4044 unsigned int filter_idx,
4045 const struct efx_filter_spec *spec,
4046 unsigned int flags)
4047{
4048 table->entry[filter_idx].spec = (unsigned long)spec | flags;
4049}
4050
4051static void
4052efx_ef10_filter_push_prep_set_match_fields(struct efx_nic *efx,
4053 const struct efx_filter_spec *spec,
4054 efx_dword_t *inbuf)
4055{
4056 enum efx_encap_type encap_type = efx_filter_get_encap_type(spec);
4057 u32 match_fields = 0, uc_match, mc_match;
4058
4059 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4060 efx_ef10_filter_is_exclusive(spec) ?
4061 MC_CMD_FILTER_OP_IN_OP_INSERT :
4062 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
4063
4064 /* Convert match flags and values. Unlike almost
4065 * everything else in MCDI, these fields are in
4066 * network byte order.
4067 */
4068#define COPY_VALUE(value, mcdi_field) \
4069 do { \
4070 match_fields |= \
4071 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
4072 mcdi_field ## _LBN; \
4073 BUILD_BUG_ON( \
4074 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
4075 sizeof(value)); \
4076 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
4077 &value, sizeof(value)); \
4078 } while (0)
4079#define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
4080 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
4081 COPY_VALUE(spec->gen_field, mcdi_field); \
4082 }
4083 /* Handle encap filters first. They will always be mismatch
4084 * (unknown UC or MC) filters
4085 */
4086 if (encap_type) {
4087 /* ether_type and outer_ip_proto need to be variables
4088 * because COPY_VALUE wants to memcpy them
4089 */
4090 __be16 ether_type =
4091 htons(encap_type & EFX_ENCAP_FLAG_IPV6 ?
4092 ETH_P_IPV6 : ETH_P_IP);
4093 u8 vni_type = MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE;
4094 u8 outer_ip_proto;
4095
4096 switch (encap_type & EFX_ENCAP_TYPES_MASK) {
4097 case EFX_ENCAP_TYPE_VXLAN:
4098 vni_type = MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN;
4099 /* fallthrough */
4100 case EFX_ENCAP_TYPE_GENEVE:
4101 COPY_VALUE(ether_type, ETHER_TYPE);
4102 outer_ip_proto = IPPROTO_UDP;
4103 COPY_VALUE(outer_ip_proto, IP_PROTO);
4104 /* We always need to set the type field, even
4105 * though we're not matching on the TNI.
4106 */
4107 MCDI_POPULATE_DWORD_1(inbuf,
4108 FILTER_OP_EXT_IN_VNI_OR_VSID,
4109 FILTER_OP_EXT_IN_VNI_TYPE,
4110 vni_type);
4111 break;
4112 case EFX_ENCAP_TYPE_NVGRE:
4113 COPY_VALUE(ether_type, ETHER_TYPE);
4114 outer_ip_proto = IPPROTO_GRE;
4115 COPY_VALUE(outer_ip_proto, IP_PROTO);
4116 break;
4117 default:
4118 WARN_ON(1);
4119 }
4120
4121 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN;
4122 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN;
4123 } else {
4124 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
4125 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN;
4126 }
4127
4128 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
4129 match_fields |=
4130 is_multicast_ether_addr(spec->loc_mac) ?
4131 1 << mc_match :
4132 1 << uc_match;
4133 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
4134 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
4135 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
4136 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
4137 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
4138 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
4139 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
4140 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
4141 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
4142 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
4143#undef COPY_FIELD
4144#undef COPY_VALUE
4145 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
4146 match_fields);
4147}
4148
4149static void efx_ef10_filter_push_prep(struct efx_nic *efx,
4150 const struct efx_filter_spec *spec,
4151 efx_dword_t *inbuf, u64 handle,
4152 struct efx_rss_context *ctx,
4153 bool replacing)
4154{
4155 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4156 u32 flags = spec->flags;
4157
4158 memset(inbuf, 0, MC_CMD_FILTER_OP_EXT_IN_LEN);
4159
4160 /* If RSS filter, caller better have given us an RSS context */
4161 if (flags & EFX_FILTER_FLAG_RX_RSS) {
4162 /* We don't have the ability to return an error, so we'll just
4163 * log a warning and disable RSS for the filter.
4164 */
4165 if (WARN_ON_ONCE(!ctx))
4166 flags &= ~EFX_FILTER_FLAG_RX_RSS;
4167 else if (WARN_ON_ONCE(ctx->context_id == EFX_EF10_RSS_CONTEXT_INVALID))
4168 flags &= ~EFX_FILTER_FLAG_RX_RSS;
4169 }
4170
4171 if (replacing) {
4172 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4173 MC_CMD_FILTER_OP_IN_OP_REPLACE);
4174 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
4175 } else {
4176 efx_ef10_filter_push_prep_set_match_fields(efx, spec, inbuf);
4177 }
4178
4179 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
4180 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
4181 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
4182 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
4183 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
4184 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
4185 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
4186 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
4187 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
4188 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
4189 0 : spec->dmaq_id);
4190 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
4191 (flags & EFX_FILTER_FLAG_RX_RSS) ?
4192 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
4193 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
4194 if (flags & EFX_FILTER_FLAG_RX_RSS)
4195 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT, ctx->context_id);
4196}
4197
4198static int efx_ef10_filter_push(struct efx_nic *efx,
4199 const struct efx_filter_spec *spec, u64 *handle,
4200 struct efx_rss_context *ctx, bool replacing)
4201{
4202 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
4203 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_EXT_OUT_LEN);
4204 int rc;
4205
4206 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, ctx, replacing);
4207 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
4208 outbuf, sizeof(outbuf), NULL);
4209 if (rc == 0)
4210 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
4211 if (rc == -ENOSPC)
4212 rc = -EBUSY; /* to match efx_farch_filter_insert() */
4213 return rc;
4214}
4215
4216static u32 efx_ef10_filter_mcdi_flags_from_spec(const struct efx_filter_spec *spec)
4217{
4218 enum efx_encap_type encap_type = efx_filter_get_encap_type(spec);
4219 unsigned int match_flags = spec->match_flags;
4220 unsigned int uc_match, mc_match;
4221 u32 mcdi_flags = 0;
4222
4223#define MAP_FILTER_TO_MCDI_FLAG(gen_flag, mcdi_field, encap) { \
4224 unsigned int old_match_flags = match_flags; \
4225 match_flags &= ~EFX_FILTER_MATCH_ ## gen_flag; \
4226 if (match_flags != old_match_flags) \
4227 mcdi_flags |= \
4228 (1 << ((encap) ? \
4229 MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ ## \
4230 mcdi_field ## _LBN : \
4231 MC_CMD_FILTER_OP_EXT_IN_MATCH_ ##\
4232 mcdi_field ## _LBN)); \
4233 }
4234 /* inner or outer based on encap type */
4235 MAP_FILTER_TO_MCDI_FLAG(REM_HOST, SRC_IP, encap_type);
4236 MAP_FILTER_TO_MCDI_FLAG(LOC_HOST, DST_IP, encap_type);
4237 MAP_FILTER_TO_MCDI_FLAG(REM_MAC, SRC_MAC, encap_type);
4238 MAP_FILTER_TO_MCDI_FLAG(REM_PORT, SRC_PORT, encap_type);
4239 MAP_FILTER_TO_MCDI_FLAG(LOC_MAC, DST_MAC, encap_type);
4240 MAP_FILTER_TO_MCDI_FLAG(LOC_PORT, DST_PORT, encap_type);
4241 MAP_FILTER_TO_MCDI_FLAG(ETHER_TYPE, ETHER_TYPE, encap_type);
4242 MAP_FILTER_TO_MCDI_FLAG(IP_PROTO, IP_PROTO, encap_type);
4243 /* always outer */
4244 MAP_FILTER_TO_MCDI_FLAG(INNER_VID, INNER_VLAN, false);
4245 MAP_FILTER_TO_MCDI_FLAG(OUTER_VID, OUTER_VLAN, false);
4246#undef MAP_FILTER_TO_MCDI_FLAG
4247
4248 /* special handling for encap type, and mismatch */
4249 if (encap_type) {
4250 match_flags &= ~EFX_FILTER_MATCH_ENCAP_TYPE;
4251 mcdi_flags |=
4252 (1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN);
4253 mcdi_flags |= (1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN);
4254
4255 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN;
4256 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN;
4257 } else {
4258 uc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
4259 mc_match = MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN;
4260 }
4261
4262 if (match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) {
4263 match_flags &= ~EFX_FILTER_MATCH_LOC_MAC_IG;
4264 mcdi_flags |=
4265 is_multicast_ether_addr(spec->loc_mac) ?
4266 1 << mc_match :
4267 1 << uc_match;
4268 }
4269
4270 /* Did we map them all? */
4271 WARN_ON_ONCE(match_flags);
4272
4273 return mcdi_flags;
4274}
4275
4276static int efx_ef10_filter_pri(struct efx_ef10_filter_table *table,
4277 const struct efx_filter_spec *spec)
4278{
4279 u32 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
4280 unsigned int match_pri;
4281
4282 for (match_pri = 0;
4283 match_pri < table->rx_match_count;
4284 match_pri++)
4285 if (table->rx_match_mcdi_flags[match_pri] == mcdi_flags)
4286 return match_pri;
4287
4288 return -EPROTONOSUPPORT;
4289}
4290
4291static s32 efx_ef10_filter_insert(struct efx_nic *efx,
4292 struct efx_filter_spec *spec,
4293 bool replace_equal)
4294{
4295 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
4296 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4297 struct efx_ef10_filter_table *table;
4298 struct efx_filter_spec *saved_spec;
4299 struct efx_rss_context *ctx = NULL;
4300 unsigned int match_pri, hash;
4301 unsigned int priv_flags;
4302 bool rss_locked = false;
4303 bool replacing = false;
4304 unsigned int depth, i;
4305 int ins_index = -1;
4306 DEFINE_WAIT(wait);
4307 bool is_mc_recip;
4308 s32 rc;
4309
4310 down_read(&efx->filter_sem);
4311 table = efx->filter_state;
4312 down_write(&table->lock);
4313
4314 /* For now, only support RX filters */
4315 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
4316 EFX_FILTER_FLAG_RX) {
4317 rc = -EINVAL;
4318 goto out_unlock;
4319 }
4320
4321 rc = efx_ef10_filter_pri(table, spec);
4322 if (rc < 0)
4323 goto out_unlock;
4324 match_pri = rc;
4325
4326 hash = efx_filter_spec_hash(spec);
4327 is_mc_recip = efx_filter_is_mc_recipient(spec);
4328 if (is_mc_recip)
4329 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
4330
4331 if (spec->flags & EFX_FILTER_FLAG_RX_RSS) {
4332 mutex_lock(&efx->rss_lock);
4333 rss_locked = true;
4334 if (spec->rss_context)
4335 ctx = efx_find_rss_context_entry(efx, spec->rss_context);
4336 else
4337 ctx = &efx->rss_context;
4338 if (!ctx) {
4339 rc = -ENOENT;
4340 goto out_unlock;
4341 }
4342 if (ctx->context_id == EFX_EF10_RSS_CONTEXT_INVALID) {
4343 rc = -EOPNOTSUPP;
4344 goto out_unlock;
4345 }
4346 }
4347
4348 /* Find any existing filters with the same match tuple or
4349 * else a free slot to insert at.
4350 */
4351 for (depth = 1; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
4352 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4353 saved_spec = efx_ef10_filter_entry_spec(table, i);
4354
4355 if (!saved_spec) {
4356 if (ins_index < 0)
4357 ins_index = i;
4358 } else if (efx_filter_spec_equal(spec, saved_spec)) {
4359 if (spec->priority < saved_spec->priority &&
4360 spec->priority != EFX_FILTER_PRI_AUTO) {
4361 rc = -EPERM;
4362 goto out_unlock;
4363 }
4364 if (!is_mc_recip) {
4365 /* This is the only one */
4366 if (spec->priority ==
4367 saved_spec->priority &&
4368 !replace_equal) {
4369 rc = -EEXIST;
4370 goto out_unlock;
4371 }
4372 ins_index = i;
4373 break;
4374 } else if (spec->priority >
4375 saved_spec->priority ||
4376 (spec->priority ==
4377 saved_spec->priority &&
4378 replace_equal)) {
4379 if (ins_index < 0)
4380 ins_index = i;
4381 else
4382 __set_bit(depth, mc_rem_map);
4383 }
4384 }
4385 }
4386
4387 /* Once we reach the maximum search depth, use the first suitable
4388 * slot, or return -EBUSY if there was none
4389 */
4390 if (ins_index < 0) {
4391 rc = -EBUSY;
4392 goto out_unlock;
4393 }
4394
4395 /* Create a software table entry if necessary. */
4396 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
4397 if (saved_spec) {
4398 if (spec->priority == EFX_FILTER_PRI_AUTO &&
4399 saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
4400 /* Just make sure it won't be removed */
4401 if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
4402 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
4403 table->entry[ins_index].spec &=
4404 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
4405 rc = ins_index;
4406 goto out_unlock;
4407 }
4408 replacing = true;
4409 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
4410 } else {
4411 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
4412 if (!saved_spec) {
4413 rc = -ENOMEM;
4414 goto out_unlock;
4415 }
4416 *saved_spec = *spec;
4417 priv_flags = 0;
4418 }
4419 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
4420
4421 /* Actually insert the filter on the HW */
4422 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
4423 ctx, replacing);
4424
4425 if (rc == -EINVAL && nic_data->must_realloc_vis)
4426 /* The MC rebooted under us, causing it to reject our filter
4427 * insertion as pointing to an invalid VI (spec->dmaq_id).
4428 */
4429 rc = -EAGAIN;
4430
4431 /* Finalise the software table entry */
4432 if (rc == 0) {
4433 if (replacing) {
4434 /* Update the fields that may differ */
4435 if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
4436 saved_spec->flags |=
4437 EFX_FILTER_FLAG_RX_OVER_AUTO;
4438 saved_spec->priority = spec->priority;
4439 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
4440 saved_spec->flags |= spec->flags;
4441 saved_spec->rss_context = spec->rss_context;
4442 saved_spec->dmaq_id = spec->dmaq_id;
4443 }
4444 } else if (!replacing) {
4445 kfree(saved_spec);
4446 saved_spec = NULL;
4447 } else {
4448 /* We failed to replace, so the old filter is still present.
4449 * Roll back the software table to reflect this. In fact the
4450 * efx_ef10_filter_set_entry() call below will do the right
4451 * thing, so nothing extra is needed here.
4452 */
4453 }
4454 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
4455
4456 /* Remove and finalise entries for lower-priority multicast
4457 * recipients
4458 */
4459 if (is_mc_recip) {
4460 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
4461 unsigned int depth, i;
4462
4463 memset(inbuf, 0, sizeof(inbuf));
4464
4465 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
4466 if (!test_bit(depth, mc_rem_map))
4467 continue;
4468
4469 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4470 saved_spec = efx_ef10_filter_entry_spec(table, i);
4471 priv_flags = efx_ef10_filter_entry_flags(table, i);
4472
4473 if (rc == 0) {
4474 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4475 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4476 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4477 table->entry[i].handle);
4478 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
4479 inbuf, sizeof(inbuf),
4480 NULL, 0, NULL);
4481 }
4482
4483 if (rc == 0) {
4484 kfree(saved_spec);
4485 saved_spec = NULL;
4486 priv_flags = 0;
4487 }
4488 efx_ef10_filter_set_entry(table, i, saved_spec,
4489 priv_flags);
4490 }
4491 }
4492
4493 /* If successful, return the inserted filter ID */
4494 if (rc == 0)
4495 rc = efx_ef10_make_filter_id(match_pri, ins_index);
4496
4497out_unlock:
4498 if (rss_locked)
4499 mutex_unlock(&efx->rss_lock);
4500 up_write(&table->lock);
4501 up_read(&efx->filter_sem);
4502 return rc;
4503}
4504
4505static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
4506{
4507 /* no need to do anything here on EF10 */
4508}
4509
4510/* Remove a filter.
4511 * If !by_index, remove by ID
4512 * If by_index, remove by index
4513 * Filter ID may come from userland and must be range-checked.
4514 * Caller must hold efx->filter_sem for read, and efx->filter_state->lock
4515 * for write.
4516 */
4517static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
4518 unsigned int priority_mask,
4519 u32 filter_id, bool by_index)
4520{
4521 unsigned int filter_idx = efx_ef10_filter_get_unsafe_id(filter_id);
4522 struct efx_ef10_filter_table *table = efx->filter_state;
4523 MCDI_DECLARE_BUF(inbuf,
4524 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
4525 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
4526 struct efx_filter_spec *spec;
4527 DEFINE_WAIT(wait);
4528 int rc;
4529
4530 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4531 if (!spec ||
4532 (!by_index &&
4533 efx_ef10_filter_pri(table, spec) !=
4534 efx_ef10_filter_get_unsafe_pri(filter_id)))
4535 return -ENOENT;
4536
4537 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
4538 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
4539 /* Just remove flags */
4540 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
4541 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
4542 return 0;
4543 }
4544
4545 if (!(priority_mask & (1U << spec->priority)))
4546 return -ENOENT;
4547
4548 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
4549 /* Reset to an automatic filter */
4550
4551 struct efx_filter_spec new_spec = *spec;
4552
4553 new_spec.priority = EFX_FILTER_PRI_AUTO;
4554 new_spec.flags = (EFX_FILTER_FLAG_RX |
4555 (efx_rss_active(&efx->rss_context) ?
4556 EFX_FILTER_FLAG_RX_RSS : 0));
4557 new_spec.dmaq_id = 0;
4558 new_spec.rss_context = 0;
4559 rc = efx_ef10_filter_push(efx, &new_spec,
4560 &table->entry[filter_idx].handle,
4561 &efx->rss_context,
4562 true);
4563
4564 if (rc == 0)
4565 *spec = new_spec;
4566 } else {
4567 /* Really remove the filter */
4568
4569 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4570 efx_ef10_filter_is_exclusive(spec) ?
4571 MC_CMD_FILTER_OP_IN_OP_REMOVE :
4572 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4573 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4574 table->entry[filter_idx].handle);
4575 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP,
4576 inbuf, sizeof(inbuf), NULL, 0, NULL);
4577
4578 if ((rc == 0) || (rc == -ENOENT)) {
4579 /* Filter removed OK or didn't actually exist */
4580 kfree(spec);
4581 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4582 } else {
4583 efx_mcdi_display_error(efx, MC_CMD_FILTER_OP,
4584 MC_CMD_FILTER_OP_EXT_IN_LEN,
4585 NULL, 0, rc);
4586 }
4587 }
4588
4589 return rc;
4590}
4591
4592static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
4593 enum efx_filter_priority priority,
4594 u32 filter_id)
4595{
4596 struct efx_ef10_filter_table *table;
4597 int rc;
4598
4599 down_read(&efx->filter_sem);
4600 table = efx->filter_state;
4601 down_write(&table->lock);
4602 rc = efx_ef10_filter_remove_internal(efx, 1U << priority, filter_id,
4603 false);
4604 up_write(&table->lock);
4605 up_read(&efx->filter_sem);
4606 return rc;
4607}
4608
4609/* Caller must hold efx->filter_sem for read */
4610static void efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
4611 enum efx_filter_priority priority,
4612 u32 filter_id)
4613{
4614 struct efx_ef10_filter_table *table = efx->filter_state;
4615
4616 if (filter_id == EFX_EF10_FILTER_ID_INVALID)
4617 return;
4618
4619 down_write(&table->lock);
4620 efx_ef10_filter_remove_internal(efx, 1U << priority, filter_id,
4621 true);
4622 up_write(&table->lock);
4623}
4624
4625static int efx_ef10_filter_get_safe(struct efx_nic *efx,
4626 enum efx_filter_priority priority,
4627 u32 filter_id, struct efx_filter_spec *spec)
4628{
4629 unsigned int filter_idx = efx_ef10_filter_get_unsafe_id(filter_id);
4630 const struct efx_filter_spec *saved_spec;
4631 struct efx_ef10_filter_table *table;
4632 int rc;
4633
4634 down_read(&efx->filter_sem);
4635 table = efx->filter_state;
4636 down_read(&table->lock);
4637 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
4638 if (saved_spec && saved_spec->priority == priority &&
4639 efx_ef10_filter_pri(table, saved_spec) ==
4640 efx_ef10_filter_get_unsafe_pri(filter_id)) {
4641 *spec = *saved_spec;
4642 rc = 0;
4643 } else {
4644 rc = -ENOENT;
4645 }
4646 up_read(&table->lock);
4647 up_read(&efx->filter_sem);
4648 return rc;
4649}
4650
4651static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
4652 enum efx_filter_priority priority)
4653{
4654 struct efx_ef10_filter_table *table;
4655 unsigned int priority_mask;
4656 unsigned int i;
4657 int rc;
4658
4659 priority_mask = (((1U << (priority + 1)) - 1) &
4660 ~(1U << EFX_FILTER_PRI_AUTO));
4661
4662 down_read(&efx->filter_sem);
4663 table = efx->filter_state;
4664 down_write(&table->lock);
4665 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4666 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
4667 i, true);
4668 if (rc && rc != -ENOENT)
4669 break;
4670 rc = 0;
4671 }
4672
4673 up_write(&table->lock);
4674 up_read(&efx->filter_sem);
4675 return rc;
4676}
4677
4678static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
4679 enum efx_filter_priority priority)
4680{
4681 struct efx_ef10_filter_table *table;
4682 unsigned int filter_idx;
4683 s32 count = 0;
4684
4685 down_read(&efx->filter_sem);
4686 table = efx->filter_state;
4687 down_read(&table->lock);
4688 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4689 if (table->entry[filter_idx].spec &&
4690 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
4691 priority)
4692 ++count;
4693 }
4694 up_read(&table->lock);
4695 up_read(&efx->filter_sem);
4696 return count;
4697}
4698
4699static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
4700{
4701 struct efx_ef10_filter_table *table = efx->filter_state;
4702
4703 return table->rx_match_count * HUNT_FILTER_TBL_ROWS * 2;
4704}
4705
4706static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
4707 enum efx_filter_priority priority,
4708 u32 *buf, u32 size)
4709{
4710 struct efx_ef10_filter_table *table;
4711 struct efx_filter_spec *spec;
4712 unsigned int filter_idx;
4713 s32 count = 0;
4714
4715 down_read(&efx->filter_sem);
4716 table = efx->filter_state;
4717 down_read(&table->lock);
4718
4719 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4720 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4721 if (spec && spec->priority == priority) {
4722 if (count == size) {
4723 count = -EMSGSIZE;
4724 break;
4725 }
4726 buf[count++] =
4727 efx_ef10_make_filter_id(
4728 efx_ef10_filter_pri(table, spec),
4729 filter_idx);
4730 }
4731 }
4732 up_read(&table->lock);
4733 up_read(&efx->filter_sem);
4734 return count;
4735}
4736
4737#ifdef CONFIG_RFS_ACCEL
4738
4739static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
4740 unsigned int filter_idx)
4741{
4742 struct efx_filter_spec *spec, saved_spec;
4743 struct efx_ef10_filter_table *table;
4744 struct efx_arfs_rule *rule = NULL;
4745 bool ret = true, force = false;
4746 u16 arfs_id;
4747
4748 down_read(&efx->filter_sem);
4749 table = efx->filter_state;
4750 down_write(&table->lock);
4751 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4752
4753 if (!spec || spec->priority != EFX_FILTER_PRI_HINT)
4754 goto out_unlock;
4755
4756 spin_lock_bh(&efx->rps_hash_lock);
4757 if (!efx->rps_hash_table) {
4758 /* In the absence of the table, we always return 0 to ARFS. */
4759 arfs_id = 0;
4760 } else {
4761 rule = efx_rps_hash_find(efx, spec);
4762 if (!rule)
4763 /* ARFS table doesn't know of this filter, so remove it */
4764 goto expire;
4765 arfs_id = rule->arfs_id;
4766 ret = efx_rps_check_rule(rule, filter_idx, &force);
4767 if (force)
4768 goto expire;
4769 if (!ret) {
4770 spin_unlock_bh(&efx->rps_hash_lock);
4771 goto out_unlock;
4772 }
4773 }
4774 if (!rps_may_expire_flow(efx->net_dev, spec->dmaq_id, flow_id, arfs_id))
4775 ret = false;
4776 else if (rule)
4777 rule->filter_id = EFX_ARFS_FILTER_ID_REMOVING;
4778expire:
4779 saved_spec = *spec; /* remove operation will kfree spec */
4780 spin_unlock_bh(&efx->rps_hash_lock);
4781 /* At this point (since we dropped the lock), another thread might queue
4782 * up a fresh insertion request (but the actual insertion will be held
4783 * up by our possession of the filter table lock). In that case, it
4784 * will set rule->filter_id to EFX_ARFS_FILTER_ID_PENDING, meaning that
4785 * the rule is not removed by efx_rps_hash_del() below.
4786 */
4787 if (ret)
4788 ret = efx_ef10_filter_remove_internal(efx, 1U << spec->priority,
4789 filter_idx, true) == 0;
4790 /* While we can't safely dereference rule (we dropped the lock), we can
4791 * still test it for NULL.
4792 */
4793 if (ret && rule) {
4794 /* Expiring, so remove entry from ARFS table */
4795 spin_lock_bh(&efx->rps_hash_lock);
4796 efx_rps_hash_del(efx, &saved_spec);
4797 spin_unlock_bh(&efx->rps_hash_lock);
4798 }
4799out_unlock:
4800 up_write(&table->lock);
4801 up_read(&efx->filter_sem);
4802 return ret;
4803}
4804
4805#endif /* CONFIG_RFS_ACCEL */
4806
4807static int efx_ef10_filter_match_flags_from_mcdi(bool encap, u32 mcdi_flags)
4808{
4809 int match_flags = 0;
4810
4811#define MAP_FLAG(gen_flag, mcdi_field) do { \
4812 u32 old_mcdi_flags = mcdi_flags; \
4813 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ ## \
4814 mcdi_field ## _LBN); \
4815 if (mcdi_flags != old_mcdi_flags) \
4816 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
4817 } while (0)
4818
4819 if (encap) {
4820 /* encap filters must specify encap type */
4821 match_flags |= EFX_FILTER_MATCH_ENCAP_TYPE;
4822 /* and imply ethertype and ip proto */
4823 mcdi_flags &=
4824 ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN);
4825 mcdi_flags &=
4826 ~(1 << MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN);
4827 /* VLAN tags refer to the outer packet */
4828 MAP_FLAG(INNER_VID, INNER_VLAN);
4829 MAP_FLAG(OUTER_VID, OUTER_VLAN);
4830 /* everything else refers to the inner packet */
4831 MAP_FLAG(LOC_MAC_IG, IFRM_UNKNOWN_UCAST_DST);
4832 MAP_FLAG(LOC_MAC_IG, IFRM_UNKNOWN_MCAST_DST);
4833 MAP_FLAG(REM_HOST, IFRM_SRC_IP);
4834 MAP_FLAG(LOC_HOST, IFRM_DST_IP);
4835 MAP_FLAG(REM_MAC, IFRM_SRC_MAC);
4836 MAP_FLAG(REM_PORT, IFRM_SRC_PORT);
4837 MAP_FLAG(LOC_MAC, IFRM_DST_MAC);
4838 MAP_FLAG(LOC_PORT, IFRM_DST_PORT);
4839 MAP_FLAG(ETHER_TYPE, IFRM_ETHER_TYPE);
4840 MAP_FLAG(IP_PROTO, IFRM_IP_PROTO);
4841 } else {
4842 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
4843 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
4844 MAP_FLAG(REM_HOST, SRC_IP);
4845 MAP_FLAG(LOC_HOST, DST_IP);
4846 MAP_FLAG(REM_MAC, SRC_MAC);
4847 MAP_FLAG(REM_PORT, SRC_PORT);
4848 MAP_FLAG(LOC_MAC, DST_MAC);
4849 MAP_FLAG(LOC_PORT, DST_PORT);
4850 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
4851 MAP_FLAG(INNER_VID, INNER_VLAN);
4852 MAP_FLAG(OUTER_VID, OUTER_VLAN);
4853 MAP_FLAG(IP_PROTO, IP_PROTO);
4854 }
4855#undef MAP_FLAG
4856
4857 /* Did we map them all? */
4858 if (mcdi_flags)
4859 return -EINVAL;
4860
4861 return match_flags;
4862}
4863
4864static void efx_ef10_filter_cleanup_vlans(struct efx_nic *efx)
4865{
4866 struct efx_ef10_filter_table *table = efx->filter_state;
4867 struct efx_ef10_filter_vlan *vlan, *next_vlan;
4868
4869 /* See comment in efx_ef10_filter_table_remove() */
4870 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4871 return;
4872
4873 if (!table)
4874 return;
4875
4876 list_for_each_entry_safe(vlan, next_vlan, &table->vlan_list, list)
4877 efx_ef10_filter_del_vlan_internal(efx, vlan);
4878}
4879
4880static bool efx_ef10_filter_match_supported(struct efx_ef10_filter_table *table,
4881 bool encap,
4882 enum efx_filter_match_flags match_flags)
4883{
4884 unsigned int match_pri;
4885 int mf;
4886
4887 for (match_pri = 0;
4888 match_pri < table->rx_match_count;
4889 match_pri++) {
4890 mf = efx_ef10_filter_match_flags_from_mcdi(encap,
4891 table->rx_match_mcdi_flags[match_pri]);
4892 if (mf == match_flags)
4893 return true;
4894 }
4895
4896 return false;
4897}
4898
4899static int
4900efx_ef10_filter_table_probe_matches(struct efx_nic *efx,
4901 struct efx_ef10_filter_table *table,
4902 bool encap)
4903{
4904 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
4905 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
4906 unsigned int pd_match_pri, pd_match_count;
4907 size_t outlen;
4908 int rc;
4909
4910 /* Find out which RX filter types are supported, and their priorities */
4911 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
4912 encap ?
4913 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES :
4914 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
4915 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
4916 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
4917 &outlen);
4918 if (rc)
4919 return rc;
4920
4921 pd_match_count = MCDI_VAR_ARRAY_LEN(
4922 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
4923
4924 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
4925 u32 mcdi_flags =
4926 MCDI_ARRAY_DWORD(
4927 outbuf,
4928 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
4929 pd_match_pri);
4930 rc = efx_ef10_filter_match_flags_from_mcdi(encap, mcdi_flags);
4931 if (rc < 0) {
4932 netif_dbg(efx, probe, efx->net_dev,
4933 "%s: fw flags %#x pri %u not supported in driver\n",
4934 __func__, mcdi_flags, pd_match_pri);
4935 } else {
4936 netif_dbg(efx, probe, efx->net_dev,
4937 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
4938 __func__, mcdi_flags, pd_match_pri,
4939 rc, table->rx_match_count);
4940 table->rx_match_mcdi_flags[table->rx_match_count] = mcdi_flags;
4941 table->rx_match_count++;
4942 }
4943 }
4944
4945 return 0;
4946}
4947
4948static int efx_ef10_filter_table_probe(struct efx_nic *efx)
4949{
4950 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4951 struct net_device *net_dev = efx->net_dev;
4952 struct efx_ef10_filter_table *table;
4953 struct efx_ef10_vlan *vlan;
4954 int rc;
4955
4956 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4957 return -EINVAL;
4958
4959 if (efx->filter_state) /* already probed */
4960 return 0;
4961
4962 table = kzalloc(sizeof(*table), GFP_KERNEL);
4963 if (!table)
4964 return -ENOMEM;
4965
4966 table->rx_match_count = 0;
4967 rc = efx_ef10_filter_table_probe_matches(efx, table, false);
4968 if (rc)
4969 goto fail;
4970 if (nic_data->datapath_caps &
4971 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))
4972 rc = efx_ef10_filter_table_probe_matches(efx, table, true);
4973 if (rc)
4974 goto fail;
4975 if ((efx_supported_features(efx) & NETIF_F_HW_VLAN_CTAG_FILTER) &&
4976 !(efx_ef10_filter_match_supported(table, false,
4977 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC)) &&
4978 efx_ef10_filter_match_supported(table, false,
4979 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC_IG)))) {
4980 netif_info(efx, probe, net_dev,
4981 "VLAN filters are not supported in this firmware variant\n");
4982 net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4983 efx->fixed_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4984 net_dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4985 }
4986
4987 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
4988 if (!table->entry) {
4989 rc = -ENOMEM;
4990 goto fail;
4991 }
4992
4993 table->mc_promisc_last = false;
4994 table->vlan_filter =
4995 !!(efx->net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
4996 INIT_LIST_HEAD(&table->vlan_list);
4997 init_rwsem(&table->lock);
4998
4999 efx->filter_state = table;
5000
5001 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
5002 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
5003 if (rc)
5004 goto fail_add_vlan;
5005 }
5006
5007 return 0;
5008
5009fail_add_vlan:
5010 efx_ef10_filter_cleanup_vlans(efx);
5011 efx->filter_state = NULL;
5012fail:
5013 kfree(table);
5014 return rc;
5015}
5016
5017/* Caller must hold efx->filter_sem for read if race against
5018 * efx_ef10_filter_table_remove() is possible
5019 */
5020static void efx_ef10_filter_table_restore(struct efx_nic *efx)
5021{
5022 struct efx_ef10_filter_table *table = efx->filter_state;
5023 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5024 unsigned int invalid_filters = 0, failed = 0;
5025 struct efx_ef10_filter_vlan *vlan;
5026 struct efx_filter_spec *spec;
5027 struct efx_rss_context *ctx;
5028 unsigned int filter_idx;
5029 u32 mcdi_flags;
5030 int match_pri;
5031 int rc, i;
5032
5033 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
5034
5035 if (!nic_data->must_restore_filters)
5036 return;
5037
5038 if (!table)
5039 return;
5040
5041 down_write(&table->lock);
5042 mutex_lock(&efx->rss_lock);
5043
5044 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
5045 spec = efx_ef10_filter_entry_spec(table, filter_idx);
5046 if (!spec)
5047 continue;
5048
5049 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
5050 match_pri = 0;
5051 while (match_pri < table->rx_match_count &&
5052 table->rx_match_mcdi_flags[match_pri] != mcdi_flags)
5053 ++match_pri;
5054 if (match_pri >= table->rx_match_count) {
5055 invalid_filters++;
5056 goto not_restored;
5057 }
5058 if (spec->rss_context)
5059 ctx = efx_find_rss_context_entry(efx, spec->rss_context);
5060 else
5061 ctx = &efx->rss_context;
5062 if (spec->flags & EFX_FILTER_FLAG_RX_RSS) {
5063 if (!ctx) {
5064 netif_warn(efx, drv, efx->net_dev,
5065 "Warning: unable to restore a filter with nonexistent RSS context %u.\n",
5066 spec->rss_context);
5067 invalid_filters++;
5068 goto not_restored;
5069 }
5070 if (ctx->context_id == EFX_EF10_RSS_CONTEXT_INVALID) {
5071 netif_warn(efx, drv, efx->net_dev,
5072 "Warning: unable to restore a filter with RSS context %u as it was not created.\n",
5073 spec->rss_context);
5074 invalid_filters++;
5075 goto not_restored;
5076 }
5077 }
5078
5079 rc = efx_ef10_filter_push(efx, spec,
5080 &table->entry[filter_idx].handle,
5081 ctx, false);
5082 if (rc)
5083 failed++;
5084
5085 if (rc) {
5086not_restored:
5087 list_for_each_entry(vlan, &table->vlan_list, list)
5088 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; ++i)
5089 if (vlan->default_filters[i] == filter_idx)
5090 vlan->default_filters[i] =
5091 EFX_EF10_FILTER_ID_INVALID;
5092
5093 kfree(spec);
5094 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
5095 }
5096 }
5097
5098 mutex_unlock(&efx->rss_lock);
5099 up_write(&table->lock);
5100
5101 /* This can happen validly if the MC's capabilities have changed, so
5102 * is not an error.
5103 */
5104 if (invalid_filters)
5105 netif_dbg(efx, drv, efx->net_dev,
5106 "Did not restore %u filters that are now unsupported.\n",
5107 invalid_filters);
5108
5109 if (failed)
5110 netif_err(efx, hw, efx->net_dev,
5111 "unable to restore %u filters\n", failed);
5112 else
5113 nic_data->must_restore_filters = false;
5114}
5115
5116static void efx_ef10_filter_table_remove(struct efx_nic *efx)
5117{
5118 struct efx_ef10_filter_table *table = efx->filter_state;
5119 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_EXT_IN_LEN);
5120 struct efx_filter_spec *spec;
5121 unsigned int filter_idx;
5122 int rc;
5123
5124 efx_ef10_filter_cleanup_vlans(efx);
5125 efx->filter_state = NULL;
5126 /* If we were called without locking, then it's not safe to free
5127 * the table as others might be using it. So we just WARN, leak
5128 * the memory, and potentially get an inconsistent filter table
5129 * state.
5130 * This should never actually happen.
5131 */
5132 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5133 return;
5134
5135 if (!table)
5136 return;
5137
5138 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
5139 spec = efx_ef10_filter_entry_spec(table, filter_idx);
5140 if (!spec)
5141 continue;
5142
5143 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
5144 efx_ef10_filter_is_exclusive(spec) ?
5145 MC_CMD_FILTER_OP_IN_OP_REMOVE :
5146 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
5147 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
5148 table->entry[filter_idx].handle);
5149 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP, inbuf,
5150 sizeof(inbuf), NULL, 0, NULL);
5151 if (rc)
5152 netif_info(efx, drv, efx->net_dev,
5153 "%s: filter %04x remove failed\n",
5154 __func__, filter_idx);
5155 kfree(spec);
5156 }
5157
5158 vfree(table->entry);
5159 kfree(table);
5160}
5161
5162static void efx_ef10_filter_mark_one_old(struct efx_nic *efx, uint16_t *id)
5163{
5164 struct efx_ef10_filter_table *table = efx->filter_state;
5165 unsigned int filter_idx;
5166
5167 efx_rwsem_assert_write_locked(&table->lock);
5168
5169 if (*id != EFX_EF10_FILTER_ID_INVALID) {
5170 filter_idx = efx_ef10_filter_get_unsafe_id(*id);
5171 if (!table->entry[filter_idx].spec)
5172 netif_dbg(efx, drv, efx->net_dev,
5173 "marked null spec old %04x:%04x\n", *id,
5174 filter_idx);
5175 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
5176 *id = EFX_EF10_FILTER_ID_INVALID;
5177 }
5178}
5179
5180/* Mark old per-VLAN filters that may need to be removed */
5181static void _efx_ef10_filter_vlan_mark_old(struct efx_nic *efx,
5182 struct efx_ef10_filter_vlan *vlan)
5183{
5184 struct efx_ef10_filter_table *table = efx->filter_state;
5185 unsigned int i;
5186
5187 for (i = 0; i < table->dev_uc_count; i++)
5188 efx_ef10_filter_mark_one_old(efx, &vlan->uc[i]);
5189 for (i = 0; i < table->dev_mc_count; i++)
5190 efx_ef10_filter_mark_one_old(efx, &vlan->mc[i]);
5191 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5192 efx_ef10_filter_mark_one_old(efx, &vlan->default_filters[i]);
5193}
5194
5195/* Mark old filters that may need to be removed.
5196 * Caller must hold efx->filter_sem for read if race against
5197 * efx_ef10_filter_table_remove() is possible
5198 */
5199static void efx_ef10_filter_mark_old(struct efx_nic *efx)
5200{
5201 struct efx_ef10_filter_table *table = efx->filter_state;
5202 struct efx_ef10_filter_vlan *vlan;
5203
5204 down_write(&table->lock);
5205 list_for_each_entry(vlan, &table->vlan_list, list)
5206 _efx_ef10_filter_vlan_mark_old(efx, vlan);
5207 up_write(&table->lock);
5208}
5209
5210static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx)
5211{
5212 struct efx_ef10_filter_table *table = efx->filter_state;
5213 struct net_device *net_dev = efx->net_dev;
5214 struct netdev_hw_addr *uc;
5215 unsigned int i;
5216
5217 table->uc_promisc = !!(net_dev->flags & IFF_PROMISC);
5218 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
5219 i = 1;
5220 netdev_for_each_uc_addr(uc, net_dev) {
5221 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
5222 table->uc_promisc = true;
5223 break;
5224 }
5225 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
5226 i++;
5227 }
5228
5229 table->dev_uc_count = i;
5230}
5231
5232static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx)
5233{
5234 struct efx_ef10_filter_table *table = efx->filter_state;
5235 struct net_device *net_dev = efx->net_dev;
5236 struct netdev_hw_addr *mc;
5237 unsigned int i;
5238
5239 table->mc_overflow = false;
5240 table->mc_promisc = !!(net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI));
5241
5242 i = 0;
5243 netdev_for_each_mc_addr(mc, net_dev) {
5244 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
5245 table->mc_promisc = true;
5246 table->mc_overflow = true;
5247 break;
5248 }
5249 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
5250 i++;
5251 }
5252
5253 table->dev_mc_count = i;
5254}
5255
5256static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
5257 struct efx_ef10_filter_vlan *vlan,
5258 bool multicast, bool rollback)
5259{
5260 struct efx_ef10_filter_table *table = efx->filter_state;
5261 struct efx_ef10_dev_addr *addr_list;
5262 enum efx_filter_flags filter_flags;
5263 struct efx_filter_spec spec;
5264 u8 baddr[ETH_ALEN];
5265 unsigned int i, j;
5266 int addr_count;
5267 u16 *ids;
5268 int rc;
5269
5270 if (multicast) {
5271 addr_list = table->dev_mc_list;
5272 addr_count = table->dev_mc_count;
5273 ids = vlan->mc;
5274 } else {
5275 addr_list = table->dev_uc_list;
5276 addr_count = table->dev_uc_count;
5277 ids = vlan->uc;
5278 }
5279
5280 filter_flags = efx_rss_active(&efx->rss_context) ? EFX_FILTER_FLAG_RX_RSS : 0;
5281
5282 /* Insert/renew filters */
5283 for (i = 0; i < addr_count; i++) {
5284 EFX_WARN_ON_PARANOID(ids[i] != EFX_EF10_FILTER_ID_INVALID);
5285 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
5286 efx_filter_set_eth_local(&spec, vlan->vid, addr_list[i].addr);
5287 rc = efx_ef10_filter_insert(efx, &spec, true);
5288 if (rc < 0) {
5289 if (rollback) {
5290 netif_info(efx, drv, efx->net_dev,
5291 "efx_ef10_filter_insert failed rc=%d\n",
5292 rc);
5293 /* Fall back to promiscuous */
5294 for (j = 0; j < i; j++) {
5295 efx_ef10_filter_remove_unsafe(
5296 efx, EFX_FILTER_PRI_AUTO,
5297 ids[j]);
5298 ids[j] = EFX_EF10_FILTER_ID_INVALID;
5299 }
5300 return rc;
5301 } else {
5302 /* keep invalid ID, and carry on */
5303 }
5304 } else {
5305 ids[i] = efx_ef10_filter_get_unsafe_id(rc);
5306 }
5307 }
5308
5309 if (multicast && rollback) {
5310 /* Also need an Ethernet broadcast filter */
5311 EFX_WARN_ON_PARANOID(vlan->default_filters[EFX_EF10_BCAST] !=
5312 EFX_EF10_FILTER_ID_INVALID);
5313 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
5314 eth_broadcast_addr(baddr);
5315 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
5316 rc = efx_ef10_filter_insert(efx, &spec, true);
5317 if (rc < 0) {
5318 netif_warn(efx, drv, efx->net_dev,
5319 "Broadcast filter insert failed rc=%d\n", rc);
5320 /* Fall back to promiscuous */
5321 for (j = 0; j < i; j++) {
5322 efx_ef10_filter_remove_unsafe(
5323 efx, EFX_FILTER_PRI_AUTO,
5324 ids[j]);
5325 ids[j] = EFX_EF10_FILTER_ID_INVALID;
5326 }
5327 return rc;
5328 } else {
5329 vlan->default_filters[EFX_EF10_BCAST] =
5330 efx_ef10_filter_get_unsafe_id(rc);
5331 }
5332 }
5333
5334 return 0;
5335}
5336
5337static int efx_ef10_filter_insert_def(struct efx_nic *efx,
5338 struct efx_ef10_filter_vlan *vlan,
5339 enum efx_encap_type encap_type,
5340 bool multicast, bool rollback)
5341{
5342 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5343 enum efx_filter_flags filter_flags;
5344 struct efx_filter_spec spec;
5345 u8 baddr[ETH_ALEN];
5346 int rc;
5347 u16 *id;
5348
5349 filter_flags = efx_rss_active(&efx->rss_context) ? EFX_FILTER_FLAG_RX_RSS : 0;
5350
5351 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
5352
5353 if (multicast)
5354 efx_filter_set_mc_def(&spec);
5355 else
5356 efx_filter_set_uc_def(&spec);
5357
5358 if (encap_type) {
5359 if (nic_data->datapath_caps &
5360 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))
5361 efx_filter_set_encap_type(&spec, encap_type);
5362 else
5363 /* don't insert encap filters on non-supporting
5364 * platforms. ID will be left as INVALID.
5365 */
5366 return 0;
5367 }
5368
5369 if (vlan->vid != EFX_FILTER_VID_UNSPEC)
5370 efx_filter_set_eth_local(&spec, vlan->vid, NULL);
5371
5372 rc = efx_ef10_filter_insert(efx, &spec, true);
5373 if (rc < 0) {
5374 const char *um = multicast ? "Multicast" : "Unicast";
5375 const char *encap_name = "";
5376 const char *encap_ipv = "";
5377
5378 if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5379 EFX_ENCAP_TYPE_VXLAN)
5380 encap_name = "VXLAN ";
5381 else if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5382 EFX_ENCAP_TYPE_NVGRE)
5383 encap_name = "NVGRE ";
5384 else if ((encap_type & EFX_ENCAP_TYPES_MASK) ==
5385 EFX_ENCAP_TYPE_GENEVE)
5386 encap_name = "GENEVE ";
5387 if (encap_type & EFX_ENCAP_FLAG_IPV6)
5388 encap_ipv = "IPv6 ";
5389 else if (encap_type)
5390 encap_ipv = "IPv4 ";
5391
5392 /* unprivileged functions can't insert mismatch filters
5393 * for encapsulated or unicast traffic, so downgrade
5394 * those warnings to debug.
5395 */
5396 netif_cond_dbg(efx, drv, efx->net_dev,
5397 rc == -EPERM && (encap_type || !multicast), warn,
5398 "%s%s%s mismatch filter insert failed rc=%d\n",
5399 encap_name, encap_ipv, um, rc);
5400 } else if (multicast) {
5401 /* mapping from encap types to default filter IDs (multicast) */
5402 static enum efx_ef10_default_filters map[] = {
5403 [EFX_ENCAP_TYPE_NONE] = EFX_EF10_MCDEF,
5404 [EFX_ENCAP_TYPE_VXLAN] = EFX_EF10_VXLAN4_MCDEF,
5405 [EFX_ENCAP_TYPE_NVGRE] = EFX_EF10_NVGRE4_MCDEF,
5406 [EFX_ENCAP_TYPE_GENEVE] = EFX_EF10_GENEVE4_MCDEF,
5407 [EFX_ENCAP_TYPE_VXLAN | EFX_ENCAP_FLAG_IPV6] =
5408 EFX_EF10_VXLAN6_MCDEF,
5409 [EFX_ENCAP_TYPE_NVGRE | EFX_ENCAP_FLAG_IPV6] =
5410 EFX_EF10_NVGRE6_MCDEF,
5411 [EFX_ENCAP_TYPE_GENEVE | EFX_ENCAP_FLAG_IPV6] =
5412 EFX_EF10_GENEVE6_MCDEF,
5413 };
5414
5415 /* quick bounds check (BCAST result impossible) */
5416 BUILD_BUG_ON(EFX_EF10_BCAST != 0);
5417 if (encap_type >= ARRAY_SIZE(map) || map[encap_type] == 0) {
5418 WARN_ON(1);
5419 return -EINVAL;
5420 }
5421 /* then follow map */
5422 id = &vlan->default_filters[map[encap_type]];
5423
5424 EFX_WARN_ON_PARANOID(*id != EFX_EF10_FILTER_ID_INVALID);
5425 *id = efx_ef10_filter_get_unsafe_id(rc);
5426 if (!nic_data->workaround_26807 && !encap_type) {
5427 /* Also need an Ethernet broadcast filter */
5428 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
5429 filter_flags, 0);
5430 eth_broadcast_addr(baddr);
5431 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
5432 rc = efx_ef10_filter_insert(efx, &spec, true);
5433 if (rc < 0) {
5434 netif_warn(efx, drv, efx->net_dev,
5435 "Broadcast filter insert failed rc=%d\n",
5436 rc);
5437 if (rollback) {
5438 /* Roll back the mc_def filter */
5439 efx_ef10_filter_remove_unsafe(
5440 efx, EFX_FILTER_PRI_AUTO,
5441 *id);
5442 *id = EFX_EF10_FILTER_ID_INVALID;
5443 return rc;
5444 }
5445 } else {
5446 EFX_WARN_ON_PARANOID(
5447 vlan->default_filters[EFX_EF10_BCAST] !=
5448 EFX_EF10_FILTER_ID_INVALID);
5449 vlan->default_filters[EFX_EF10_BCAST] =
5450 efx_ef10_filter_get_unsafe_id(rc);
5451 }
5452 }
5453 rc = 0;
5454 } else {
5455 /* mapping from encap types to default filter IDs (unicast) */
5456 static enum efx_ef10_default_filters map[] = {
5457 [EFX_ENCAP_TYPE_NONE] = EFX_EF10_UCDEF,
5458 [EFX_ENCAP_TYPE_VXLAN] = EFX_EF10_VXLAN4_UCDEF,
5459 [EFX_ENCAP_TYPE_NVGRE] = EFX_EF10_NVGRE4_UCDEF,
5460 [EFX_ENCAP_TYPE_GENEVE] = EFX_EF10_GENEVE4_UCDEF,
5461 [EFX_ENCAP_TYPE_VXLAN | EFX_ENCAP_FLAG_IPV6] =
5462 EFX_EF10_VXLAN6_UCDEF,
5463 [EFX_ENCAP_TYPE_NVGRE | EFX_ENCAP_FLAG_IPV6] =
5464 EFX_EF10_NVGRE6_UCDEF,
5465 [EFX_ENCAP_TYPE_GENEVE | EFX_ENCAP_FLAG_IPV6] =
5466 EFX_EF10_GENEVE6_UCDEF,
5467 };
5468
5469 /* quick bounds check (BCAST result impossible) */
5470 BUILD_BUG_ON(EFX_EF10_BCAST != 0);
5471 if (encap_type >= ARRAY_SIZE(map) || map[encap_type] == 0) {
5472 WARN_ON(1);
5473 return -EINVAL;
5474 }
5475 /* then follow map */
5476 id = &vlan->default_filters[map[encap_type]];
5477 EFX_WARN_ON_PARANOID(*id != EFX_EF10_FILTER_ID_INVALID);
5478 *id = rc;
5479 rc = 0;
5480 }
5481 return rc;
5482}
5483
5484/* Remove filters that weren't renewed. */
5485static void efx_ef10_filter_remove_old(struct efx_nic *efx)
5486{
5487 struct efx_ef10_filter_table *table = efx->filter_state;
5488 int remove_failed = 0;
5489 int remove_noent = 0;
5490 int rc;
5491 int i;
5492
5493 down_write(&table->lock);
5494 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
5495 if (READ_ONCE(table->entry[i].spec) &
5496 EFX_EF10_FILTER_FLAG_AUTO_OLD) {
5497 rc = efx_ef10_filter_remove_internal(efx,
5498 1U << EFX_FILTER_PRI_AUTO, i, true);
5499 if (rc == -ENOENT)
5500 remove_noent++;
5501 else if (rc)
5502 remove_failed++;
5503 }
5504 }
5505 up_write(&table->lock);
5506
5507 if (remove_failed)
5508 netif_info(efx, drv, efx->net_dev,
5509 "%s: failed to remove %d filters\n",
5510 __func__, remove_failed);
5511 if (remove_noent)
5512 netif_info(efx, drv, efx->net_dev,
5513 "%s: failed to remove %d non-existent filters\n",
5514 __func__, remove_noent);
5515}
5516
5517static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
5518{
5519 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5520 u8 mac_old[ETH_ALEN];
5521 int rc, rc2;
5522
5523 /* Only reconfigure a PF-created vport */
5524 if (is_zero_ether_addr(nic_data->vport_mac))
5525 return 0;
5526
5527 efx_device_detach_sync(efx);
5528 efx_net_stop(efx->net_dev);
5529 down_write(&efx->filter_sem);
5530 efx_ef10_filter_table_remove(efx);
5531 up_write(&efx->filter_sem);
5532
5533 rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
5534 if (rc)
5535 goto restore_filters;
5536
5537 ether_addr_copy(mac_old, nic_data->vport_mac);
5538 rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
5539 nic_data->vport_mac);
5540 if (rc)
5541 goto restore_vadaptor;
5542
5543 rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
5544 efx->net_dev->dev_addr);
5545 if (!rc) {
5546 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
5547 } else {
5548 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
5549 if (rc2) {
5550 /* Failed to add original MAC, so clear vport_mac */
5551 eth_zero_addr(nic_data->vport_mac);
5552 goto reset_nic;
5553 }
5554 }
5555
5556restore_vadaptor:
5557 rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
5558 if (rc2)
5559 goto reset_nic;
5560restore_filters:
5561 down_write(&efx->filter_sem);
5562 rc2 = efx_ef10_filter_table_probe(efx);
5563 up_write(&efx->filter_sem);
5564 if (rc2)
5565 goto reset_nic;
5566
5567 rc2 = efx_net_open(efx->net_dev);
5568 if (rc2)
5569 goto reset_nic;
5570
5571 efx_device_attach_if_not_resetting(efx);
5572
5573 return rc;
5574
5575reset_nic:
5576 netif_err(efx, drv, efx->net_dev,
5577 "Failed to restore when changing MAC address - scheduling reset\n");
5578 efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
5579
5580 return rc ? rc : rc2;
5581}
5582
5583/* Caller must hold efx->filter_sem for read if race against
5584 * efx_ef10_filter_table_remove() is possible
5585 */
5586static void efx_ef10_filter_vlan_sync_rx_mode(struct efx_nic *efx,
5587 struct efx_ef10_filter_vlan *vlan)
5588{
5589 struct efx_ef10_filter_table *table = efx->filter_state;
5590 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5591
5592 /* Do not install unspecified VID if VLAN filtering is enabled.
5593 * Do not install all specified VIDs if VLAN filtering is disabled.
5594 */
5595 if ((vlan->vid == EFX_FILTER_VID_UNSPEC) == table->vlan_filter)
5596 return;
5597
5598 /* Insert/renew unicast filters */
5599 if (table->uc_promisc) {
5600 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NONE,
5601 false, false);
5602 efx_ef10_filter_insert_addr_list(efx, vlan, false, false);
5603 } else {
5604 /* If any of the filters failed to insert, fall back to
5605 * promiscuous mode - add in the uc_def filter. But keep
5606 * our individual unicast filters.
5607 */
5608 if (efx_ef10_filter_insert_addr_list(efx, vlan, false, false))
5609 efx_ef10_filter_insert_def(efx, vlan,
5610 EFX_ENCAP_TYPE_NONE,
5611 false, false);
5612 }
5613 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN,
5614 false, false);
5615 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN |
5616 EFX_ENCAP_FLAG_IPV6,
5617 false, false);
5618 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE,
5619 false, false);
5620 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE |
5621 EFX_ENCAP_FLAG_IPV6,
5622 false, false);
5623 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE,
5624 false, false);
5625 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE |
5626 EFX_ENCAP_FLAG_IPV6,
5627 false, false);
5628
5629 /* Insert/renew multicast filters */
5630 /* If changing promiscuous state with cascaded multicast filters, remove
5631 * old filters first, so that packets are dropped rather than duplicated
5632 */
5633 if (nic_data->workaround_26807 &&
5634 table->mc_promisc_last != table->mc_promisc)
5635 efx_ef10_filter_remove_old(efx);
5636 if (table->mc_promisc) {
5637 if (nic_data->workaround_26807) {
5638 /* If we failed to insert promiscuous filters, rollback
5639 * and fall back to individual multicast filters
5640 */
5641 if (efx_ef10_filter_insert_def(efx, vlan,
5642 EFX_ENCAP_TYPE_NONE,
5643 true, true)) {
5644 /* Changing promisc state, so remove old filters */
5645 efx_ef10_filter_remove_old(efx);
5646 efx_ef10_filter_insert_addr_list(efx, vlan,
5647 true, false);
5648 }
5649 } else {
5650 /* If we failed to insert promiscuous filters, don't
5651 * rollback. Regardless, also insert the mc_list,
5652 * unless it's incomplete due to overflow
5653 */
5654 efx_ef10_filter_insert_def(efx, vlan,
5655 EFX_ENCAP_TYPE_NONE,
5656 true, false);
5657 if (!table->mc_overflow)
5658 efx_ef10_filter_insert_addr_list(efx, vlan,
5659 true, false);
5660 }
5661 } else {
5662 /* If any filters failed to insert, rollback and fall back to
5663 * promiscuous mode - mc_def filter and maybe broadcast. If
5664 * that fails, roll back again and insert as many of our
5665 * individual multicast filters as we can.
5666 */
5667 if (efx_ef10_filter_insert_addr_list(efx, vlan, true, true)) {
5668 /* Changing promisc state, so remove old filters */
5669 if (nic_data->workaround_26807)
5670 efx_ef10_filter_remove_old(efx);
5671 if (efx_ef10_filter_insert_def(efx, vlan,
5672 EFX_ENCAP_TYPE_NONE,
5673 true, true))
5674 efx_ef10_filter_insert_addr_list(efx, vlan,
5675 true, false);
5676 }
5677 }
5678 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN,
5679 true, false);
5680 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_VXLAN |
5681 EFX_ENCAP_FLAG_IPV6,
5682 true, false);
5683 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE,
5684 true, false);
5685 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_NVGRE |
5686 EFX_ENCAP_FLAG_IPV6,
5687 true, false);
5688 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE,
5689 true, false);
5690 efx_ef10_filter_insert_def(efx, vlan, EFX_ENCAP_TYPE_GENEVE |
5691 EFX_ENCAP_FLAG_IPV6,
5692 true, false);
5693}
5694
5695/* Caller must hold efx->filter_sem for read if race against
5696 * efx_ef10_filter_table_remove() is possible
5697 */
5698static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
5699{
5700 struct efx_ef10_filter_table *table = efx->filter_state;
5701 struct net_device *net_dev = efx->net_dev;
5702 struct efx_ef10_filter_vlan *vlan;
5703 bool vlan_filter;
5704
5705 if (!efx_dev_registered(efx))
5706 return;
5707
5708 if (!table)
5709 return;
5710
5711 efx_ef10_filter_mark_old(efx);
5712
5713 /* Copy/convert the address lists; add the primary station
5714 * address and broadcast address
5715 */
5716 netif_addr_lock_bh(net_dev);
5717 efx_ef10_filter_uc_addr_list(efx);
5718 efx_ef10_filter_mc_addr_list(efx);
5719 netif_addr_unlock_bh(net_dev);
5720
5721 /* If VLAN filtering changes, all old filters are finally removed.
5722 * Do it in advance to avoid conflicts for unicast untagged and
5723 * VLAN 0 tagged filters.
5724 */
5725 vlan_filter = !!(net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
5726 if (table->vlan_filter != vlan_filter) {
5727 table->vlan_filter = vlan_filter;
5728 efx_ef10_filter_remove_old(efx);
5729 }
5730
5731 list_for_each_entry(vlan, &table->vlan_list, list)
5732 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
5733
5734 efx_ef10_filter_remove_old(efx);
5735 table->mc_promisc_last = table->mc_promisc;
5736}
5737
5738static struct efx_ef10_filter_vlan *efx_ef10_filter_find_vlan(struct efx_nic *efx, u16 vid)
5739{
5740 struct efx_ef10_filter_table *table = efx->filter_state;
5741 struct efx_ef10_filter_vlan *vlan;
5742
5743 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
5744
5745 list_for_each_entry(vlan, &table->vlan_list, list) {
5746 if (vlan->vid == vid)
5747 return vlan;
5748 }
5749
5750 return NULL;
5751}
5752
5753static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid)
5754{
5755 struct efx_ef10_filter_table *table = efx->filter_state;
5756 struct efx_ef10_filter_vlan *vlan;
5757 unsigned int i;
5758
5759 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5760 return -EINVAL;
5761
5762 vlan = efx_ef10_filter_find_vlan(efx, vid);
5763 if (WARN_ON(vlan)) {
5764 netif_err(efx, drv, efx->net_dev,
5765 "VLAN %u already added\n", vid);
5766 return -EALREADY;
5767 }
5768
5769 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
5770 if (!vlan)
5771 return -ENOMEM;
5772
5773 vlan->vid = vid;
5774
5775 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
5776 vlan->uc[i] = EFX_EF10_FILTER_ID_INVALID;
5777 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
5778 vlan->mc[i] = EFX_EF10_FILTER_ID_INVALID;
5779 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5780 vlan->default_filters[i] = EFX_EF10_FILTER_ID_INVALID;
5781
5782 list_add_tail(&vlan->list, &table->vlan_list);
5783
5784 if (efx_dev_registered(efx))
5785 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
5786
5787 return 0;
5788}
5789
5790static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
5791 struct efx_ef10_filter_vlan *vlan)
5792{
5793 unsigned int i;
5794
5795 /* See comment in efx_ef10_filter_table_remove() */
5796 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5797 return;
5798
5799 list_del(&vlan->list);
5800
5801 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
5802 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5803 vlan->uc[i]);
5804 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
5805 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5806 vlan->mc[i]);
5807 for (i = 0; i < EFX_EF10_NUM_DEFAULT_FILTERS; i++)
5808 if (vlan->default_filters[i] != EFX_EF10_FILTER_ID_INVALID)
5809 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
5810 vlan->default_filters[i]);
5811
5812 kfree(vlan);
5813}
5814
5815static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid)
5816{
5817 struct efx_ef10_filter_vlan *vlan;
5818
5819 /* See comment in efx_ef10_filter_table_remove() */
5820 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
5821 return;
5822
5823 vlan = efx_ef10_filter_find_vlan(efx, vid);
5824 if (!vlan) {
5825 netif_err(efx, drv, efx->net_dev,
5826 "VLAN %u not found in filter state\n", vid);
5827 return;
5828 }
5829
5830 efx_ef10_filter_del_vlan_internal(efx, vlan);
5831}
5832
5833static int efx_ef10_set_mac_address(struct efx_nic *efx)
5834{
5835 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
5836 struct efx_ef10_nic_data *nic_data = efx->nic_data;
5837 bool was_enabled = efx->port_enabled;
5838 int rc;
5839
5840 efx_device_detach_sync(efx);
5841 efx_net_stop(efx->net_dev);
5842
5843 mutex_lock(&efx->mac_lock);
5844 down_write(&efx->filter_sem);
5845 efx_ef10_filter_table_remove(efx);
5846
5847 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
5848 efx->net_dev->dev_addr);
5849 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
5850 nic_data->vport_id);
5851 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
5852 sizeof(inbuf), NULL, 0, NULL);
5853
5854 efx_ef10_filter_table_probe(efx);
5855 up_write(&efx->filter_sem);
5856 mutex_unlock(&efx->mac_lock);
5857
5858 if (was_enabled)
5859 efx_net_open(efx->net_dev);
5860 efx_device_attach_if_not_resetting(efx);
5861
5862#ifdef CONFIG_SFC_SRIOV
5863 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
5864 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
5865
5866 if (rc == -EPERM) {
5867 struct efx_nic *efx_pf;
5868
5869 /* Switch to PF and change MAC address on vport */
5870 efx_pf = pci_get_drvdata(pci_dev_pf);
5871
5872 rc = efx_ef10_sriov_set_vf_mac(efx_pf,
5873 nic_data->vf_index,
5874 efx->net_dev->dev_addr);
5875 } else if (!rc) {
5876 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
5877 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
5878 unsigned int i;
5879
5880 /* MAC address successfully changed by VF (with MAC
5881 * spoofing) so update the parent PF if possible.
5882 */
5883 for (i = 0; i < efx_pf->vf_count; ++i) {
5884 struct ef10_vf *vf = nic_data->vf + i;
5885
5886 if (vf->efx == efx) {
5887 ether_addr_copy(vf->mac,
5888 efx->net_dev->dev_addr);
5889 return 0;
5890 }
5891 }
5892 }
5893 } else
5894#endif
5895 if (rc == -EPERM) {
5896 netif_err(efx, drv, efx->net_dev,
5897 "Cannot change MAC address; use sfboot to enable"
5898 " mac-spoofing on this interface\n");
5899 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
5900 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
5901 * fall-back to the method of changing the MAC address on the
5902 * vport. This only applies to PFs because such versions of
5903 * MCFW do not support VFs.
5904 */
5905 rc = efx_ef10_vport_set_mac_address(efx);
5906 } else if (rc) {
5907 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
5908 sizeof(inbuf), NULL, 0, rc);
5909 }
5910
5911 return rc;
5912}
5913
5914static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
5915{
5916 efx_ef10_filter_sync_rx_mode(efx);
5917
5918 return efx_mcdi_set_mac(efx);
5919}
5920
5921static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
5922{
5923 efx_ef10_filter_sync_rx_mode(efx);
5924
5925 return 0;
5926}
5927
5928static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
5929{
5930 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
5931
5932 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
5933 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
5934 NULL, 0, NULL);
5935}
5936
5937/* MC BISTs follow a different poll mechanism to phy BISTs.
5938 * The BIST is done in the poll handler on the MC, and the MCDI command
5939 * will block until the BIST is done.
5940 */
5941static int efx_ef10_poll_bist(struct efx_nic *efx)
5942{
5943 int rc;
5944 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
5945 size_t outlen;
5946 u32 result;
5947
5948 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
5949 outbuf, sizeof(outbuf), &outlen);
5950 if (rc != 0)
5951 return rc;
5952
5953 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
5954 return -EIO;
5955
5956 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
5957 switch (result) {
5958 case MC_CMD_POLL_BIST_PASSED:
5959 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
5960 return 0;
5961 case MC_CMD_POLL_BIST_TIMEOUT:
5962 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
5963 return -EIO;
5964 case MC_CMD_POLL_BIST_FAILED:
5965 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
5966 return -EIO;
5967 default:
5968 netif_err(efx, hw, efx->net_dev,
5969 "BIST returned unknown result %u", result);
5970 return -EIO;
5971 }
5972}
5973
5974static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
5975{
5976 int rc;
5977
5978 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
5979
5980 rc = efx_ef10_start_bist(efx, bist_type);
5981 if (rc != 0)
5982 return rc;
5983
5984 return efx_ef10_poll_bist(efx);
5985}
5986
5987static int
5988efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
5989{
5990 int rc, rc2;
5991
5992 efx_reset_down(efx, RESET_TYPE_WORLD);
5993
5994 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
5995 NULL, 0, NULL, 0, NULL);
5996 if (rc != 0)
5997 goto out;
5998
5999 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
6000 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
6001
6002 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
6003
6004out:
6005 if (rc == -EPERM)
6006 rc = 0;
6007 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
6008 return rc ? rc : rc2;
6009}
6010
6011#ifdef CONFIG_SFC_MTD
6012
6013struct efx_ef10_nvram_type_info {
6014 u16 type, type_mask;
6015 u8 port;
6016 const char *name;
6017};
6018
6019static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
6020 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
6021 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
6022 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
6023 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
6024 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
6025 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
6026 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
6027 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
6028 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
6029 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
6030 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
6031};
6032
6033static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
6034 struct efx_mcdi_mtd_partition *part,
6035 unsigned int type)
6036{
6037 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
6038 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
6039 const struct efx_ef10_nvram_type_info *info;
6040 size_t size, erase_size, outlen;
6041 bool protected;
6042 int rc;
6043
6044 for (info = efx_ef10_nvram_types; ; info++) {
6045 if (info ==
6046 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
6047 return -ENODEV;
6048 if ((type & ~info->type_mask) == info->type)
6049 break;
6050 }
6051 if (info->port != efx_port_num(efx))
6052 return -ENODEV;
6053
6054 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
6055 if (rc)
6056 return rc;
6057 if (protected)
6058 return -ENODEV; /* hide it */
6059
6060 part->nvram_type = type;
6061
6062 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
6063 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
6064 outbuf, sizeof(outbuf), &outlen);
6065 if (rc)
6066 return rc;
6067 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
6068 return -EIO;
6069 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
6070 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
6071 part->fw_subtype = MCDI_DWORD(outbuf,
6072 NVRAM_METADATA_OUT_SUBTYPE);
6073
6074 part->common.dev_type_name = "EF10 NVRAM manager";
6075 part->common.type_name = info->name;
6076
6077 part->common.mtd.type = MTD_NORFLASH;
6078 part->common.mtd.flags = MTD_CAP_NORFLASH;
6079 part->common.mtd.size = size;
6080 part->common.mtd.erasesize = erase_size;
6081
6082 return 0;
6083}
6084
6085static int efx_ef10_mtd_probe(struct efx_nic *efx)
6086{
6087 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
6088 struct efx_mcdi_mtd_partition *parts;
6089 size_t outlen, n_parts_total, i, n_parts;
6090 unsigned int type;
6091 int rc;
6092
6093 ASSERT_RTNL();
6094
6095 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
6096 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
6097 outbuf, sizeof(outbuf), &outlen);
6098 if (rc)
6099 return rc;
6100 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
6101 return -EIO;
6102
6103 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
6104 if (n_parts_total >
6105 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
6106 return -EIO;
6107
6108 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
6109 if (!parts)
6110 return -ENOMEM;
6111
6112 n_parts = 0;
6113 for (i = 0; i < n_parts_total; i++) {
6114 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
6115 i);
6116 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
6117 if (rc == 0)
6118 n_parts++;
6119 else if (rc != -ENODEV)
6120 goto fail;
6121 }
6122
6123 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
6124fail:
6125 if (rc)
6126 kfree(parts);
6127 return rc;
6128}
6129
6130#endif /* CONFIG_SFC_MTD */
6131
6132static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
6133{
6134 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
6135}
6136
6137static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
6138 u32 host_time) {}
6139
6140static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
6141 bool temp)
6142{
6143 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
6144 int rc;
6145
6146 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
6147 channel->sync_events_state == SYNC_EVENTS_VALID ||
6148 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
6149 return 0;
6150 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
6151
6152 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
6153 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
6154 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
6155 channel->channel);
6156
6157 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
6158 inbuf, sizeof(inbuf), NULL, 0, NULL);
6159
6160 if (rc != 0)
6161 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
6162 SYNC_EVENTS_DISABLED;
6163
6164 return rc;
6165}
6166
6167static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
6168 bool temp)
6169{
6170 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
6171 int rc;
6172
6173 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
6174 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
6175 return 0;
6176 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
6177 channel->sync_events_state = SYNC_EVENTS_DISABLED;
6178 return 0;
6179 }
6180 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
6181 SYNC_EVENTS_DISABLED;
6182
6183 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
6184 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
6185 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
6186 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
6187 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
6188 channel->channel);
6189
6190 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
6191 inbuf, sizeof(inbuf), NULL, 0, NULL);
6192
6193 return rc;
6194}
6195
6196static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
6197 bool temp)
6198{
6199 int (*set)(struct efx_channel *channel, bool temp);
6200 struct efx_channel *channel;
6201
6202 set = en ?
6203 efx_ef10_rx_enable_timestamping :
6204 efx_ef10_rx_disable_timestamping;
6205
6206 channel = efx_ptp_channel(efx);
6207 if (channel) {
6208 int rc = set(channel, temp);
6209 if (en && rc != 0) {
6210 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
6211 return rc;
6212 }
6213 }
6214
6215 return 0;
6216}
6217
6218static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
6219 struct hwtstamp_config *init)
6220{
6221 return -EOPNOTSUPP;
6222}
6223
6224static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
6225 struct hwtstamp_config *init)
6226{
6227 int rc;
6228
6229 switch (init->rx_filter) {
6230 case HWTSTAMP_FILTER_NONE:
6231 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
6232 /* if TX timestamping is still requested then leave PTP on */
6233 return efx_ptp_change_mode(efx,
6234 init->tx_type != HWTSTAMP_TX_OFF, 0);
6235 case HWTSTAMP_FILTER_ALL:
6236 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
6237 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
6238 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
6239 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
6240 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6241 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6242 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
6243 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6244 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6245 case HWTSTAMP_FILTER_PTP_V2_EVENT:
6246 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6247 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6248 case HWTSTAMP_FILTER_NTP_ALL:
6249 init->rx_filter = HWTSTAMP_FILTER_ALL;
6250 rc = efx_ptp_change_mode(efx, true, 0);
6251 if (!rc)
6252 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
6253 if (rc)
6254 efx_ptp_change_mode(efx, false, 0);
6255 return rc;
6256 default:
6257 return -ERANGE;
6258 }
6259}
6260
6261static int efx_ef10_get_phys_port_id(struct efx_nic *efx,
6262 struct netdev_phys_item_id *ppid)
6263{
6264 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6265
6266 if (!is_valid_ether_addr(nic_data->port_id))
6267 return -EOPNOTSUPP;
6268
6269 ppid->id_len = ETH_ALEN;
6270 memcpy(ppid->id, nic_data->port_id, ppid->id_len);
6271
6272 return 0;
6273}
6274
6275static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid)
6276{
6277 if (proto != htons(ETH_P_8021Q))
6278 return -EINVAL;
6279
6280 return efx_ef10_add_vlan(efx, vid);
6281}
6282
6283static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid)
6284{
6285 if (proto != htons(ETH_P_8021Q))
6286 return -EINVAL;
6287
6288 return efx_ef10_del_vlan(efx, vid);
6289}
6290
6291/* We rely on the MCDI wiping out our TX rings if it made any changes to the
6292 * ports table, ensuring that any TSO descriptors that were made on a now-
6293 * removed tunnel port will be blown away and won't break things when we try
6294 * to transmit them using the new ports table.
6295 */
6296static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading)
6297{
6298 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6299 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX);
6300 MCDI_DECLARE_BUF(outbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN);
6301 bool will_reset = false;
6302 size_t num_entries = 0;
6303 size_t inlen, outlen;
6304 size_t i;
6305 int rc;
6306 efx_dword_t flags_and_num_entries;
6307
6308 WARN_ON(!mutex_is_locked(&nic_data->udp_tunnels_lock));
6309
6310 nic_data->udp_tunnels_dirty = false;
6311
6312 if (!(nic_data->datapath_caps &
6313 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) {
6314 efx_device_attach_if_not_resetting(efx);
6315 return 0;
6316 }
6317
6318 BUILD_BUG_ON(ARRAY_SIZE(nic_data->udp_tunnels) >
6319 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM);
6320
6321 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) {
6322 if (nic_data->udp_tunnels[i].count &&
6323 nic_data->udp_tunnels[i].port) {
6324 efx_dword_t entry;
6325
6326 EFX_POPULATE_DWORD_2(entry,
6327 TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT,
6328 ntohs(nic_data->udp_tunnels[i].port),
6329 TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL,
6330 nic_data->udp_tunnels[i].type);
6331 *_MCDI_ARRAY_DWORD(inbuf,
6332 SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES,
6333 num_entries++) = entry;
6334 }
6335 }
6336
6337 BUILD_BUG_ON((MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST -
6338 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST) * 8 !=
6339 EFX_WORD_1_LBN);
6340 BUILD_BUG_ON(MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN * 8 !=
6341 EFX_WORD_1_WIDTH);
6342 EFX_POPULATE_DWORD_2(flags_and_num_entries,
6343 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING,
6344 !!unloading,
6345 EFX_WORD_1, num_entries);
6346 *_MCDI_DWORD(inbuf, SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS) =
6347 flags_and_num_entries;
6348
6349 inlen = MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num_entries);
6350
6351 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS,
6352 inbuf, inlen, outbuf, sizeof(outbuf), &outlen);
6353 if (rc == -EIO) {
6354 /* Most likely the MC rebooted due to another function also
6355 * setting its tunnel port list. Mark the tunnel port list as
6356 * dirty, so it will be pushed upon coming up from the reboot.
6357 */
6358 nic_data->udp_tunnels_dirty = true;
6359 return 0;
6360 }
6361
6362 if (rc) {
6363 /* expected not available on unprivileged functions */
6364 if (rc != -EPERM)
6365 netif_warn(efx, drv, efx->net_dev,
6366 "Unable to set UDP tunnel ports; rc=%d.\n", rc);
6367 } else if (MCDI_DWORD(outbuf, SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS) &
6368 (1 << MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN)) {
6369 netif_info(efx, drv, efx->net_dev,
6370 "Rebooting MC due to UDP tunnel port list change\n");
6371 will_reset = true;
6372 if (unloading)
6373 /* Delay for the MC reset to complete. This will make
6374 * unloading other functions a bit smoother. This is a
6375 * race, but the other unload will work whichever way
6376 * it goes, this just avoids an unnecessary error
6377 * message.
6378 */
6379 msleep(100);
6380 }
6381 if (!will_reset && !unloading) {
6382 /* The caller will have detached, relying on the MC reset to
6383 * trigger a re-attach. Since there won't be an MC reset, we
6384 * have to do the attach ourselves.
6385 */
6386 efx_device_attach_if_not_resetting(efx);
6387 }
6388
6389 return rc;
6390}
6391
6392static int efx_ef10_udp_tnl_push_ports(struct efx_nic *efx)
6393{
6394 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6395 int rc = 0;
6396
6397 mutex_lock(&nic_data->udp_tunnels_lock);
6398 if (nic_data->udp_tunnels_dirty) {
6399 /* Make sure all TX are stopped while we modify the table, else
6400 * we might race against an efx_features_check().
6401 */
6402 efx_device_detach_sync(efx);
6403 rc = efx_ef10_set_udp_tnl_ports(efx, false);
6404 }
6405 mutex_unlock(&nic_data->udp_tunnels_lock);
6406 return rc;
6407}
6408
6409static struct efx_udp_tunnel *__efx_ef10_udp_tnl_lookup_port(struct efx_nic *efx,
6410 __be16 port)
6411{
6412 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6413 size_t i;
6414
6415 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) {
6416 if (!nic_data->udp_tunnels[i].count)
6417 continue;
6418 if (nic_data->udp_tunnels[i].port == port)
6419 return &nic_data->udp_tunnels[i];
6420 }
6421 return NULL;
6422}
6423
6424static int efx_ef10_udp_tnl_add_port(struct efx_nic *efx,
6425 struct efx_udp_tunnel tnl)
6426{
6427 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6428 struct efx_udp_tunnel *match;
6429 char typebuf[8];
6430 size_t i;
6431 int rc;
6432
6433 if (!(nic_data->datapath_caps &
6434 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6435 return 0;
6436
6437 efx_get_udp_tunnel_type_name(tnl.type, typebuf, sizeof(typebuf));
6438 netif_dbg(efx, drv, efx->net_dev, "Adding UDP tunnel (%s) port %d\n",
6439 typebuf, ntohs(tnl.port));
6440
6441 mutex_lock(&nic_data->udp_tunnels_lock);
6442 /* Make sure all TX are stopped while we add to the table, else we
6443 * might race against an efx_features_check().
6444 */
6445 efx_device_detach_sync(efx);
6446
6447 match = __efx_ef10_udp_tnl_lookup_port(efx, tnl.port);
6448 if (match != NULL) {
6449 if (match->type == tnl.type) {
6450 netif_dbg(efx, drv, efx->net_dev,
6451 "Referencing existing tunnel entry\n");
6452 match->count++;
6453 /* No need to cause an MCDI update */
6454 rc = 0;
6455 goto unlock_out;
6456 }
6457 efx_get_udp_tunnel_type_name(match->type,
6458 typebuf, sizeof(typebuf));
6459 netif_dbg(efx, drv, efx->net_dev,
6460 "UDP port %d is already in use by %s\n",
6461 ntohs(tnl.port), typebuf);
6462 rc = -EEXIST;
6463 goto unlock_out;
6464 }
6465
6466 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i)
6467 if (!nic_data->udp_tunnels[i].count) {
6468 nic_data->udp_tunnels[i] = tnl;
6469 nic_data->udp_tunnels[i].count = 1;
6470 rc = efx_ef10_set_udp_tnl_ports(efx, false);
6471 goto unlock_out;
6472 }
6473
6474 netif_dbg(efx, drv, efx->net_dev,
6475 "Unable to add UDP tunnel (%s) port %d; insufficient resources.\n",
6476 typebuf, ntohs(tnl.port));
6477
6478 rc = -ENOMEM;
6479
6480unlock_out:
6481 mutex_unlock(&nic_data->udp_tunnels_lock);
6482 return rc;
6483}
6484
6485/* Called under the TX lock with the TX queue running, hence no-one can be
6486 * in the middle of updating the UDP tunnels table. However, they could
6487 * have tried and failed the MCDI, in which case they'll have set the dirty
6488 * flag before dropping their locks.
6489 */
6490static bool efx_ef10_udp_tnl_has_port(struct efx_nic *efx, __be16 port)
6491{
6492 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6493
6494 if (!(nic_data->datapath_caps &
6495 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6496 return false;
6497
6498 if (nic_data->udp_tunnels_dirty)
6499 /* SW table may not match HW state, so just assume we can't
6500 * use any UDP tunnel offloads.
6501 */
6502 return false;
6503
6504 return __efx_ef10_udp_tnl_lookup_port(efx, port) != NULL;
6505}
6506
6507static int efx_ef10_udp_tnl_del_port(struct efx_nic *efx,
6508 struct efx_udp_tunnel tnl)
6509{
6510 struct efx_ef10_nic_data *nic_data = efx->nic_data;
6511 struct efx_udp_tunnel *match;
6512 char typebuf[8];
6513 int rc;
6514
6515 if (!(nic_data->datapath_caps &
6516 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)))
6517 return 0;
6518
6519 efx_get_udp_tunnel_type_name(tnl.type, typebuf, sizeof(typebuf));
6520 netif_dbg(efx, drv, efx->net_dev, "Removing UDP tunnel (%s) port %d\n",
6521 typebuf, ntohs(tnl.port));
6522
6523 mutex_lock(&nic_data->udp_tunnels_lock);
6524 /* Make sure all TX are stopped while we remove from the table, else we
6525 * might race against an efx_features_check().
6526 */
6527 efx_device_detach_sync(efx);
6528
6529 match = __efx_ef10_udp_tnl_lookup_port(efx, tnl.port);
6530 if (match != NULL) {
6531 if (match->type == tnl.type) {
6532 if (--match->count) {
6533 /* Port is still in use, so nothing to do */
6534 netif_dbg(efx, drv, efx->net_dev,
6535 "UDP tunnel port %d remains active\n",
6536 ntohs(tnl.port));
6537 rc = 0;
6538 goto out_unlock;
6539 }
6540 rc = efx_ef10_set_udp_tnl_ports(efx, false);
6541 goto out_unlock;
6542 }
6543 efx_get_udp_tunnel_type_name(match->type,
6544 typebuf, sizeof(typebuf));
6545 netif_warn(efx, drv, efx->net_dev,
6546 "UDP port %d is actually in use by %s, not removing\n",
6547 ntohs(tnl.port), typebuf);
6548 }
6549 rc = -ENOENT;
6550
6551out_unlock:
6552 mutex_unlock(&nic_data->udp_tunnels_lock);
6553 return rc;
6554}
6555
6556#define EF10_OFFLOAD_FEATURES \
6557 (NETIF_F_IP_CSUM | \
6558 NETIF_F_HW_VLAN_CTAG_FILTER | \
6559 NETIF_F_IPV6_CSUM | \
6560 NETIF_F_RXHASH | \
6561 NETIF_F_NTUPLE)
6562
6563const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
6564 .is_vf = true,
6565 .mem_bar = efx_ef10_vf_mem_bar,
6566 .mem_map_size = efx_ef10_mem_map_size,
6567 .probe = efx_ef10_probe_vf,
6568 .remove = efx_ef10_remove,
6569 .dimension_resources = efx_ef10_dimension_resources,
6570 .init = efx_ef10_init_nic,
6571 .fini = efx_port_dummy_op_void,
6572 .map_reset_reason = efx_ef10_map_reset_reason,
6573 .map_reset_flags = efx_ef10_map_reset_flags,
6574 .reset = efx_ef10_reset,
6575 .probe_port = efx_mcdi_port_probe,
6576 .remove_port = efx_mcdi_port_remove,
6577 .fini_dmaq = efx_ef10_fini_dmaq,
6578 .prepare_flr = efx_ef10_prepare_flr,
6579 .finish_flr = efx_port_dummy_op_void,
6580 .describe_stats = efx_ef10_describe_stats,
6581 .update_stats = efx_ef10_update_stats_vf,
6582 .start_stats = efx_port_dummy_op_void,
6583 .pull_stats = efx_port_dummy_op_void,
6584 .stop_stats = efx_port_dummy_op_void,
6585 .set_id_led = efx_mcdi_set_id_led,
6586 .push_irq_moderation = efx_ef10_push_irq_moderation,
6587 .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
6588 .check_mac_fault = efx_mcdi_mac_check_fault,
6589 .reconfigure_port = efx_mcdi_port_reconfigure,
6590 .get_wol = efx_ef10_get_wol_vf,
6591 .set_wol = efx_ef10_set_wol_vf,
6592 .resume_wol = efx_port_dummy_op_void,
6593 .mcdi_request = efx_ef10_mcdi_request,
6594 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
6595 .mcdi_read_response = efx_ef10_mcdi_read_response,
6596 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
6597 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
6598 .irq_enable_master = efx_port_dummy_op_void,
6599 .irq_test_generate = efx_ef10_irq_test_generate,
6600 .irq_disable_non_ev = efx_port_dummy_op_void,
6601 .irq_handle_msi = efx_ef10_msi_interrupt,
6602 .irq_handle_legacy = efx_ef10_legacy_interrupt,
6603 .tx_probe = efx_ef10_tx_probe,
6604 .tx_init = efx_ef10_tx_init,
6605 .tx_remove = efx_ef10_tx_remove,
6606 .tx_write = efx_ef10_tx_write,
6607 .tx_limit_len = efx_ef10_tx_limit_len,
6608 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
6609 .rx_pull_rss_config = efx_ef10_rx_pull_rss_config,
6610 .rx_probe = efx_ef10_rx_probe,
6611 .rx_init = efx_ef10_rx_init,
6612 .rx_remove = efx_ef10_rx_remove,
6613 .rx_write = efx_ef10_rx_write,
6614 .rx_defer_refill = efx_ef10_rx_defer_refill,
6615 .ev_probe = efx_ef10_ev_probe,
6616 .ev_init = efx_ef10_ev_init,
6617 .ev_fini = efx_ef10_ev_fini,
6618 .ev_remove = efx_ef10_ev_remove,
6619 .ev_process = efx_ef10_ev_process,
6620 .ev_read_ack = efx_ef10_ev_read_ack,
6621 .ev_test_generate = efx_ef10_ev_test_generate,
6622 .filter_table_probe = efx_ef10_filter_table_probe,
6623 .filter_table_restore = efx_ef10_filter_table_restore,
6624 .filter_table_remove = efx_ef10_filter_table_remove,
6625 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
6626 .filter_insert = efx_ef10_filter_insert,
6627 .filter_remove_safe = efx_ef10_filter_remove_safe,
6628 .filter_get_safe = efx_ef10_filter_get_safe,
6629 .filter_clear_rx = efx_ef10_filter_clear_rx,
6630 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
6631 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
6632 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
6633#ifdef CONFIG_RFS_ACCEL
6634 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
6635#endif
6636#ifdef CONFIG_SFC_MTD
6637 .mtd_probe = efx_port_dummy_op_int,
6638#endif
6639 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
6640 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
6641 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
6642 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
6643#ifdef CONFIG_SFC_SRIOV
6644 .vswitching_probe = efx_ef10_vswitching_probe_vf,
6645 .vswitching_restore = efx_ef10_vswitching_restore_vf,
6646 .vswitching_remove = efx_ef10_vswitching_remove_vf,
6647#endif
6648 .get_mac_address = efx_ef10_get_mac_address_vf,
6649 .set_mac_address = efx_ef10_set_mac_address,
6650
6651 .get_phys_port_id = efx_ef10_get_phys_port_id,
6652 .revision = EFX_REV_HUNT_A0,
6653 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
6654 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
6655 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
6656 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
6657 .can_rx_scatter = true,
6658 .always_rx_scatter = true,
6659 .min_interrupt_mode = EFX_INT_MODE_MSIX,
6660 .max_interrupt_mode = EFX_INT_MODE_MSIX,
6661 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
6662 .offload_features = EF10_OFFLOAD_FEATURES,
6663 .mcdi_max_ver = 2,
6664 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
6665 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
6666 1 << HWTSTAMP_FILTER_ALL,
6667 .rx_hash_key_size = 40,
6668};
6669
6670const struct efx_nic_type efx_hunt_a0_nic_type = {
6671 .is_vf = false,
6672 .mem_bar = efx_ef10_pf_mem_bar,
6673 .mem_map_size = efx_ef10_mem_map_size,
6674 .probe = efx_ef10_probe_pf,
6675 .remove = efx_ef10_remove,
6676 .dimension_resources = efx_ef10_dimension_resources,
6677 .init = efx_ef10_init_nic,
6678 .fini = efx_port_dummy_op_void,
6679 .map_reset_reason = efx_ef10_map_reset_reason,
6680 .map_reset_flags = efx_ef10_map_reset_flags,
6681 .reset = efx_ef10_reset,
6682 .probe_port = efx_mcdi_port_probe,
6683 .remove_port = efx_mcdi_port_remove,
6684 .fini_dmaq = efx_ef10_fini_dmaq,
6685 .prepare_flr = efx_ef10_prepare_flr,
6686 .finish_flr = efx_port_dummy_op_void,
6687 .describe_stats = efx_ef10_describe_stats,
6688 .update_stats = efx_ef10_update_stats_pf,
6689 .start_stats = efx_mcdi_mac_start_stats,
6690 .pull_stats = efx_mcdi_mac_pull_stats,
6691 .stop_stats = efx_mcdi_mac_stop_stats,
6692 .set_id_led = efx_mcdi_set_id_led,
6693 .push_irq_moderation = efx_ef10_push_irq_moderation,
6694 .reconfigure_mac = efx_ef10_mac_reconfigure,
6695 .check_mac_fault = efx_mcdi_mac_check_fault,
6696 .reconfigure_port = efx_mcdi_port_reconfigure,
6697 .get_wol = efx_ef10_get_wol,
6698 .set_wol = efx_ef10_set_wol,
6699 .resume_wol = efx_port_dummy_op_void,
6700 .test_chip = efx_ef10_test_chip,
6701 .test_nvram = efx_mcdi_nvram_test_all,
6702 .mcdi_request = efx_ef10_mcdi_request,
6703 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
6704 .mcdi_read_response = efx_ef10_mcdi_read_response,
6705 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
6706 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
6707 .irq_enable_master = efx_port_dummy_op_void,
6708 .irq_test_generate = efx_ef10_irq_test_generate,
6709 .irq_disable_non_ev = efx_port_dummy_op_void,
6710 .irq_handle_msi = efx_ef10_msi_interrupt,
6711 .irq_handle_legacy = efx_ef10_legacy_interrupt,
6712 .tx_probe = efx_ef10_tx_probe,
6713 .tx_init = efx_ef10_tx_init,
6714 .tx_remove = efx_ef10_tx_remove,
6715 .tx_write = efx_ef10_tx_write,
6716 .tx_limit_len = efx_ef10_tx_limit_len,
6717 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
6718 .rx_pull_rss_config = efx_ef10_rx_pull_rss_config,
6719 .rx_push_rss_context_config = efx_ef10_rx_push_rss_context_config,
6720 .rx_pull_rss_context_config = efx_ef10_rx_pull_rss_context_config,
6721 .rx_restore_rss_contexts = efx_ef10_rx_restore_rss_contexts,
6722 .rx_probe = efx_ef10_rx_probe,
6723 .rx_init = efx_ef10_rx_init,
6724 .rx_remove = efx_ef10_rx_remove,
6725 .rx_write = efx_ef10_rx_write,
6726 .rx_defer_refill = efx_ef10_rx_defer_refill,
6727 .ev_probe = efx_ef10_ev_probe,
6728 .ev_init = efx_ef10_ev_init,
6729 .ev_fini = efx_ef10_ev_fini,
6730 .ev_remove = efx_ef10_ev_remove,
6731 .ev_process = efx_ef10_ev_process,
6732 .ev_read_ack = efx_ef10_ev_read_ack,
6733 .ev_test_generate = efx_ef10_ev_test_generate,
6734 .filter_table_probe = efx_ef10_filter_table_probe,
6735 .filter_table_restore = efx_ef10_filter_table_restore,
6736 .filter_table_remove = efx_ef10_filter_table_remove,
6737 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
6738 .filter_insert = efx_ef10_filter_insert,
6739 .filter_remove_safe = efx_ef10_filter_remove_safe,
6740 .filter_get_safe = efx_ef10_filter_get_safe,
6741 .filter_clear_rx = efx_ef10_filter_clear_rx,
6742 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
6743 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
6744 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
6745#ifdef CONFIG_RFS_ACCEL
6746 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
6747#endif
6748#ifdef CONFIG_SFC_MTD
6749 .mtd_probe = efx_ef10_mtd_probe,
6750 .mtd_rename = efx_mcdi_mtd_rename,
6751 .mtd_read = efx_mcdi_mtd_read,
6752 .mtd_erase = efx_mcdi_mtd_erase,
6753 .mtd_write = efx_mcdi_mtd_write,
6754 .mtd_sync = efx_mcdi_mtd_sync,
6755#endif
6756 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
6757 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
6758 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
6759 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
6760 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
6761 .udp_tnl_push_ports = efx_ef10_udp_tnl_push_ports,
6762 .udp_tnl_add_port = efx_ef10_udp_tnl_add_port,
6763 .udp_tnl_has_port = efx_ef10_udp_tnl_has_port,
6764 .udp_tnl_del_port = efx_ef10_udp_tnl_del_port,
6765#ifdef CONFIG_SFC_SRIOV
6766 .sriov_configure = efx_ef10_sriov_configure,
6767 .sriov_init = efx_ef10_sriov_init,
6768 .sriov_fini = efx_ef10_sriov_fini,
6769 .sriov_wanted = efx_ef10_sriov_wanted,
6770 .sriov_reset = efx_ef10_sriov_reset,
6771 .sriov_flr = efx_ef10_sriov_flr,
6772 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
6773 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
6774 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
6775 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
6776 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
6777 .vswitching_probe = efx_ef10_vswitching_probe_pf,
6778 .vswitching_restore = efx_ef10_vswitching_restore_pf,
6779 .vswitching_remove = efx_ef10_vswitching_remove_pf,
6780#endif
6781 .get_mac_address = efx_ef10_get_mac_address_pf,
6782 .set_mac_address = efx_ef10_set_mac_address,
6783 .tso_versions = efx_ef10_tso_versions,
6784
6785 .get_phys_port_id = efx_ef10_get_phys_port_id,
6786 .revision = EFX_REV_HUNT_A0,
6787 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
6788 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
6789 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
6790 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
6791 .can_rx_scatter = true,
6792 .always_rx_scatter = true,
6793 .option_descriptors = true,
6794 .min_interrupt_mode = EFX_INT_MODE_LEGACY,
6795 .max_interrupt_mode = EFX_INT_MODE_MSIX,
6796 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
6797 .offload_features = EF10_OFFLOAD_FEATURES,
6798 .mcdi_max_ver = 2,
6799 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
6800 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
6801 1 << HWTSTAMP_FILTER_ALL,
6802 .rx_hash_key_size = 40,
6803};
1/****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10#include "net_driver.h"
11#include "ef10_regs.h"
12#include "io.h"
13#include "mcdi.h"
14#include "mcdi_pcol.h"
15#include "nic.h"
16#include "workarounds.h"
17#include "selftest.h"
18#include <linux/in.h>
19#include <linux/jhash.h>
20#include <linux/wait.h>
21#include <linux/workqueue.h>
22
23/* Hardware control for EF10 architecture including 'Huntington'. */
24
25#define EFX_EF10_DRVGEN_EV 7
26enum {
27 EFX_EF10_TEST = 1,
28 EFX_EF10_REFILL,
29};
30
31/* The reserved RSS context value */
32#define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
33
34/* The filter table(s) are managed by firmware and we have write-only
35 * access. When removing filters we must identify them to the
36 * firmware by a 64-bit handle, but this is too wide for Linux kernel
37 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
38 * be able to tell in advance whether a requested insertion will
39 * replace an existing filter. Therefore we maintain a software hash
40 * table, which should be at least as large as the hardware hash
41 * table.
42 *
43 * Huntington has a single 8K filter table shared between all filter
44 * types and both ports.
45 */
46#define HUNT_FILTER_TBL_ROWS 8192
47
48struct efx_ef10_filter_table {
49/* The RX match field masks supported by this fw & hw, in order of priority */
50 enum efx_filter_match_flags rx_match_flags[
51 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
52 unsigned int rx_match_count;
53
54 struct {
55 unsigned long spec; /* pointer to spec plus flag bits */
56/* BUSY flag indicates that an update is in progress. AUTO_OLD is
57 * used to mark and sweep MAC filters for the device address lists.
58 */
59#define EFX_EF10_FILTER_FLAG_BUSY 1UL
60#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
61#define EFX_EF10_FILTER_FLAGS 3UL
62 u64 handle; /* firmware handle */
63 } *entry;
64 wait_queue_head_t waitq;
65/* Shadow of net_device address lists, guarded by mac_lock */
66#define EFX_EF10_FILTER_DEV_UC_MAX 32
67#define EFX_EF10_FILTER_DEV_MC_MAX 256
68 struct {
69 u8 addr[ETH_ALEN];
70 u16 id;
71 } dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX],
72 dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
73 int dev_uc_count; /* negative for PROMISC */
74 int dev_mc_count; /* negative for PROMISC/ALLMULTI */
75};
76
77/* An arbitrary search limit for the software hash table */
78#define EFX_EF10_FILTER_SEARCH_LIMIT 200
79
80static void efx_ef10_rx_push_rss_config(struct efx_nic *efx);
81static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
82static void efx_ef10_filter_table_remove(struct efx_nic *efx);
83
84static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
85{
86 efx_dword_t reg;
87
88 efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS);
89 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
90 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
91}
92
93static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
94{
95 return resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]);
96}
97
98static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
99{
100 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN);
101 struct efx_ef10_nic_data *nic_data = efx->nic_data;
102 size_t outlen;
103 int rc;
104
105 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
106
107 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
108 outbuf, sizeof(outbuf), &outlen);
109 if (rc)
110 return rc;
111 if (outlen < sizeof(outbuf)) {
112 netif_err(efx, drv, efx->net_dev,
113 "unable to read datapath firmware capabilities\n");
114 return -EIO;
115 }
116
117 nic_data->datapath_caps =
118 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
119
120 if (!(nic_data->datapath_caps &
121 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) {
122 netif_err(efx, drv, efx->net_dev,
123 "current firmware does not support TSO\n");
124 return -ENODEV;
125 }
126
127 if (!(nic_data->datapath_caps &
128 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
129 netif_err(efx, probe, efx->net_dev,
130 "current firmware does not support an RX prefix\n");
131 return -ENODEV;
132 }
133
134 return 0;
135}
136
137static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
138{
139 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
140 int rc;
141
142 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
143 outbuf, sizeof(outbuf), NULL);
144 if (rc)
145 return rc;
146 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
147 return rc > 0 ? rc : -ERANGE;
148}
149
150static int efx_ef10_get_mac_address(struct efx_nic *efx, u8 *mac_address)
151{
152 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
153 size_t outlen;
154 int rc;
155
156 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
157
158 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
159 outbuf, sizeof(outbuf), &outlen);
160 if (rc)
161 return rc;
162 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
163 return -EIO;
164
165 ether_addr_copy(mac_address,
166 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
167 return 0;
168}
169
170static int efx_ef10_probe(struct efx_nic *efx)
171{
172 struct efx_ef10_nic_data *nic_data;
173 int i, rc;
174
175 /* We can have one VI for each 8K region. However, until we
176 * use TX option descriptors we need two TX queues per channel.
177 */
178 efx->max_channels =
179 min_t(unsigned int,
180 EFX_MAX_CHANNELS,
181 resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]) /
182 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
183 BUG_ON(efx->max_channels == 0);
184
185 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
186 if (!nic_data)
187 return -ENOMEM;
188 efx->nic_data = nic_data;
189
190 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
191 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
192 if (rc)
193 goto fail1;
194
195 /* Get the MC's warm boot count. In case it's rebooting right
196 * now, be prepared to retry.
197 */
198 i = 0;
199 for (;;) {
200 rc = efx_ef10_get_warm_boot_count(efx);
201 if (rc >= 0)
202 break;
203 if (++i == 5)
204 goto fail2;
205 ssleep(1);
206 }
207 nic_data->warm_boot_count = rc;
208
209 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
210
211 /* In case we're recovering from a crash (kexec), we want to
212 * cancel any outstanding request by the previous user of this
213 * function. We send a special message using the least
214 * significant bits of the 'high' (doorbell) register.
215 */
216 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
217
218 rc = efx_mcdi_init(efx);
219 if (rc)
220 goto fail2;
221
222 /* Reset (most) configuration for this function */
223 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
224 if (rc)
225 goto fail3;
226
227 /* Enable event logging */
228 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
229 if (rc)
230 goto fail3;
231
232 rc = efx_ef10_init_datapath_caps(efx);
233 if (rc < 0)
234 goto fail3;
235
236 efx->rx_packet_len_offset =
237 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
238
239 rc = efx_mcdi_port_get_number(efx);
240 if (rc < 0)
241 goto fail3;
242 efx->port_num = rc;
243
244 rc = efx_ef10_get_mac_address(efx, efx->net_dev->perm_addr);
245 if (rc)
246 goto fail3;
247
248 rc = efx_ef10_get_sysclk_freq(efx);
249 if (rc < 0)
250 goto fail3;
251 efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */
252
253 /* Check whether firmware supports bug 35388 workaround */
254 rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true);
255 if (rc == 0)
256 nic_data->workaround_35388 = true;
257 else if (rc != -ENOSYS && rc != -ENOENT)
258 goto fail3;
259 netif_dbg(efx, probe, efx->net_dev,
260 "workaround for bug 35388 is %sabled\n",
261 nic_data->workaround_35388 ? "en" : "dis");
262
263 rc = efx_mcdi_mon_probe(efx);
264 if (rc)
265 goto fail3;
266
267 efx_ptp_probe(efx, NULL);
268
269 return 0;
270
271fail3:
272 efx_mcdi_fini(efx);
273fail2:
274 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
275fail1:
276 kfree(nic_data);
277 efx->nic_data = NULL;
278 return rc;
279}
280
281static int efx_ef10_free_vis(struct efx_nic *efx)
282{
283 MCDI_DECLARE_BUF_OUT_OR_ERR(outbuf, 0);
284 size_t outlen;
285 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
286 outbuf, sizeof(outbuf), &outlen);
287
288 /* -EALREADY means nothing to free, so ignore */
289 if (rc == -EALREADY)
290 rc = 0;
291 if (rc)
292 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
293 rc);
294 return rc;
295}
296
297#ifdef EFX_USE_PIO
298
299static void efx_ef10_free_piobufs(struct efx_nic *efx)
300{
301 struct efx_ef10_nic_data *nic_data = efx->nic_data;
302 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
303 unsigned int i;
304 int rc;
305
306 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
307
308 for (i = 0; i < nic_data->n_piobufs; i++) {
309 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
310 nic_data->piobuf_handle[i]);
311 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
312 NULL, 0, NULL);
313 WARN_ON(rc);
314 }
315
316 nic_data->n_piobufs = 0;
317}
318
319static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
320{
321 struct efx_ef10_nic_data *nic_data = efx->nic_data;
322 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
323 unsigned int i;
324 size_t outlen;
325 int rc = 0;
326
327 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
328
329 for (i = 0; i < n; i++) {
330 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
331 outbuf, sizeof(outbuf), &outlen);
332 if (rc)
333 break;
334 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
335 rc = -EIO;
336 break;
337 }
338 nic_data->piobuf_handle[i] =
339 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
340 netif_dbg(efx, probe, efx->net_dev,
341 "allocated PIO buffer %u handle %x\n", i,
342 nic_data->piobuf_handle[i]);
343 }
344
345 nic_data->n_piobufs = i;
346 if (rc)
347 efx_ef10_free_piobufs(efx);
348 return rc;
349}
350
351static int efx_ef10_link_piobufs(struct efx_nic *efx)
352{
353 struct efx_ef10_nic_data *nic_data = efx->nic_data;
354 MCDI_DECLARE_BUF(inbuf,
355 max(MC_CMD_LINK_PIOBUF_IN_LEN,
356 MC_CMD_UNLINK_PIOBUF_IN_LEN));
357 struct efx_channel *channel;
358 struct efx_tx_queue *tx_queue;
359 unsigned int offset, index;
360 int rc;
361
362 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
363 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
364
365 /* Link a buffer to each VI in the write-combining mapping */
366 for (index = 0; index < nic_data->n_piobufs; ++index) {
367 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
368 nic_data->piobuf_handle[index]);
369 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
370 nic_data->pio_write_vi_base + index);
371 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
372 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
373 NULL, 0, NULL);
374 if (rc) {
375 netif_err(efx, drv, efx->net_dev,
376 "failed to link VI %u to PIO buffer %u (%d)\n",
377 nic_data->pio_write_vi_base + index, index,
378 rc);
379 goto fail;
380 }
381 netif_dbg(efx, probe, efx->net_dev,
382 "linked VI %u to PIO buffer %u\n",
383 nic_data->pio_write_vi_base + index, index);
384 }
385
386 /* Link a buffer to each TX queue */
387 efx_for_each_channel(channel, efx) {
388 efx_for_each_channel_tx_queue(tx_queue, channel) {
389 /* We assign the PIO buffers to queues in
390 * reverse order to allow for the following
391 * special case.
392 */
393 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
394 tx_queue->channel->channel - 1) *
395 efx_piobuf_size);
396 index = offset / ER_DZ_TX_PIOBUF_SIZE;
397 offset = offset % ER_DZ_TX_PIOBUF_SIZE;
398
399 /* When the host page size is 4K, the first
400 * host page in the WC mapping may be within
401 * the same VI page as the last TX queue. We
402 * can only link one buffer to each VI.
403 */
404 if (tx_queue->queue == nic_data->pio_write_vi_base) {
405 BUG_ON(index != 0);
406 rc = 0;
407 } else {
408 MCDI_SET_DWORD(inbuf,
409 LINK_PIOBUF_IN_PIOBUF_HANDLE,
410 nic_data->piobuf_handle[index]);
411 MCDI_SET_DWORD(inbuf,
412 LINK_PIOBUF_IN_TXQ_INSTANCE,
413 tx_queue->queue);
414 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
415 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
416 NULL, 0, NULL);
417 }
418
419 if (rc) {
420 /* This is non-fatal; the TX path just
421 * won't use PIO for this queue
422 */
423 netif_err(efx, drv, efx->net_dev,
424 "failed to link VI %u to PIO buffer %u (%d)\n",
425 tx_queue->queue, index, rc);
426 tx_queue->piobuf = NULL;
427 } else {
428 tx_queue->piobuf =
429 nic_data->pio_write_base +
430 index * EFX_VI_PAGE_SIZE + offset;
431 tx_queue->piobuf_offset = offset;
432 netif_dbg(efx, probe, efx->net_dev,
433 "linked VI %u to PIO buffer %u offset %x addr %p\n",
434 tx_queue->queue, index,
435 tx_queue->piobuf_offset,
436 tx_queue->piobuf);
437 }
438 }
439 }
440
441 return 0;
442
443fail:
444 while (index--) {
445 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
446 nic_data->pio_write_vi_base + index);
447 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
448 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
449 NULL, 0, NULL);
450 }
451 return rc;
452}
453
454#else /* !EFX_USE_PIO */
455
456static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
457{
458 return n == 0 ? 0 : -ENOBUFS;
459}
460
461static int efx_ef10_link_piobufs(struct efx_nic *efx)
462{
463 return 0;
464}
465
466static void efx_ef10_free_piobufs(struct efx_nic *efx)
467{
468}
469
470#endif /* EFX_USE_PIO */
471
472static void efx_ef10_remove(struct efx_nic *efx)
473{
474 struct efx_ef10_nic_data *nic_data = efx->nic_data;
475 int rc;
476
477 efx_ptp_remove(efx);
478
479 efx_mcdi_mon_remove(efx);
480
481 efx_ef10_rx_free_indir_table(efx);
482
483 if (nic_data->wc_membase)
484 iounmap(nic_data->wc_membase);
485
486 rc = efx_ef10_free_vis(efx);
487 WARN_ON(rc != 0);
488
489 if (!nic_data->must_restore_piobufs)
490 efx_ef10_free_piobufs(efx);
491
492 efx_mcdi_fini(efx);
493 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
494 kfree(nic_data);
495}
496
497static int efx_ef10_alloc_vis(struct efx_nic *efx,
498 unsigned int min_vis, unsigned int max_vis)
499{
500 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
501 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
502 struct efx_ef10_nic_data *nic_data = efx->nic_data;
503 size_t outlen;
504 int rc;
505
506 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
507 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
508 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
509 outbuf, sizeof(outbuf), &outlen);
510 if (rc != 0)
511 return rc;
512
513 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
514 return -EIO;
515
516 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
517 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
518
519 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
520 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
521 return 0;
522}
523
524/* Note that the failure path of this function does not free
525 * resources, as this will be done by efx_ef10_remove().
526 */
527static int efx_ef10_dimension_resources(struct efx_nic *efx)
528{
529 struct efx_ef10_nic_data *nic_data = efx->nic_data;
530 unsigned int uc_mem_map_size, wc_mem_map_size;
531 unsigned int min_vis, pio_write_vi_base, max_vis;
532 void __iomem *membase;
533 int rc;
534
535 min_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
536
537#ifdef EFX_USE_PIO
538 /* Try to allocate PIO buffers if wanted and if the full
539 * number of PIO buffers would be sufficient to allocate one
540 * copy-buffer per TX channel. Failure is non-fatal, as there
541 * are only a small number of PIO buffers shared between all
542 * functions of the controller.
543 */
544 if (efx_piobuf_size != 0 &&
545 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
546 efx->n_tx_channels) {
547 unsigned int n_piobufs =
548 DIV_ROUND_UP(efx->n_tx_channels,
549 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
550
551 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
552 if (rc)
553 netif_err(efx, probe, efx->net_dev,
554 "failed to allocate PIO buffers (%d)\n", rc);
555 else
556 netif_dbg(efx, probe, efx->net_dev,
557 "allocated %u PIO buffers\n", n_piobufs);
558 }
559#else
560 nic_data->n_piobufs = 0;
561#endif
562
563 /* PIO buffers should be mapped with write-combining enabled,
564 * and we want to make single UC and WC mappings rather than
565 * several of each (in fact that's the only option if host
566 * page size is >4K). So we may allocate some extra VIs just
567 * for writing PIO buffers through.
568 *
569 * The UC mapping contains (min_vis - 1) complete VIs and the
570 * first half of the next VI. Then the WC mapping begins with
571 * the second half of this last VI.
572 */
573 uc_mem_map_size = PAGE_ALIGN((min_vis - 1) * EFX_VI_PAGE_SIZE +
574 ER_DZ_TX_PIOBUF);
575 if (nic_data->n_piobufs) {
576 /* pio_write_vi_base rounds down to give the number of complete
577 * VIs inside the UC mapping.
578 */
579 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
580 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
581 nic_data->n_piobufs) *
582 EFX_VI_PAGE_SIZE) -
583 uc_mem_map_size);
584 max_vis = pio_write_vi_base + nic_data->n_piobufs;
585 } else {
586 pio_write_vi_base = 0;
587 wc_mem_map_size = 0;
588 max_vis = min_vis;
589 }
590
591 /* In case the last attached driver failed to free VIs, do it now */
592 rc = efx_ef10_free_vis(efx);
593 if (rc != 0)
594 return rc;
595
596 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
597 if (rc != 0)
598 return rc;
599
600 /* If we didn't get enough VIs to map all the PIO buffers, free the
601 * PIO buffers
602 */
603 if (nic_data->n_piobufs &&
604 nic_data->n_allocated_vis <
605 pio_write_vi_base + nic_data->n_piobufs) {
606 netif_dbg(efx, probe, efx->net_dev,
607 "%u VIs are not sufficient to map %u PIO buffers\n",
608 nic_data->n_allocated_vis, nic_data->n_piobufs);
609 efx_ef10_free_piobufs(efx);
610 }
611
612 /* Shrink the original UC mapping of the memory BAR */
613 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
614 if (!membase) {
615 netif_err(efx, probe, efx->net_dev,
616 "could not shrink memory BAR to %x\n",
617 uc_mem_map_size);
618 return -ENOMEM;
619 }
620 iounmap(efx->membase);
621 efx->membase = membase;
622
623 /* Set up the WC mapping if needed */
624 if (wc_mem_map_size) {
625 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
626 uc_mem_map_size,
627 wc_mem_map_size);
628 if (!nic_data->wc_membase) {
629 netif_err(efx, probe, efx->net_dev,
630 "could not allocate WC mapping of size %x\n",
631 wc_mem_map_size);
632 return -ENOMEM;
633 }
634 nic_data->pio_write_vi_base = pio_write_vi_base;
635 nic_data->pio_write_base =
636 nic_data->wc_membase +
637 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
638 uc_mem_map_size);
639
640 rc = efx_ef10_link_piobufs(efx);
641 if (rc)
642 efx_ef10_free_piobufs(efx);
643 }
644
645 netif_dbg(efx, probe, efx->net_dev,
646 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
647 &efx->membase_phys, efx->membase, uc_mem_map_size,
648 nic_data->wc_membase, wc_mem_map_size);
649
650 return 0;
651}
652
653static int efx_ef10_init_nic(struct efx_nic *efx)
654{
655 struct efx_ef10_nic_data *nic_data = efx->nic_data;
656 int rc;
657
658 if (nic_data->must_check_datapath_caps) {
659 rc = efx_ef10_init_datapath_caps(efx);
660 if (rc)
661 return rc;
662 nic_data->must_check_datapath_caps = false;
663 }
664
665 if (nic_data->must_realloc_vis) {
666 /* We cannot let the number of VIs change now */
667 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
668 nic_data->n_allocated_vis);
669 if (rc)
670 return rc;
671 nic_data->must_realloc_vis = false;
672 }
673
674 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
675 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
676 if (rc == 0) {
677 rc = efx_ef10_link_piobufs(efx);
678 if (rc)
679 efx_ef10_free_piobufs(efx);
680 }
681
682 /* Log an error on failure, but this is non-fatal */
683 if (rc)
684 netif_err(efx, drv, efx->net_dev,
685 "failed to restore PIO buffers (%d)\n", rc);
686 nic_data->must_restore_piobufs = false;
687 }
688
689 efx_ef10_rx_push_rss_config(efx);
690 return 0;
691}
692
693static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
694{
695 struct efx_ef10_nic_data *nic_data = efx->nic_data;
696
697 /* All our allocations have been reset */
698 nic_data->must_realloc_vis = true;
699 nic_data->must_restore_filters = true;
700 nic_data->must_restore_piobufs = true;
701 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
702}
703
704static int efx_ef10_map_reset_flags(u32 *flags)
705{
706 enum {
707 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
708 ETH_RESET_SHARED_SHIFT),
709 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
710 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
711 ETH_RESET_PHY | ETH_RESET_MGMT) <<
712 ETH_RESET_SHARED_SHIFT)
713 };
714
715 /* We assume for now that our PCI function is permitted to
716 * reset everything.
717 */
718
719 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
720 *flags &= ~EF10_RESET_MC;
721 return RESET_TYPE_WORLD;
722 }
723
724 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
725 *flags &= ~EF10_RESET_PORT;
726 return RESET_TYPE_ALL;
727 }
728
729 /* no invisible reset implemented */
730
731 return -EINVAL;
732}
733
734static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
735{
736 int rc = efx_mcdi_reset(efx, reset_type);
737
738 /* If it was a port reset, trigger reallocation of MC resources.
739 * Note that on an MC reset nothing needs to be done now because we'll
740 * detect the MC reset later and handle it then.
741 * For an FLR, we never get an MC reset event, but the MC has reset all
742 * resources assigned to us, so we have to trigger reallocation now.
743 */
744 if ((reset_type == RESET_TYPE_ALL ||
745 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
746 efx_ef10_reset_mc_allocations(efx);
747 return rc;
748}
749
750#define EF10_DMA_STAT(ext_name, mcdi_name) \
751 [EF10_STAT_ ## ext_name] = \
752 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
753#define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
754 [EF10_STAT_ ## int_name] = \
755 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
756#define EF10_OTHER_STAT(ext_name) \
757 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
758
759static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
760 EF10_DMA_STAT(tx_bytes, TX_BYTES),
761 EF10_DMA_STAT(tx_packets, TX_PKTS),
762 EF10_DMA_STAT(tx_pause, TX_PAUSE_PKTS),
763 EF10_DMA_STAT(tx_control, TX_CONTROL_PKTS),
764 EF10_DMA_STAT(tx_unicast, TX_UNICAST_PKTS),
765 EF10_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS),
766 EF10_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS),
767 EF10_DMA_STAT(tx_lt64, TX_LT64_PKTS),
768 EF10_DMA_STAT(tx_64, TX_64_PKTS),
769 EF10_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS),
770 EF10_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS),
771 EF10_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS),
772 EF10_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS),
773 EF10_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
774 EF10_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
775 EF10_DMA_STAT(rx_bytes, RX_BYTES),
776 EF10_DMA_INVIS_STAT(rx_bytes_minus_good_bytes, RX_BAD_BYTES),
777 EF10_OTHER_STAT(rx_good_bytes),
778 EF10_OTHER_STAT(rx_bad_bytes),
779 EF10_DMA_STAT(rx_packets, RX_PKTS),
780 EF10_DMA_STAT(rx_good, RX_GOOD_PKTS),
781 EF10_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS),
782 EF10_DMA_STAT(rx_pause, RX_PAUSE_PKTS),
783 EF10_DMA_STAT(rx_control, RX_CONTROL_PKTS),
784 EF10_DMA_STAT(rx_unicast, RX_UNICAST_PKTS),
785 EF10_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS),
786 EF10_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS),
787 EF10_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS),
788 EF10_DMA_STAT(rx_64, RX_64_PKTS),
789 EF10_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS),
790 EF10_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS),
791 EF10_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS),
792 EF10_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS),
793 EF10_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
794 EF10_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
795 EF10_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS),
796 EF10_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS),
797 EF10_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS),
798 EF10_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS),
799 EF10_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS),
800 EF10_DMA_STAT(rx_nodesc_drops, RX_NODESC_DROPS),
801 EF10_DMA_STAT(rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
802 EF10_DMA_STAT(rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
803 EF10_DMA_STAT(rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
804 EF10_DMA_STAT(rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
805 EF10_DMA_STAT(rx_pm_trunc_qbb, PM_TRUNC_QBB),
806 EF10_DMA_STAT(rx_pm_discard_qbb, PM_DISCARD_QBB),
807 EF10_DMA_STAT(rx_pm_discard_mapping, PM_DISCARD_MAPPING),
808 EF10_DMA_STAT(rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
809 EF10_DMA_STAT(rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
810 EF10_DMA_STAT(rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
811 EF10_DMA_STAT(rx_dp_hlb_fetch, RXDP_EMERGENCY_FETCH_CONDITIONS),
812 EF10_DMA_STAT(rx_dp_hlb_wait, RXDP_EMERGENCY_WAIT_CONDITIONS),
813};
814
815#define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_tx_bytes) | \
816 (1ULL << EF10_STAT_tx_packets) | \
817 (1ULL << EF10_STAT_tx_pause) | \
818 (1ULL << EF10_STAT_tx_unicast) | \
819 (1ULL << EF10_STAT_tx_multicast) | \
820 (1ULL << EF10_STAT_tx_broadcast) | \
821 (1ULL << EF10_STAT_rx_bytes) | \
822 (1ULL << EF10_STAT_rx_bytes_minus_good_bytes) | \
823 (1ULL << EF10_STAT_rx_good_bytes) | \
824 (1ULL << EF10_STAT_rx_bad_bytes) | \
825 (1ULL << EF10_STAT_rx_packets) | \
826 (1ULL << EF10_STAT_rx_good) | \
827 (1ULL << EF10_STAT_rx_bad) | \
828 (1ULL << EF10_STAT_rx_pause) | \
829 (1ULL << EF10_STAT_rx_control) | \
830 (1ULL << EF10_STAT_rx_unicast) | \
831 (1ULL << EF10_STAT_rx_multicast) | \
832 (1ULL << EF10_STAT_rx_broadcast) | \
833 (1ULL << EF10_STAT_rx_lt64) | \
834 (1ULL << EF10_STAT_rx_64) | \
835 (1ULL << EF10_STAT_rx_65_to_127) | \
836 (1ULL << EF10_STAT_rx_128_to_255) | \
837 (1ULL << EF10_STAT_rx_256_to_511) | \
838 (1ULL << EF10_STAT_rx_512_to_1023) | \
839 (1ULL << EF10_STAT_rx_1024_to_15xx) | \
840 (1ULL << EF10_STAT_rx_15xx_to_jumbo) | \
841 (1ULL << EF10_STAT_rx_gtjumbo) | \
842 (1ULL << EF10_STAT_rx_bad_gtjumbo) | \
843 (1ULL << EF10_STAT_rx_overflow) | \
844 (1ULL << EF10_STAT_rx_nodesc_drops))
845
846/* These statistics are only provided by the 10G MAC. For a 10G/40G
847 * switchable port we do not expose these because they might not
848 * include all the packets they should.
849 */
850#define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_tx_control) | \
851 (1ULL << EF10_STAT_tx_lt64) | \
852 (1ULL << EF10_STAT_tx_64) | \
853 (1ULL << EF10_STAT_tx_65_to_127) | \
854 (1ULL << EF10_STAT_tx_128_to_255) | \
855 (1ULL << EF10_STAT_tx_256_to_511) | \
856 (1ULL << EF10_STAT_tx_512_to_1023) | \
857 (1ULL << EF10_STAT_tx_1024_to_15xx) | \
858 (1ULL << EF10_STAT_tx_15xx_to_jumbo))
859
860/* These statistics are only provided by the 40G MAC. For a 10G/40G
861 * switchable port we do expose these because the errors will otherwise
862 * be silent.
863 */
864#define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_rx_align_error) | \
865 (1ULL << EF10_STAT_rx_length_error))
866
867/* These statistics are only provided if the firmware supports the
868 * capability PM_AND_RXDP_COUNTERS.
869 */
870#define HUNT_PM_AND_RXDP_STAT_MASK ( \
871 (1ULL << EF10_STAT_rx_pm_trunc_bb_overflow) | \
872 (1ULL << EF10_STAT_rx_pm_discard_bb_overflow) | \
873 (1ULL << EF10_STAT_rx_pm_trunc_vfifo_full) | \
874 (1ULL << EF10_STAT_rx_pm_discard_vfifo_full) | \
875 (1ULL << EF10_STAT_rx_pm_trunc_qbb) | \
876 (1ULL << EF10_STAT_rx_pm_discard_qbb) | \
877 (1ULL << EF10_STAT_rx_pm_discard_mapping) | \
878 (1ULL << EF10_STAT_rx_dp_q_disabled_packets) | \
879 (1ULL << EF10_STAT_rx_dp_di_dropped_packets) | \
880 (1ULL << EF10_STAT_rx_dp_streaming_packets) | \
881 (1ULL << EF10_STAT_rx_dp_hlb_fetch) | \
882 (1ULL << EF10_STAT_rx_dp_hlb_wait))
883
884static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
885{
886 u64 raw_mask = HUNT_COMMON_STAT_MASK;
887 u32 port_caps = efx_mcdi_phy_get_caps(efx);
888 struct efx_ef10_nic_data *nic_data = efx->nic_data;
889
890 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
891 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
892 else
893 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
894
895 if (nic_data->datapath_caps &
896 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
897 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
898
899 return raw_mask;
900}
901
902static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
903{
904 u64 raw_mask = efx_ef10_raw_stat_mask(efx);
905
906#if BITS_PER_LONG == 64
907 mask[0] = raw_mask;
908#else
909 mask[0] = raw_mask & 0xffffffff;
910 mask[1] = raw_mask >> 32;
911#endif
912}
913
914static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
915{
916 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
917
918 efx_ef10_get_stat_mask(efx, mask);
919 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
920 mask, names);
921}
922
923static int efx_ef10_try_update_nic_stats(struct efx_nic *efx)
924{
925 struct efx_ef10_nic_data *nic_data = efx->nic_data;
926 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
927 __le64 generation_start, generation_end;
928 u64 *stats = nic_data->stats;
929 __le64 *dma_stats;
930
931 efx_ef10_get_stat_mask(efx, mask);
932
933 dma_stats = efx->stats_buffer.addr;
934 nic_data = efx->nic_data;
935
936 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
937 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
938 return 0;
939 rmb();
940 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
941 stats, efx->stats_buffer.addr, false);
942 rmb();
943 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
944 if (generation_end != generation_start)
945 return -EAGAIN;
946
947 /* Update derived statistics */
948 efx_nic_fix_nodesc_drop_stat(efx, &stats[EF10_STAT_rx_nodesc_drops]);
949 stats[EF10_STAT_rx_good_bytes] =
950 stats[EF10_STAT_rx_bytes] -
951 stats[EF10_STAT_rx_bytes_minus_good_bytes];
952 efx_update_diff_stat(&stats[EF10_STAT_rx_bad_bytes],
953 stats[EF10_STAT_rx_bytes_minus_good_bytes]);
954
955 return 0;
956}
957
958
959static size_t efx_ef10_update_stats(struct efx_nic *efx, u64 *full_stats,
960 struct rtnl_link_stats64 *core_stats)
961{
962 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
963 struct efx_ef10_nic_data *nic_data = efx->nic_data;
964 u64 *stats = nic_data->stats;
965 size_t stats_count = 0, index;
966 int retry;
967
968 efx_ef10_get_stat_mask(efx, mask);
969
970 /* If we're unlucky enough to read statistics during the DMA, wait
971 * up to 10ms for it to finish (typically takes <500us)
972 */
973 for (retry = 0; retry < 100; ++retry) {
974 if (efx_ef10_try_update_nic_stats(efx) == 0)
975 break;
976 udelay(100);
977 }
978
979 if (full_stats) {
980 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
981 if (efx_ef10_stat_desc[index].name) {
982 *full_stats++ = stats[index];
983 ++stats_count;
984 }
985 }
986 }
987
988 if (core_stats) {
989 core_stats->rx_packets = stats[EF10_STAT_rx_packets];
990 core_stats->tx_packets = stats[EF10_STAT_tx_packets];
991 core_stats->rx_bytes = stats[EF10_STAT_rx_bytes];
992 core_stats->tx_bytes = stats[EF10_STAT_tx_bytes];
993 core_stats->rx_dropped = stats[EF10_STAT_rx_nodesc_drops];
994 core_stats->multicast = stats[EF10_STAT_rx_multicast];
995 core_stats->rx_length_errors =
996 stats[EF10_STAT_rx_gtjumbo] +
997 stats[EF10_STAT_rx_length_error];
998 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
999 core_stats->rx_frame_errors = stats[EF10_STAT_rx_align_error];
1000 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1001 core_stats->rx_errors = (core_stats->rx_length_errors +
1002 core_stats->rx_crc_errors +
1003 core_stats->rx_frame_errors);
1004 }
1005
1006 return stats_count;
1007}
1008
1009static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1010{
1011 struct efx_nic *efx = channel->efx;
1012 unsigned int mode, value;
1013 efx_dword_t timer_cmd;
1014
1015 if (channel->irq_moderation) {
1016 mode = 3;
1017 value = channel->irq_moderation - 1;
1018 } else {
1019 mode = 0;
1020 value = 0;
1021 }
1022
1023 if (EFX_EF10_WORKAROUND_35388(efx)) {
1024 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1025 EFE_DD_EVQ_IND_TIMER_FLAGS,
1026 ERF_DD_EVQ_IND_TIMER_MODE, mode,
1027 ERF_DD_EVQ_IND_TIMER_VAL, value);
1028 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1029 channel->channel);
1030 } else {
1031 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1032 ERF_DZ_TC_TIMER_VAL, value);
1033 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1034 channel->channel);
1035 }
1036}
1037
1038static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1039{
1040 wol->supported = 0;
1041 wol->wolopts = 0;
1042 memset(&wol->sopass, 0, sizeof(wol->sopass));
1043}
1044
1045static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1046{
1047 if (type != 0)
1048 return -EINVAL;
1049 return 0;
1050}
1051
1052static void efx_ef10_mcdi_request(struct efx_nic *efx,
1053 const efx_dword_t *hdr, size_t hdr_len,
1054 const efx_dword_t *sdu, size_t sdu_len)
1055{
1056 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1057 u8 *pdu = nic_data->mcdi_buf.addr;
1058
1059 memcpy(pdu, hdr, hdr_len);
1060 memcpy(pdu + hdr_len, sdu, sdu_len);
1061 wmb();
1062
1063 /* The hardware provides 'low' and 'high' (doorbell) registers
1064 * for passing the 64-bit address of an MCDI request to
1065 * firmware. However the dwords are swapped by firmware. The
1066 * least significant bits of the doorbell are then 0 for all
1067 * MCDI requests due to alignment.
1068 */
1069 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1070 ER_DZ_MC_DB_LWRD);
1071 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1072 ER_DZ_MC_DB_HWRD);
1073}
1074
1075static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1076{
1077 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1078 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1079
1080 rmb();
1081 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1082}
1083
1084static void
1085efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1086 size_t offset, size_t outlen)
1087{
1088 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1089 const u8 *pdu = nic_data->mcdi_buf.addr;
1090
1091 memcpy(outbuf, pdu + offset, outlen);
1092}
1093
1094static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1095{
1096 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1097 int rc;
1098
1099 rc = efx_ef10_get_warm_boot_count(efx);
1100 if (rc < 0) {
1101 /* The firmware is presumably in the process of
1102 * rebooting. However, we are supposed to report each
1103 * reboot just once, so we must only do that once we
1104 * can read and store the updated warm boot count.
1105 */
1106 return 0;
1107 }
1108
1109 if (rc == nic_data->warm_boot_count)
1110 return 0;
1111
1112 nic_data->warm_boot_count = rc;
1113
1114 /* All our allocations have been reset */
1115 efx_ef10_reset_mc_allocations(efx);
1116
1117 /* The datapath firmware might have been changed */
1118 nic_data->must_check_datapath_caps = true;
1119
1120 /* MAC statistics have been cleared on the NIC; clear the local
1121 * statistic that we update with efx_update_diff_stat().
1122 */
1123 nic_data->stats[EF10_STAT_rx_bad_bytes] = 0;
1124
1125 return -EIO;
1126}
1127
1128/* Handle an MSI interrupt
1129 *
1130 * Handle an MSI hardware interrupt. This routine schedules event
1131 * queue processing. No interrupt acknowledgement cycle is necessary.
1132 * Also, we never need to check that the interrupt is for us, since
1133 * MSI interrupts cannot be shared.
1134 */
1135static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
1136{
1137 struct efx_msi_context *context = dev_id;
1138 struct efx_nic *efx = context->efx;
1139
1140 netif_vdbg(efx, intr, efx->net_dev,
1141 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
1142
1143 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
1144 /* Note test interrupts */
1145 if (context->index == efx->irq_level)
1146 efx->last_irq_cpu = raw_smp_processor_id();
1147
1148 /* Schedule processing of the channel */
1149 efx_schedule_channel_irq(efx->channel[context->index]);
1150 }
1151
1152 return IRQ_HANDLED;
1153}
1154
1155static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
1156{
1157 struct efx_nic *efx = dev_id;
1158 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
1159 struct efx_channel *channel;
1160 efx_dword_t reg;
1161 u32 queues;
1162
1163 /* Read the ISR which also ACKs the interrupts */
1164 efx_readd(efx, ®, ER_DZ_BIU_INT_ISR);
1165 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
1166
1167 if (queues == 0)
1168 return IRQ_NONE;
1169
1170 if (likely(soft_enabled)) {
1171 /* Note test interrupts */
1172 if (queues & (1U << efx->irq_level))
1173 efx->last_irq_cpu = raw_smp_processor_id();
1174
1175 efx_for_each_channel(channel, efx) {
1176 if (queues & 1)
1177 efx_schedule_channel_irq(channel);
1178 queues >>= 1;
1179 }
1180 }
1181
1182 netif_vdbg(efx, intr, efx->net_dev,
1183 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1184 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1185
1186 return IRQ_HANDLED;
1187}
1188
1189static void efx_ef10_irq_test_generate(struct efx_nic *efx)
1190{
1191 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
1192
1193 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
1194
1195 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
1196 (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
1197 inbuf, sizeof(inbuf), NULL, 0, NULL);
1198}
1199
1200static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
1201{
1202 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
1203 (tx_queue->ptr_mask + 1) *
1204 sizeof(efx_qword_t),
1205 GFP_KERNEL);
1206}
1207
1208/* This writes to the TX_DESC_WPTR and also pushes data */
1209static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
1210 const efx_qword_t *txd)
1211{
1212 unsigned int write_ptr;
1213 efx_oword_t reg;
1214
1215 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1216 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
1217 reg.qword[0] = *txd;
1218 efx_writeo_page(tx_queue->efx, ®,
1219 ER_DZ_TX_DESC_UPD, tx_queue->queue);
1220}
1221
1222static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
1223{
1224 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1225 EFX_BUF_SIZE));
1226 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_TXQ_OUT_LEN);
1227 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
1228 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
1229 struct efx_channel *channel = tx_queue->channel;
1230 struct efx_nic *efx = tx_queue->efx;
1231 size_t inlen, outlen;
1232 dma_addr_t dma_addr;
1233 efx_qword_t *txd;
1234 int rc;
1235 int i;
1236
1237 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
1238 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
1239 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
1240 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
1241 MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
1242 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
1243 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
1244 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
1245 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1246
1247 dma_addr = tx_queue->txd.buf.dma_addr;
1248
1249 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
1250 tx_queue->queue, entries, (u64)dma_addr);
1251
1252 for (i = 0; i < entries; ++i) {
1253 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
1254 dma_addr += EFX_BUF_SIZE;
1255 }
1256
1257 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
1258
1259 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
1260 outbuf, sizeof(outbuf), &outlen);
1261 if (rc)
1262 goto fail;
1263
1264 /* A previous user of this TX queue might have set us up the
1265 * bomb by writing a descriptor to the TX push collector but
1266 * not the doorbell. (Each collector belongs to a port, not a
1267 * queue or function, so cannot easily be reset.) We must
1268 * attempt to push a no-op descriptor in its place.
1269 */
1270 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
1271 tx_queue->insert_count = 1;
1272 txd = efx_tx_desc(tx_queue, 0);
1273 EFX_POPULATE_QWORD_4(*txd,
1274 ESF_DZ_TX_DESC_IS_OPT, true,
1275 ESF_DZ_TX_OPTION_TYPE,
1276 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
1277 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
1278 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
1279 tx_queue->write_count = 1;
1280 wmb();
1281 efx_ef10_push_tx_desc(tx_queue, txd);
1282
1283 return;
1284
1285fail:
1286 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
1287 tx_queue->queue);
1288}
1289
1290static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
1291{
1292 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
1293 MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_TXQ_OUT_LEN);
1294 struct efx_nic *efx = tx_queue->efx;
1295 size_t outlen;
1296 int rc;
1297
1298 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
1299 tx_queue->queue);
1300
1301 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
1302 outbuf, sizeof(outbuf), &outlen);
1303
1304 if (rc && rc != -EALREADY)
1305 goto fail;
1306
1307 return;
1308
1309fail:
1310 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
1311 outbuf, outlen, rc);
1312}
1313
1314static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
1315{
1316 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
1317}
1318
1319/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
1320static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
1321{
1322 unsigned int write_ptr;
1323 efx_dword_t reg;
1324
1325 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1326 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
1327 efx_writed_page(tx_queue->efx, ®,
1328 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
1329}
1330
1331static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
1332{
1333 unsigned int old_write_count = tx_queue->write_count;
1334 struct efx_tx_buffer *buffer;
1335 unsigned int write_ptr;
1336 efx_qword_t *txd;
1337
1338 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
1339
1340 do {
1341 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1342 buffer = &tx_queue->buffer[write_ptr];
1343 txd = efx_tx_desc(tx_queue, write_ptr);
1344 ++tx_queue->write_count;
1345
1346 /* Create TX descriptor ring entry */
1347 if (buffer->flags & EFX_TX_BUF_OPTION) {
1348 *txd = buffer->option;
1349 } else {
1350 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
1351 EFX_POPULATE_QWORD_3(
1352 *txd,
1353 ESF_DZ_TX_KER_CONT,
1354 buffer->flags & EFX_TX_BUF_CONT,
1355 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
1356 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
1357 }
1358 } while (tx_queue->write_count != tx_queue->insert_count);
1359
1360 wmb(); /* Ensure descriptors are written before they are fetched */
1361
1362 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
1363 txd = efx_tx_desc(tx_queue,
1364 old_write_count & tx_queue->ptr_mask);
1365 efx_ef10_push_tx_desc(tx_queue, txd);
1366 ++tx_queue->pushes;
1367 } else {
1368 efx_ef10_notify_tx_desc(tx_queue);
1369 }
1370}
1371
1372static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context)
1373{
1374 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
1375 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
1376 size_t outlen;
1377 int rc;
1378
1379 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
1380 EVB_PORT_ID_ASSIGNED);
1381 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE,
1382 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE);
1383 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES,
1384 EFX_MAX_CHANNELS);
1385
1386 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
1387 outbuf, sizeof(outbuf), &outlen);
1388 if (rc != 0)
1389 return rc;
1390
1391 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
1392 return -EIO;
1393
1394 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
1395
1396 return 0;
1397}
1398
1399static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
1400{
1401 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
1402 int rc;
1403
1404 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
1405 context);
1406
1407 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
1408 NULL, 0, NULL);
1409 WARN_ON(rc != 0);
1410}
1411
1412static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context)
1413{
1414 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
1415 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
1416 int i, rc;
1417
1418 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
1419 context);
1420 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1421 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
1422
1423 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
1424 MCDI_PTR(tablebuf,
1425 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
1426 (u8) efx->rx_indir_table[i];
1427
1428 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
1429 sizeof(tablebuf), NULL, 0, NULL);
1430 if (rc != 0)
1431 return rc;
1432
1433 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
1434 context);
1435 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
1436 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
1437 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
1438 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
1439 efx->rx_hash_key[i];
1440
1441 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
1442 sizeof(keybuf), NULL, 0, NULL);
1443}
1444
1445static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
1446{
1447 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1448
1449 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
1450 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
1451 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1452}
1453
1454static void efx_ef10_rx_push_rss_config(struct efx_nic *efx)
1455{
1456 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1457 int rc;
1458
1459 netif_dbg(efx, drv, efx->net_dev, "pushing RSS config\n");
1460
1461 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID) {
1462 rc = efx_ef10_alloc_rss_context(efx, &nic_data->rx_rss_context);
1463 if (rc != 0)
1464 goto fail;
1465 }
1466
1467 rc = efx_ef10_populate_rss_table(efx, nic_data->rx_rss_context);
1468 if (rc != 0)
1469 goto fail;
1470
1471 return;
1472
1473fail:
1474 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
1475}
1476
1477static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
1478{
1479 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
1480 (rx_queue->ptr_mask + 1) *
1481 sizeof(efx_qword_t),
1482 GFP_KERNEL);
1483}
1484
1485static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
1486{
1487 MCDI_DECLARE_BUF(inbuf,
1488 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1489 EFX_BUF_SIZE));
1490 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_RXQ_OUT_LEN);
1491 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
1492 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
1493 struct efx_nic *efx = rx_queue->efx;
1494 size_t inlen, outlen;
1495 dma_addr_t dma_addr;
1496 int rc;
1497 int i;
1498
1499 rx_queue->scatter_n = 0;
1500 rx_queue->scatter_len = 0;
1501
1502 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
1503 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
1504 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
1505 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
1506 efx_rx_queue_index(rx_queue));
1507 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
1508 INIT_RXQ_IN_FLAG_PREFIX, 1,
1509 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
1510 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
1511 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1512
1513 dma_addr = rx_queue->rxd.buf.dma_addr;
1514
1515 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
1516 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
1517
1518 for (i = 0; i < entries; ++i) {
1519 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
1520 dma_addr += EFX_BUF_SIZE;
1521 }
1522
1523 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
1524
1525 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
1526 outbuf, sizeof(outbuf), &outlen);
1527 if (rc)
1528 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
1529 efx_rx_queue_index(rx_queue));
1530}
1531
1532static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
1533{
1534 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
1535 MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_RXQ_OUT_LEN);
1536 struct efx_nic *efx = rx_queue->efx;
1537 size_t outlen;
1538 int rc;
1539
1540 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
1541 efx_rx_queue_index(rx_queue));
1542
1543 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
1544 outbuf, sizeof(outbuf), &outlen);
1545
1546 if (rc && rc != -EALREADY)
1547 goto fail;
1548
1549 return;
1550
1551fail:
1552 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
1553 outbuf, outlen, rc);
1554}
1555
1556static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
1557{
1558 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
1559}
1560
1561/* This creates an entry in the RX descriptor queue */
1562static inline void
1563efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
1564{
1565 struct efx_rx_buffer *rx_buf;
1566 efx_qword_t *rxd;
1567
1568 rxd = efx_rx_desc(rx_queue, index);
1569 rx_buf = efx_rx_buffer(rx_queue, index);
1570 EFX_POPULATE_QWORD_2(*rxd,
1571 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
1572 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
1573}
1574
1575static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
1576{
1577 struct efx_nic *efx = rx_queue->efx;
1578 unsigned int write_count;
1579 efx_dword_t reg;
1580
1581 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
1582 write_count = rx_queue->added_count & ~7;
1583 if (rx_queue->notified_count == write_count)
1584 return;
1585
1586 do
1587 efx_ef10_build_rx_desc(
1588 rx_queue,
1589 rx_queue->notified_count & rx_queue->ptr_mask);
1590 while (++rx_queue->notified_count != write_count);
1591
1592 wmb();
1593 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
1594 write_count & rx_queue->ptr_mask);
1595 efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD,
1596 efx_rx_queue_index(rx_queue));
1597}
1598
1599static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
1600
1601static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
1602{
1603 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
1604 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
1605 efx_qword_t event;
1606
1607 EFX_POPULATE_QWORD_2(event,
1608 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
1609 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
1610
1611 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
1612
1613 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
1614 * already swapped the data to little-endian order.
1615 */
1616 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
1617 sizeof(efx_qword_t));
1618
1619 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
1620 inbuf, sizeof(inbuf), 0,
1621 efx_ef10_rx_defer_refill_complete, 0);
1622}
1623
1624static void
1625efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
1626 int rc, efx_dword_t *outbuf,
1627 size_t outlen_actual)
1628{
1629 /* nothing to do */
1630}
1631
1632static int efx_ef10_ev_probe(struct efx_channel *channel)
1633{
1634 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
1635 (channel->eventq_mask + 1) *
1636 sizeof(efx_qword_t),
1637 GFP_KERNEL);
1638}
1639
1640static int efx_ef10_ev_init(struct efx_channel *channel)
1641{
1642 MCDI_DECLARE_BUF(inbuf,
1643 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
1644 EFX_BUF_SIZE));
1645 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN);
1646 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
1647 struct efx_nic *efx = channel->efx;
1648 struct efx_ef10_nic_data *nic_data;
1649 bool supports_rx_merge;
1650 size_t inlen, outlen;
1651 dma_addr_t dma_addr;
1652 int rc;
1653 int i;
1654
1655 nic_data = efx->nic_data;
1656 supports_rx_merge =
1657 !!(nic_data->datapath_caps &
1658 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
1659
1660 /* Fill event queue with all ones (i.e. empty events) */
1661 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
1662
1663 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
1664 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
1665 /* INIT_EVQ expects index in vector table, not absolute */
1666 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
1667 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
1668 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
1669 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
1670 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
1671 INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge);
1672 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
1673 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
1674 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
1675 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
1676 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
1677 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
1678 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
1679
1680 dma_addr = channel->eventq.buf.dma_addr;
1681 for (i = 0; i < entries; ++i) {
1682 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
1683 dma_addr += EFX_BUF_SIZE;
1684 }
1685
1686 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
1687
1688 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
1689 outbuf, sizeof(outbuf), &outlen);
1690 /* IRQ return is ignored */
1691 return rc;
1692}
1693
1694static void efx_ef10_ev_fini(struct efx_channel *channel)
1695{
1696 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
1697 MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_EVQ_OUT_LEN);
1698 struct efx_nic *efx = channel->efx;
1699 size_t outlen;
1700 int rc;
1701
1702 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
1703
1704 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
1705 outbuf, sizeof(outbuf), &outlen);
1706
1707 if (rc && rc != -EALREADY)
1708 goto fail;
1709
1710 return;
1711
1712fail:
1713 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
1714 outbuf, outlen, rc);
1715}
1716
1717static void efx_ef10_ev_remove(struct efx_channel *channel)
1718{
1719 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
1720}
1721
1722static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
1723 unsigned int rx_queue_label)
1724{
1725 struct efx_nic *efx = rx_queue->efx;
1726
1727 netif_info(efx, hw, efx->net_dev,
1728 "rx event arrived on queue %d labeled as queue %u\n",
1729 efx_rx_queue_index(rx_queue), rx_queue_label);
1730
1731 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1732}
1733
1734static void
1735efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
1736 unsigned int actual, unsigned int expected)
1737{
1738 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
1739 struct efx_nic *efx = rx_queue->efx;
1740
1741 netif_info(efx, hw, efx->net_dev,
1742 "dropped %d events (index=%d expected=%d)\n",
1743 dropped, actual, expected);
1744
1745 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1746}
1747
1748/* partially received RX was aborted. clean up. */
1749static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
1750{
1751 unsigned int rx_desc_ptr;
1752
1753 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
1754 "scattered RX aborted (dropping %u buffers)\n",
1755 rx_queue->scatter_n);
1756
1757 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
1758
1759 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
1760 0, EFX_RX_PKT_DISCARD);
1761
1762 rx_queue->removed_count += rx_queue->scatter_n;
1763 rx_queue->scatter_n = 0;
1764 rx_queue->scatter_len = 0;
1765 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
1766}
1767
1768static int efx_ef10_handle_rx_event(struct efx_channel *channel,
1769 const efx_qword_t *event)
1770{
1771 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
1772 unsigned int n_descs, n_packets, i;
1773 struct efx_nic *efx = channel->efx;
1774 struct efx_rx_queue *rx_queue;
1775 bool rx_cont;
1776 u16 flags = 0;
1777
1778 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
1779 return 0;
1780
1781 /* Basic packet information */
1782 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
1783 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
1784 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
1785 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
1786 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
1787
1788 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
1789 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
1790 EFX_QWORD_FMT "\n",
1791 EFX_QWORD_VAL(*event));
1792
1793 rx_queue = efx_channel_get_rx_queue(channel);
1794
1795 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
1796 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
1797
1798 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
1799 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
1800
1801 if (n_descs != rx_queue->scatter_n + 1) {
1802 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1803
1804 /* detect rx abort */
1805 if (unlikely(n_descs == rx_queue->scatter_n)) {
1806 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
1807 netdev_WARN(efx->net_dev,
1808 "invalid RX abort: scatter_n=%u event="
1809 EFX_QWORD_FMT "\n",
1810 rx_queue->scatter_n,
1811 EFX_QWORD_VAL(*event));
1812 efx_ef10_handle_rx_abort(rx_queue);
1813 return 0;
1814 }
1815
1816 /* Check that RX completion merging is valid, i.e.
1817 * the current firmware supports it and this is a
1818 * non-scattered packet.
1819 */
1820 if (!(nic_data->datapath_caps &
1821 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
1822 rx_queue->scatter_n != 0 || rx_cont) {
1823 efx_ef10_handle_rx_bad_lbits(
1824 rx_queue, next_ptr_lbits,
1825 (rx_queue->removed_count +
1826 rx_queue->scatter_n + 1) &
1827 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
1828 return 0;
1829 }
1830
1831 /* Merged completion for multiple non-scattered packets */
1832 rx_queue->scatter_n = 1;
1833 rx_queue->scatter_len = 0;
1834 n_packets = n_descs;
1835 ++channel->n_rx_merge_events;
1836 channel->n_rx_merge_packets += n_packets;
1837 flags |= EFX_RX_PKT_PREFIX_LEN;
1838 } else {
1839 ++rx_queue->scatter_n;
1840 rx_queue->scatter_len += rx_bytes;
1841 if (rx_cont)
1842 return 0;
1843 n_packets = 1;
1844 }
1845
1846 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
1847 flags |= EFX_RX_PKT_DISCARD;
1848
1849 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
1850 channel->n_rx_ip_hdr_chksum_err += n_packets;
1851 } else if (unlikely(EFX_QWORD_FIELD(*event,
1852 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
1853 channel->n_rx_tcp_udp_chksum_err += n_packets;
1854 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
1855 rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
1856 flags |= EFX_RX_PKT_CSUMMED;
1857 }
1858
1859 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
1860 flags |= EFX_RX_PKT_TCP;
1861
1862 channel->irq_mod_score += 2 * n_packets;
1863
1864 /* Handle received packet(s) */
1865 for (i = 0; i < n_packets; i++) {
1866 efx_rx_packet(rx_queue,
1867 rx_queue->removed_count & rx_queue->ptr_mask,
1868 rx_queue->scatter_n, rx_queue->scatter_len,
1869 flags);
1870 rx_queue->removed_count += rx_queue->scatter_n;
1871 }
1872
1873 rx_queue->scatter_n = 0;
1874 rx_queue->scatter_len = 0;
1875
1876 return n_packets;
1877}
1878
1879static int
1880efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
1881{
1882 struct efx_nic *efx = channel->efx;
1883 struct efx_tx_queue *tx_queue;
1884 unsigned int tx_ev_desc_ptr;
1885 unsigned int tx_ev_q_label;
1886 int tx_descs = 0;
1887
1888 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
1889 return 0;
1890
1891 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
1892 return 0;
1893
1894 /* Transmit completion */
1895 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
1896 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
1897 tx_queue = efx_channel_get_tx_queue(channel,
1898 tx_ev_q_label % EFX_TXQ_TYPES);
1899 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
1900 tx_queue->ptr_mask);
1901 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
1902
1903 return tx_descs;
1904}
1905
1906static void
1907efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
1908{
1909 struct efx_nic *efx = channel->efx;
1910 int subcode;
1911
1912 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
1913
1914 switch (subcode) {
1915 case ESE_DZ_DRV_TIMER_EV:
1916 case ESE_DZ_DRV_WAKE_UP_EV:
1917 break;
1918 case ESE_DZ_DRV_START_UP_EV:
1919 /* event queue init complete. ok. */
1920 break;
1921 default:
1922 netif_err(efx, hw, efx->net_dev,
1923 "channel %d unknown driver event type %d"
1924 " (data " EFX_QWORD_FMT ")\n",
1925 channel->channel, subcode,
1926 EFX_QWORD_VAL(*event));
1927
1928 }
1929}
1930
1931static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
1932 efx_qword_t *event)
1933{
1934 struct efx_nic *efx = channel->efx;
1935 u32 subcode;
1936
1937 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
1938
1939 switch (subcode) {
1940 case EFX_EF10_TEST:
1941 channel->event_test_cpu = raw_smp_processor_id();
1942 break;
1943 case EFX_EF10_REFILL:
1944 /* The queue must be empty, so we won't receive any rx
1945 * events, so efx_process_channel() won't refill the
1946 * queue. Refill it here
1947 */
1948 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
1949 break;
1950 default:
1951 netif_err(efx, hw, efx->net_dev,
1952 "channel %d unknown driver event type %u"
1953 " (data " EFX_QWORD_FMT ")\n",
1954 channel->channel, (unsigned) subcode,
1955 EFX_QWORD_VAL(*event));
1956 }
1957}
1958
1959static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
1960{
1961 struct efx_nic *efx = channel->efx;
1962 efx_qword_t event, *p_event;
1963 unsigned int read_ptr;
1964 int ev_code;
1965 int tx_descs = 0;
1966 int spent = 0;
1967
1968 if (quota <= 0)
1969 return spent;
1970
1971 read_ptr = channel->eventq_read_ptr;
1972
1973 for (;;) {
1974 p_event = efx_event(channel, read_ptr);
1975 event = *p_event;
1976
1977 if (!efx_event_present(&event))
1978 break;
1979
1980 EFX_SET_QWORD(*p_event);
1981
1982 ++read_ptr;
1983
1984 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
1985
1986 netif_vdbg(efx, drv, efx->net_dev,
1987 "processing event on %d " EFX_QWORD_FMT "\n",
1988 channel->channel, EFX_QWORD_VAL(event));
1989
1990 switch (ev_code) {
1991 case ESE_DZ_EV_CODE_MCDI_EV:
1992 efx_mcdi_process_event(channel, &event);
1993 break;
1994 case ESE_DZ_EV_CODE_RX_EV:
1995 spent += efx_ef10_handle_rx_event(channel, &event);
1996 if (spent >= quota) {
1997 /* XXX can we split a merged event to
1998 * avoid going over-quota?
1999 */
2000 spent = quota;
2001 goto out;
2002 }
2003 break;
2004 case ESE_DZ_EV_CODE_TX_EV:
2005 tx_descs += efx_ef10_handle_tx_event(channel, &event);
2006 if (tx_descs > efx->txq_entries) {
2007 spent = quota;
2008 goto out;
2009 } else if (++spent == quota) {
2010 goto out;
2011 }
2012 break;
2013 case ESE_DZ_EV_CODE_DRIVER_EV:
2014 efx_ef10_handle_driver_event(channel, &event);
2015 if (++spent == quota)
2016 goto out;
2017 break;
2018 case EFX_EF10_DRVGEN_EV:
2019 efx_ef10_handle_driver_generated_event(channel, &event);
2020 break;
2021 default:
2022 netif_err(efx, hw, efx->net_dev,
2023 "channel %d unknown event type %d"
2024 " (data " EFX_QWORD_FMT ")\n",
2025 channel->channel, ev_code,
2026 EFX_QWORD_VAL(event));
2027 }
2028 }
2029
2030out:
2031 channel->eventq_read_ptr = read_ptr;
2032 return spent;
2033}
2034
2035static void efx_ef10_ev_read_ack(struct efx_channel *channel)
2036{
2037 struct efx_nic *efx = channel->efx;
2038 efx_dword_t rptr;
2039
2040 if (EFX_EF10_WORKAROUND_35388(efx)) {
2041 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
2042 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
2043 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
2044 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
2045
2046 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2047 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
2048 ERF_DD_EVQ_IND_RPTR,
2049 (channel->eventq_read_ptr &
2050 channel->eventq_mask) >>
2051 ERF_DD_EVQ_IND_RPTR_WIDTH);
2052 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2053 channel->channel);
2054 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2055 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
2056 ERF_DD_EVQ_IND_RPTR,
2057 channel->eventq_read_ptr &
2058 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
2059 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2060 channel->channel);
2061 } else {
2062 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
2063 channel->eventq_read_ptr &
2064 channel->eventq_mask);
2065 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
2066 }
2067}
2068
2069static void efx_ef10_ev_test_generate(struct efx_channel *channel)
2070{
2071 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2072 struct efx_nic *efx = channel->efx;
2073 efx_qword_t event;
2074 int rc;
2075
2076 EFX_POPULATE_QWORD_2(event,
2077 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2078 ESF_DZ_EV_DATA, EFX_EF10_TEST);
2079
2080 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2081
2082 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2083 * already swapped the data to little-endian order.
2084 */
2085 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2086 sizeof(efx_qword_t));
2087
2088 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
2089 NULL, 0, NULL);
2090 if (rc != 0)
2091 goto fail;
2092
2093 return;
2094
2095fail:
2096 WARN_ON(true);
2097 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2098}
2099
2100void efx_ef10_handle_drain_event(struct efx_nic *efx)
2101{
2102 if (atomic_dec_and_test(&efx->active_queues))
2103 wake_up(&efx->flush_wq);
2104
2105 WARN_ON(atomic_read(&efx->active_queues) < 0);
2106}
2107
2108static int efx_ef10_fini_dmaq(struct efx_nic *efx)
2109{
2110 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2111 struct efx_channel *channel;
2112 struct efx_tx_queue *tx_queue;
2113 struct efx_rx_queue *rx_queue;
2114 int pending;
2115
2116 /* If the MC has just rebooted, the TX/RX queues will have already been
2117 * torn down, but efx->active_queues needs to be set to zero.
2118 */
2119 if (nic_data->must_realloc_vis) {
2120 atomic_set(&efx->active_queues, 0);
2121 return 0;
2122 }
2123
2124 /* Do not attempt to write to the NIC during EEH recovery */
2125 if (efx->state != STATE_RECOVERY) {
2126 efx_for_each_channel(channel, efx) {
2127 efx_for_each_channel_rx_queue(rx_queue, channel)
2128 efx_ef10_rx_fini(rx_queue);
2129 efx_for_each_channel_tx_queue(tx_queue, channel)
2130 efx_ef10_tx_fini(tx_queue);
2131 }
2132
2133 wait_event_timeout(efx->flush_wq,
2134 atomic_read(&efx->active_queues) == 0,
2135 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
2136 pending = atomic_read(&efx->active_queues);
2137 if (pending) {
2138 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
2139 pending);
2140 return -ETIMEDOUT;
2141 }
2142 }
2143
2144 return 0;
2145}
2146
2147static void efx_ef10_prepare_flr(struct efx_nic *efx)
2148{
2149 atomic_set(&efx->active_queues, 0);
2150}
2151
2152static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
2153 const struct efx_filter_spec *right)
2154{
2155 if ((left->match_flags ^ right->match_flags) |
2156 ((left->flags ^ right->flags) &
2157 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
2158 return false;
2159
2160 return memcmp(&left->outer_vid, &right->outer_vid,
2161 sizeof(struct efx_filter_spec) -
2162 offsetof(struct efx_filter_spec, outer_vid)) == 0;
2163}
2164
2165static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
2166{
2167 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
2168 return jhash2((const u32 *)&spec->outer_vid,
2169 (sizeof(struct efx_filter_spec) -
2170 offsetof(struct efx_filter_spec, outer_vid)) / 4,
2171 0);
2172 /* XXX should we randomise the initval? */
2173}
2174
2175/* Decide whether a filter should be exclusive or else should allow
2176 * delivery to additional recipients. Currently we decide that
2177 * filters for specific local unicast MAC and IP addresses are
2178 * exclusive.
2179 */
2180static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
2181{
2182 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
2183 !is_multicast_ether_addr(spec->loc_mac))
2184 return true;
2185
2186 if ((spec->match_flags &
2187 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
2188 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
2189 if (spec->ether_type == htons(ETH_P_IP) &&
2190 !ipv4_is_multicast(spec->loc_host[0]))
2191 return true;
2192 if (spec->ether_type == htons(ETH_P_IPV6) &&
2193 ((const u8 *)spec->loc_host)[0] != 0xff)
2194 return true;
2195 }
2196
2197 return false;
2198}
2199
2200static struct efx_filter_spec *
2201efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
2202 unsigned int filter_idx)
2203{
2204 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
2205 ~EFX_EF10_FILTER_FLAGS);
2206}
2207
2208static unsigned int
2209efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
2210 unsigned int filter_idx)
2211{
2212 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
2213}
2214
2215static void
2216efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
2217 unsigned int filter_idx,
2218 const struct efx_filter_spec *spec,
2219 unsigned int flags)
2220{
2221 table->entry[filter_idx].spec = (unsigned long)spec | flags;
2222}
2223
2224static void efx_ef10_filter_push_prep(struct efx_nic *efx,
2225 const struct efx_filter_spec *spec,
2226 efx_dword_t *inbuf, u64 handle,
2227 bool replacing)
2228{
2229 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2230
2231 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
2232
2233 if (replacing) {
2234 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2235 MC_CMD_FILTER_OP_IN_OP_REPLACE);
2236 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
2237 } else {
2238 u32 match_fields = 0;
2239
2240 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2241 efx_ef10_filter_is_exclusive(spec) ?
2242 MC_CMD_FILTER_OP_IN_OP_INSERT :
2243 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
2244
2245 /* Convert match flags and values. Unlike almost
2246 * everything else in MCDI, these fields are in
2247 * network byte order.
2248 */
2249 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
2250 match_fields |=
2251 is_multicast_ether_addr(spec->loc_mac) ?
2252 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
2253 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
2254#define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
2255 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
2256 match_fields |= \
2257 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
2258 mcdi_field ## _LBN; \
2259 BUILD_BUG_ON( \
2260 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
2261 sizeof(spec->gen_field)); \
2262 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
2263 &spec->gen_field, sizeof(spec->gen_field)); \
2264 }
2265 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
2266 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
2267 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
2268 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
2269 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
2270 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
2271 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
2272 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
2273 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
2274 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
2275#undef COPY_FIELD
2276 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
2277 match_fields);
2278 }
2279
2280 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
2281 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
2282 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2283 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
2284 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
2285 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
2286 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
2287 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
2288 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
2289 0 : spec->dmaq_id);
2290 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
2291 (spec->flags & EFX_FILTER_FLAG_RX_RSS) ?
2292 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
2293 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
2294 if (spec->flags & EFX_FILTER_FLAG_RX_RSS)
2295 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
2296 spec->rss_context !=
2297 EFX_FILTER_RSS_CONTEXT_DEFAULT ?
2298 spec->rss_context : nic_data->rx_rss_context);
2299}
2300
2301static int efx_ef10_filter_push(struct efx_nic *efx,
2302 const struct efx_filter_spec *spec,
2303 u64 *handle, bool replacing)
2304{
2305 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2306 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
2307 int rc;
2308
2309 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
2310 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2311 outbuf, sizeof(outbuf), NULL);
2312 if (rc == 0)
2313 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
2314 if (rc == -ENOSPC)
2315 rc = -EBUSY; /* to match efx_farch_filter_insert() */
2316 return rc;
2317}
2318
2319static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table,
2320 enum efx_filter_match_flags match_flags)
2321{
2322 unsigned int match_pri;
2323
2324 for (match_pri = 0;
2325 match_pri < table->rx_match_count;
2326 match_pri++)
2327 if (table->rx_match_flags[match_pri] == match_flags)
2328 return match_pri;
2329
2330 return -EPROTONOSUPPORT;
2331}
2332
2333static s32 efx_ef10_filter_insert(struct efx_nic *efx,
2334 struct efx_filter_spec *spec,
2335 bool replace_equal)
2336{
2337 struct efx_ef10_filter_table *table = efx->filter_state;
2338 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
2339 struct efx_filter_spec *saved_spec;
2340 unsigned int match_pri, hash;
2341 unsigned int priv_flags;
2342 bool replacing = false;
2343 int ins_index = -1;
2344 DEFINE_WAIT(wait);
2345 bool is_mc_recip;
2346 s32 rc;
2347
2348 /* For now, only support RX filters */
2349 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
2350 EFX_FILTER_FLAG_RX)
2351 return -EINVAL;
2352
2353 rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags);
2354 if (rc < 0)
2355 return rc;
2356 match_pri = rc;
2357
2358 hash = efx_ef10_filter_hash(spec);
2359 is_mc_recip = efx_filter_is_mc_recipient(spec);
2360 if (is_mc_recip)
2361 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
2362
2363 /* Find any existing filters with the same match tuple or
2364 * else a free slot to insert at. If any of them are busy,
2365 * we have to wait and retry.
2366 */
2367 for (;;) {
2368 unsigned int depth = 1;
2369 unsigned int i;
2370
2371 spin_lock_bh(&efx->filter_lock);
2372
2373 for (;;) {
2374 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2375 saved_spec = efx_ef10_filter_entry_spec(table, i);
2376
2377 if (!saved_spec) {
2378 if (ins_index < 0)
2379 ins_index = i;
2380 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
2381 if (table->entry[i].spec &
2382 EFX_EF10_FILTER_FLAG_BUSY)
2383 break;
2384 if (spec->priority < saved_spec->priority &&
2385 spec->priority != EFX_FILTER_PRI_AUTO) {
2386 rc = -EPERM;
2387 goto out_unlock;
2388 }
2389 if (!is_mc_recip) {
2390 /* This is the only one */
2391 if (spec->priority ==
2392 saved_spec->priority &&
2393 !replace_equal) {
2394 rc = -EEXIST;
2395 goto out_unlock;
2396 }
2397 ins_index = i;
2398 goto found;
2399 } else if (spec->priority >
2400 saved_spec->priority ||
2401 (spec->priority ==
2402 saved_spec->priority &&
2403 replace_equal)) {
2404 if (ins_index < 0)
2405 ins_index = i;
2406 else
2407 __set_bit(depth, mc_rem_map);
2408 }
2409 }
2410
2411 /* Once we reach the maximum search depth, use
2412 * the first suitable slot or return -EBUSY if
2413 * there was none
2414 */
2415 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
2416 if (ins_index < 0) {
2417 rc = -EBUSY;
2418 goto out_unlock;
2419 }
2420 goto found;
2421 }
2422
2423 ++depth;
2424 }
2425
2426 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
2427 spin_unlock_bh(&efx->filter_lock);
2428 schedule();
2429 }
2430
2431found:
2432 /* Create a software table entry if necessary, and mark it
2433 * busy. We might yet fail to insert, but any attempt to
2434 * insert a conflicting filter while we're waiting for the
2435 * firmware must find the busy entry.
2436 */
2437 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
2438 if (saved_spec) {
2439 if (spec->priority == EFX_FILTER_PRI_AUTO &&
2440 saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
2441 /* Just make sure it won't be removed */
2442 if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
2443 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
2444 table->entry[ins_index].spec &=
2445 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
2446 rc = ins_index;
2447 goto out_unlock;
2448 }
2449 replacing = true;
2450 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
2451 } else {
2452 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
2453 if (!saved_spec) {
2454 rc = -ENOMEM;
2455 goto out_unlock;
2456 }
2457 *saved_spec = *spec;
2458 priv_flags = 0;
2459 }
2460 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
2461 priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
2462
2463 /* Mark lower-priority multicast recipients busy prior to removal */
2464 if (is_mc_recip) {
2465 unsigned int depth, i;
2466
2467 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
2468 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2469 if (test_bit(depth, mc_rem_map))
2470 table->entry[i].spec |=
2471 EFX_EF10_FILTER_FLAG_BUSY;
2472 }
2473 }
2474
2475 spin_unlock_bh(&efx->filter_lock);
2476
2477 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
2478 replacing);
2479
2480 /* Finalise the software table entry */
2481 spin_lock_bh(&efx->filter_lock);
2482 if (rc == 0) {
2483 if (replacing) {
2484 /* Update the fields that may differ */
2485 if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
2486 saved_spec->flags |=
2487 EFX_FILTER_FLAG_RX_OVER_AUTO;
2488 saved_spec->priority = spec->priority;
2489 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
2490 saved_spec->flags |= spec->flags;
2491 saved_spec->rss_context = spec->rss_context;
2492 saved_spec->dmaq_id = spec->dmaq_id;
2493 }
2494 } else if (!replacing) {
2495 kfree(saved_spec);
2496 saved_spec = NULL;
2497 }
2498 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
2499
2500 /* Remove and finalise entries for lower-priority multicast
2501 * recipients
2502 */
2503 if (is_mc_recip) {
2504 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2505 unsigned int depth, i;
2506
2507 memset(inbuf, 0, sizeof(inbuf));
2508
2509 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
2510 if (!test_bit(depth, mc_rem_map))
2511 continue;
2512
2513 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2514 saved_spec = efx_ef10_filter_entry_spec(table, i);
2515 priv_flags = efx_ef10_filter_entry_flags(table, i);
2516
2517 if (rc == 0) {
2518 spin_unlock_bh(&efx->filter_lock);
2519 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2520 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2521 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2522 table->entry[i].handle);
2523 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
2524 inbuf, sizeof(inbuf),
2525 NULL, 0, NULL);
2526 spin_lock_bh(&efx->filter_lock);
2527 }
2528
2529 if (rc == 0) {
2530 kfree(saved_spec);
2531 saved_spec = NULL;
2532 priv_flags = 0;
2533 } else {
2534 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
2535 }
2536 efx_ef10_filter_set_entry(table, i, saved_spec,
2537 priv_flags);
2538 }
2539 }
2540
2541 /* If successful, return the inserted filter ID */
2542 if (rc == 0)
2543 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
2544
2545 wake_up_all(&table->waitq);
2546out_unlock:
2547 spin_unlock_bh(&efx->filter_lock);
2548 finish_wait(&table->waitq, &wait);
2549 return rc;
2550}
2551
2552static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
2553{
2554 /* no need to do anything here on EF10 */
2555}
2556
2557/* Remove a filter.
2558 * If !by_index, remove by ID
2559 * If by_index, remove by index
2560 * Filter ID may come from userland and must be range-checked.
2561 */
2562static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
2563 unsigned int priority_mask,
2564 u32 filter_id, bool by_index)
2565{
2566 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
2567 struct efx_ef10_filter_table *table = efx->filter_state;
2568 MCDI_DECLARE_BUF(inbuf,
2569 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
2570 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
2571 struct efx_filter_spec *spec;
2572 DEFINE_WAIT(wait);
2573 int rc;
2574
2575 /* Find the software table entry and mark it busy. Don't
2576 * remove it yet; any attempt to update while we're waiting
2577 * for the firmware must find the busy entry.
2578 */
2579 for (;;) {
2580 spin_lock_bh(&efx->filter_lock);
2581 if (!(table->entry[filter_idx].spec &
2582 EFX_EF10_FILTER_FLAG_BUSY))
2583 break;
2584 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
2585 spin_unlock_bh(&efx->filter_lock);
2586 schedule();
2587 }
2588
2589 spec = efx_ef10_filter_entry_spec(table, filter_idx);
2590 if (!spec ||
2591 (!by_index &&
2592 efx_ef10_filter_rx_match_pri(table, spec->match_flags) !=
2593 filter_id / HUNT_FILTER_TBL_ROWS)) {
2594 rc = -ENOENT;
2595 goto out_unlock;
2596 }
2597
2598 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
2599 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
2600 /* Just remove flags */
2601 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
2602 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
2603 rc = 0;
2604 goto out_unlock;
2605 }
2606
2607 if (!(priority_mask & (1U << spec->priority))) {
2608 rc = -ENOENT;
2609 goto out_unlock;
2610 }
2611
2612 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
2613 spin_unlock_bh(&efx->filter_lock);
2614
2615 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
2616 /* Reset to an automatic filter */
2617
2618 struct efx_filter_spec new_spec = *spec;
2619
2620 new_spec.priority = EFX_FILTER_PRI_AUTO;
2621 new_spec.flags = (EFX_FILTER_FLAG_RX |
2622 EFX_FILTER_FLAG_RX_RSS);
2623 new_spec.dmaq_id = 0;
2624 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
2625 rc = efx_ef10_filter_push(efx, &new_spec,
2626 &table->entry[filter_idx].handle,
2627 true);
2628
2629 spin_lock_bh(&efx->filter_lock);
2630 if (rc == 0)
2631 *spec = new_spec;
2632 } else {
2633 /* Really remove the filter */
2634
2635 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2636 efx_ef10_filter_is_exclusive(spec) ?
2637 MC_CMD_FILTER_OP_IN_OP_REMOVE :
2638 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
2639 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2640 table->entry[filter_idx].handle);
2641 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
2642 inbuf, sizeof(inbuf), NULL, 0, NULL);
2643
2644 spin_lock_bh(&efx->filter_lock);
2645 if (rc == 0) {
2646 kfree(spec);
2647 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
2648 }
2649 }
2650
2651 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
2652 wake_up_all(&table->waitq);
2653out_unlock:
2654 spin_unlock_bh(&efx->filter_lock);
2655 finish_wait(&table->waitq, &wait);
2656 return rc;
2657}
2658
2659static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
2660 enum efx_filter_priority priority,
2661 u32 filter_id)
2662{
2663 return efx_ef10_filter_remove_internal(efx, 1U << priority,
2664 filter_id, false);
2665}
2666
2667static int efx_ef10_filter_get_safe(struct efx_nic *efx,
2668 enum efx_filter_priority priority,
2669 u32 filter_id, struct efx_filter_spec *spec)
2670{
2671 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
2672 struct efx_ef10_filter_table *table = efx->filter_state;
2673 const struct efx_filter_spec *saved_spec;
2674 int rc;
2675
2676 spin_lock_bh(&efx->filter_lock);
2677 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
2678 if (saved_spec && saved_spec->priority == priority &&
2679 efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) ==
2680 filter_id / HUNT_FILTER_TBL_ROWS) {
2681 *spec = *saved_spec;
2682 rc = 0;
2683 } else {
2684 rc = -ENOENT;
2685 }
2686 spin_unlock_bh(&efx->filter_lock);
2687 return rc;
2688}
2689
2690static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
2691 enum efx_filter_priority priority)
2692{
2693 unsigned int priority_mask;
2694 unsigned int i;
2695 int rc;
2696
2697 priority_mask = (((1U << (priority + 1)) - 1) &
2698 ~(1U << EFX_FILTER_PRI_AUTO));
2699
2700 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
2701 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
2702 i, true);
2703 if (rc && rc != -ENOENT)
2704 return rc;
2705 }
2706
2707 return 0;
2708}
2709
2710static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
2711 enum efx_filter_priority priority)
2712{
2713 struct efx_ef10_filter_table *table = efx->filter_state;
2714 unsigned int filter_idx;
2715 s32 count = 0;
2716
2717 spin_lock_bh(&efx->filter_lock);
2718 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
2719 if (table->entry[filter_idx].spec &&
2720 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
2721 priority)
2722 ++count;
2723 }
2724 spin_unlock_bh(&efx->filter_lock);
2725 return count;
2726}
2727
2728static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
2729{
2730 struct efx_ef10_filter_table *table = efx->filter_state;
2731
2732 return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
2733}
2734
2735static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
2736 enum efx_filter_priority priority,
2737 u32 *buf, u32 size)
2738{
2739 struct efx_ef10_filter_table *table = efx->filter_state;
2740 struct efx_filter_spec *spec;
2741 unsigned int filter_idx;
2742 s32 count = 0;
2743
2744 spin_lock_bh(&efx->filter_lock);
2745 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
2746 spec = efx_ef10_filter_entry_spec(table, filter_idx);
2747 if (spec && spec->priority == priority) {
2748 if (count == size) {
2749 count = -EMSGSIZE;
2750 break;
2751 }
2752 buf[count++] = (efx_ef10_filter_rx_match_pri(
2753 table, spec->match_flags) *
2754 HUNT_FILTER_TBL_ROWS +
2755 filter_idx);
2756 }
2757 }
2758 spin_unlock_bh(&efx->filter_lock);
2759 return count;
2760}
2761
2762#ifdef CONFIG_RFS_ACCEL
2763
2764static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
2765
2766static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
2767 struct efx_filter_spec *spec)
2768{
2769 struct efx_ef10_filter_table *table = efx->filter_state;
2770 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
2771 struct efx_filter_spec *saved_spec;
2772 unsigned int hash, i, depth = 1;
2773 bool replacing = false;
2774 int ins_index = -1;
2775 u64 cookie;
2776 s32 rc;
2777
2778 /* Must be an RX filter without RSS and not for a multicast
2779 * destination address (RFS only works for connected sockets).
2780 * These restrictions allow us to pass only a tiny amount of
2781 * data through to the completion function.
2782 */
2783 EFX_WARN_ON_PARANOID(spec->flags !=
2784 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
2785 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
2786 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
2787
2788 hash = efx_ef10_filter_hash(spec);
2789
2790 spin_lock_bh(&efx->filter_lock);
2791
2792 /* Find any existing filter with the same match tuple or else
2793 * a free slot to insert at. If an existing filter is busy,
2794 * we have to give up.
2795 */
2796 for (;;) {
2797 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
2798 saved_spec = efx_ef10_filter_entry_spec(table, i);
2799
2800 if (!saved_spec) {
2801 if (ins_index < 0)
2802 ins_index = i;
2803 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
2804 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
2805 rc = -EBUSY;
2806 goto fail_unlock;
2807 }
2808 if (spec->priority < saved_spec->priority) {
2809 rc = -EPERM;
2810 goto fail_unlock;
2811 }
2812 ins_index = i;
2813 break;
2814 }
2815
2816 /* Once we reach the maximum search depth, use the
2817 * first suitable slot or return -EBUSY if there was
2818 * none
2819 */
2820 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
2821 if (ins_index < 0) {
2822 rc = -EBUSY;
2823 goto fail_unlock;
2824 }
2825 break;
2826 }
2827
2828 ++depth;
2829 }
2830
2831 /* Create a software table entry if necessary, and mark it
2832 * busy. We might yet fail to insert, but any attempt to
2833 * insert a conflicting filter while we're waiting for the
2834 * firmware must find the busy entry.
2835 */
2836 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
2837 if (saved_spec) {
2838 replacing = true;
2839 } else {
2840 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
2841 if (!saved_spec) {
2842 rc = -ENOMEM;
2843 goto fail_unlock;
2844 }
2845 *saved_spec = *spec;
2846 }
2847 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
2848 EFX_EF10_FILTER_FLAG_BUSY);
2849
2850 spin_unlock_bh(&efx->filter_lock);
2851
2852 /* Pack up the variables needed on completion */
2853 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
2854
2855 efx_ef10_filter_push_prep(efx, spec, inbuf,
2856 table->entry[ins_index].handle, replacing);
2857 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
2858 MC_CMD_FILTER_OP_OUT_LEN,
2859 efx_ef10_filter_rfs_insert_complete, cookie);
2860
2861 return ins_index;
2862
2863fail_unlock:
2864 spin_unlock_bh(&efx->filter_lock);
2865 return rc;
2866}
2867
2868static void
2869efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
2870 int rc, efx_dword_t *outbuf,
2871 size_t outlen_actual)
2872{
2873 struct efx_ef10_filter_table *table = efx->filter_state;
2874 unsigned int ins_index, dmaq_id;
2875 struct efx_filter_spec *spec;
2876 bool replacing;
2877
2878 /* Unpack the cookie */
2879 replacing = cookie >> 31;
2880 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
2881 dmaq_id = cookie & 0xffff;
2882
2883 spin_lock_bh(&efx->filter_lock);
2884 spec = efx_ef10_filter_entry_spec(table, ins_index);
2885 if (rc == 0) {
2886 table->entry[ins_index].handle =
2887 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
2888 if (replacing)
2889 spec->dmaq_id = dmaq_id;
2890 } else if (!replacing) {
2891 kfree(spec);
2892 spec = NULL;
2893 }
2894 efx_ef10_filter_set_entry(table, ins_index, spec, 0);
2895 spin_unlock_bh(&efx->filter_lock);
2896
2897 wake_up_all(&table->waitq);
2898}
2899
2900static void
2901efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
2902 unsigned long filter_idx,
2903 int rc, efx_dword_t *outbuf,
2904 size_t outlen_actual);
2905
2906static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
2907 unsigned int filter_idx)
2908{
2909 struct efx_ef10_filter_table *table = efx->filter_state;
2910 struct efx_filter_spec *spec =
2911 efx_ef10_filter_entry_spec(table, filter_idx);
2912 MCDI_DECLARE_BUF(inbuf,
2913 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
2914 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
2915
2916 if (!spec ||
2917 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
2918 spec->priority != EFX_FILTER_PRI_HINT ||
2919 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
2920 flow_id, filter_idx))
2921 return false;
2922
2923 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
2924 MC_CMD_FILTER_OP_IN_OP_REMOVE);
2925 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
2926 table->entry[filter_idx].handle);
2927 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
2928 efx_ef10_filter_rfs_expire_complete, filter_idx))
2929 return false;
2930
2931 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
2932 return true;
2933}
2934
2935static void
2936efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
2937 unsigned long filter_idx,
2938 int rc, efx_dword_t *outbuf,
2939 size_t outlen_actual)
2940{
2941 struct efx_ef10_filter_table *table = efx->filter_state;
2942 struct efx_filter_spec *spec =
2943 efx_ef10_filter_entry_spec(table, filter_idx);
2944
2945 spin_lock_bh(&efx->filter_lock);
2946 if (rc == 0) {
2947 kfree(spec);
2948 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
2949 }
2950 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
2951 wake_up_all(&table->waitq);
2952 spin_unlock_bh(&efx->filter_lock);
2953}
2954
2955#endif /* CONFIG_RFS_ACCEL */
2956
2957static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
2958{
2959 int match_flags = 0;
2960
2961#define MAP_FLAG(gen_flag, mcdi_field) { \
2962 u32 old_mcdi_flags = mcdi_flags; \
2963 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
2964 mcdi_field ## _LBN); \
2965 if (mcdi_flags != old_mcdi_flags) \
2966 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
2967 }
2968 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
2969 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
2970 MAP_FLAG(REM_HOST, SRC_IP);
2971 MAP_FLAG(LOC_HOST, DST_IP);
2972 MAP_FLAG(REM_MAC, SRC_MAC);
2973 MAP_FLAG(REM_PORT, SRC_PORT);
2974 MAP_FLAG(LOC_MAC, DST_MAC);
2975 MAP_FLAG(LOC_PORT, DST_PORT);
2976 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
2977 MAP_FLAG(INNER_VID, INNER_VLAN);
2978 MAP_FLAG(OUTER_VID, OUTER_VLAN);
2979 MAP_FLAG(IP_PROTO, IP_PROTO);
2980#undef MAP_FLAG
2981
2982 /* Did we map them all? */
2983 if (mcdi_flags)
2984 return -EINVAL;
2985
2986 return match_flags;
2987}
2988
2989static int efx_ef10_filter_table_probe(struct efx_nic *efx)
2990{
2991 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
2992 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
2993 unsigned int pd_match_pri, pd_match_count;
2994 struct efx_ef10_filter_table *table;
2995 size_t outlen;
2996 int rc;
2997
2998 table = kzalloc(sizeof(*table), GFP_KERNEL);
2999 if (!table)
3000 return -ENOMEM;
3001
3002 /* Find out which RX filter types are supported, and their priorities */
3003 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
3004 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
3005 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
3006 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
3007 &outlen);
3008 if (rc)
3009 goto fail;
3010 pd_match_count = MCDI_VAR_ARRAY_LEN(
3011 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
3012 table->rx_match_count = 0;
3013
3014 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
3015 u32 mcdi_flags =
3016 MCDI_ARRAY_DWORD(
3017 outbuf,
3018 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
3019 pd_match_pri);
3020 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
3021 if (rc < 0) {
3022 netif_dbg(efx, probe, efx->net_dev,
3023 "%s: fw flags %#x pri %u not supported in driver\n",
3024 __func__, mcdi_flags, pd_match_pri);
3025 } else {
3026 netif_dbg(efx, probe, efx->net_dev,
3027 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
3028 __func__, mcdi_flags, pd_match_pri,
3029 rc, table->rx_match_count);
3030 table->rx_match_flags[table->rx_match_count++] = rc;
3031 }
3032 }
3033
3034 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
3035 if (!table->entry) {
3036 rc = -ENOMEM;
3037 goto fail;
3038 }
3039
3040 efx->filter_state = table;
3041 init_waitqueue_head(&table->waitq);
3042 return 0;
3043
3044fail:
3045 kfree(table);
3046 return rc;
3047}
3048
3049static void efx_ef10_filter_table_restore(struct efx_nic *efx)
3050{
3051 struct efx_ef10_filter_table *table = efx->filter_state;
3052 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3053 struct efx_filter_spec *spec;
3054 unsigned int filter_idx;
3055 bool failed = false;
3056 int rc;
3057
3058 if (!nic_data->must_restore_filters)
3059 return;
3060
3061 spin_lock_bh(&efx->filter_lock);
3062
3063 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3064 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3065 if (!spec)
3066 continue;
3067
3068 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3069 spin_unlock_bh(&efx->filter_lock);
3070
3071 rc = efx_ef10_filter_push(efx, spec,
3072 &table->entry[filter_idx].handle,
3073 false);
3074 if (rc)
3075 failed = true;
3076
3077 spin_lock_bh(&efx->filter_lock);
3078 if (rc) {
3079 kfree(spec);
3080 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3081 } else {
3082 table->entry[filter_idx].spec &=
3083 ~EFX_EF10_FILTER_FLAG_BUSY;
3084 }
3085 }
3086
3087 spin_unlock_bh(&efx->filter_lock);
3088
3089 if (failed)
3090 netif_err(efx, hw, efx->net_dev,
3091 "unable to restore all filters\n");
3092 else
3093 nic_data->must_restore_filters = false;
3094}
3095
3096static void efx_ef10_filter_table_remove(struct efx_nic *efx)
3097{
3098 struct efx_ef10_filter_table *table = efx->filter_state;
3099 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3100 struct efx_filter_spec *spec;
3101 unsigned int filter_idx;
3102 int rc;
3103
3104 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3105 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3106 if (!spec)
3107 continue;
3108
3109 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3110 efx_ef10_filter_is_exclusive(spec) ?
3111 MC_CMD_FILTER_OP_IN_OP_REMOVE :
3112 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3113 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3114 table->entry[filter_idx].handle);
3115 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3116 NULL, 0, NULL);
3117 if (rc)
3118 netdev_WARN(efx->net_dev,
3119 "filter_idx=%#x handle=%#llx\n",
3120 filter_idx,
3121 table->entry[filter_idx].handle);
3122 kfree(spec);
3123 }
3124
3125 vfree(table->entry);
3126 kfree(table);
3127}
3128
3129static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
3130{
3131 struct efx_ef10_filter_table *table = efx->filter_state;
3132 struct net_device *net_dev = efx->net_dev;
3133 struct efx_filter_spec spec;
3134 bool remove_failed = false;
3135 struct netdev_hw_addr *uc;
3136 struct netdev_hw_addr *mc;
3137 unsigned int filter_idx;
3138 int i, n, rc;
3139
3140 if (!efx_dev_registered(efx))
3141 return;
3142
3143 /* Mark old filters that may need to be removed */
3144 spin_lock_bh(&efx->filter_lock);
3145 n = table->dev_uc_count < 0 ? 1 : table->dev_uc_count;
3146 for (i = 0; i < n; i++) {
3147 filter_idx = table->dev_uc_list[i].id % HUNT_FILTER_TBL_ROWS;
3148 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
3149 }
3150 n = table->dev_mc_count < 0 ? 1 : table->dev_mc_count;
3151 for (i = 0; i < n; i++) {
3152 filter_idx = table->dev_mc_list[i].id % HUNT_FILTER_TBL_ROWS;
3153 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
3154 }
3155 spin_unlock_bh(&efx->filter_lock);
3156
3157 /* Copy/convert the address lists; add the primary station
3158 * address and broadcast address
3159 */
3160 netif_addr_lock_bh(net_dev);
3161 if (net_dev->flags & IFF_PROMISC ||
3162 netdev_uc_count(net_dev) >= EFX_EF10_FILTER_DEV_UC_MAX) {
3163 table->dev_uc_count = -1;
3164 } else {
3165 table->dev_uc_count = 1 + netdev_uc_count(net_dev);
3166 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
3167 i = 1;
3168 netdev_for_each_uc_addr(uc, net_dev) {
3169 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
3170 i++;
3171 }
3172 }
3173 if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI) ||
3174 netdev_mc_count(net_dev) >= EFX_EF10_FILTER_DEV_MC_MAX) {
3175 table->dev_mc_count = -1;
3176 } else {
3177 table->dev_mc_count = 1 + netdev_mc_count(net_dev);
3178 eth_broadcast_addr(table->dev_mc_list[0].addr);
3179 i = 1;
3180 netdev_for_each_mc_addr(mc, net_dev) {
3181 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
3182 i++;
3183 }
3184 }
3185 netif_addr_unlock_bh(net_dev);
3186
3187 /* Insert/renew unicast filters */
3188 if (table->dev_uc_count >= 0) {
3189 for (i = 0; i < table->dev_uc_count; i++) {
3190 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3191 EFX_FILTER_FLAG_RX_RSS,
3192 0);
3193 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
3194 table->dev_uc_list[i].addr);
3195 rc = efx_ef10_filter_insert(efx, &spec, true);
3196 if (rc < 0) {
3197 /* Fall back to unicast-promisc */
3198 while (i--)
3199 efx_ef10_filter_remove_safe(
3200 efx, EFX_FILTER_PRI_AUTO,
3201 table->dev_uc_list[i].id);
3202 table->dev_uc_count = -1;
3203 break;
3204 }
3205 table->dev_uc_list[i].id = rc;
3206 }
3207 }
3208 if (table->dev_uc_count < 0) {
3209 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3210 EFX_FILTER_FLAG_RX_RSS,
3211 0);
3212 efx_filter_set_uc_def(&spec);
3213 rc = efx_ef10_filter_insert(efx, &spec, true);
3214 if (rc < 0) {
3215 WARN_ON(1);
3216 table->dev_uc_count = 0;
3217 } else {
3218 table->dev_uc_list[0].id = rc;
3219 }
3220 }
3221
3222 /* Insert/renew multicast filters */
3223 if (table->dev_mc_count >= 0) {
3224 for (i = 0; i < table->dev_mc_count; i++) {
3225 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3226 EFX_FILTER_FLAG_RX_RSS,
3227 0);
3228 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC,
3229 table->dev_mc_list[i].addr);
3230 rc = efx_ef10_filter_insert(efx, &spec, true);
3231 if (rc < 0) {
3232 /* Fall back to multicast-promisc */
3233 while (i--)
3234 efx_ef10_filter_remove_safe(
3235 efx, EFX_FILTER_PRI_AUTO,
3236 table->dev_mc_list[i].id);
3237 table->dev_mc_count = -1;
3238 break;
3239 }
3240 table->dev_mc_list[i].id = rc;
3241 }
3242 }
3243 if (table->dev_mc_count < 0) {
3244 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
3245 EFX_FILTER_FLAG_RX_RSS,
3246 0);
3247 efx_filter_set_mc_def(&spec);
3248 rc = efx_ef10_filter_insert(efx, &spec, true);
3249 if (rc < 0) {
3250 WARN_ON(1);
3251 table->dev_mc_count = 0;
3252 } else {
3253 table->dev_mc_list[0].id = rc;
3254 }
3255 }
3256
3257 /* Remove filters that weren't renewed. Since nothing else
3258 * changes the AUTO_OLD flag or removes these filters, we
3259 * don't need to hold the filter_lock while scanning for
3260 * these filters.
3261 */
3262 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3263 if (ACCESS_ONCE(table->entry[i].spec) &
3264 EFX_EF10_FILTER_FLAG_AUTO_OLD) {
3265 if (efx_ef10_filter_remove_internal(
3266 efx, 1U << EFX_FILTER_PRI_AUTO,
3267 i, true) < 0)
3268 remove_failed = true;
3269 }
3270 }
3271 WARN_ON(remove_failed);
3272}
3273
3274static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
3275{
3276 efx_ef10_filter_sync_rx_mode(efx);
3277
3278 return efx_mcdi_set_mac(efx);
3279}
3280
3281static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
3282{
3283 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
3284
3285 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
3286 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
3287 NULL, 0, NULL);
3288}
3289
3290/* MC BISTs follow a different poll mechanism to phy BISTs.
3291 * The BIST is done in the poll handler on the MC, and the MCDI command
3292 * will block until the BIST is done.
3293 */
3294static int efx_ef10_poll_bist(struct efx_nic *efx)
3295{
3296 int rc;
3297 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
3298 size_t outlen;
3299 u32 result;
3300
3301 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
3302 outbuf, sizeof(outbuf), &outlen);
3303 if (rc != 0)
3304 return rc;
3305
3306 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
3307 return -EIO;
3308
3309 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
3310 switch (result) {
3311 case MC_CMD_POLL_BIST_PASSED:
3312 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
3313 return 0;
3314 case MC_CMD_POLL_BIST_TIMEOUT:
3315 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
3316 return -EIO;
3317 case MC_CMD_POLL_BIST_FAILED:
3318 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
3319 return -EIO;
3320 default:
3321 netif_err(efx, hw, efx->net_dev,
3322 "BIST returned unknown result %u", result);
3323 return -EIO;
3324 }
3325}
3326
3327static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
3328{
3329 int rc;
3330
3331 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
3332
3333 rc = efx_ef10_start_bist(efx, bist_type);
3334 if (rc != 0)
3335 return rc;
3336
3337 return efx_ef10_poll_bist(efx);
3338}
3339
3340static int
3341efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
3342{
3343 int rc, rc2;
3344
3345 efx_reset_down(efx, RESET_TYPE_WORLD);
3346
3347 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
3348 NULL, 0, NULL, 0, NULL);
3349 if (rc != 0)
3350 goto out;
3351
3352 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
3353 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
3354
3355 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
3356
3357out:
3358 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
3359 return rc ? rc : rc2;
3360}
3361
3362#ifdef CONFIG_SFC_MTD
3363
3364struct efx_ef10_nvram_type_info {
3365 u16 type, type_mask;
3366 u8 port;
3367 const char *name;
3368};
3369
3370static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
3371 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
3372 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
3373 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
3374 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
3375 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
3376 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
3377 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
3378 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
3379 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
3380 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
3381 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
3382};
3383
3384static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
3385 struct efx_mcdi_mtd_partition *part,
3386 unsigned int type)
3387{
3388 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
3389 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
3390 const struct efx_ef10_nvram_type_info *info;
3391 size_t size, erase_size, outlen;
3392 bool protected;
3393 int rc;
3394
3395 for (info = efx_ef10_nvram_types; ; info++) {
3396 if (info ==
3397 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
3398 return -ENODEV;
3399 if ((type & ~info->type_mask) == info->type)
3400 break;
3401 }
3402 if (info->port != efx_port_num(efx))
3403 return -ENODEV;
3404
3405 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
3406 if (rc)
3407 return rc;
3408 if (protected)
3409 return -ENODEV; /* hide it */
3410
3411 part->nvram_type = type;
3412
3413 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
3414 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
3415 outbuf, sizeof(outbuf), &outlen);
3416 if (rc)
3417 return rc;
3418 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
3419 return -EIO;
3420 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
3421 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
3422 part->fw_subtype = MCDI_DWORD(outbuf,
3423 NVRAM_METADATA_OUT_SUBTYPE);
3424
3425 part->common.dev_type_name = "EF10 NVRAM manager";
3426 part->common.type_name = info->name;
3427
3428 part->common.mtd.type = MTD_NORFLASH;
3429 part->common.mtd.flags = MTD_CAP_NORFLASH;
3430 part->common.mtd.size = size;
3431 part->common.mtd.erasesize = erase_size;
3432
3433 return 0;
3434}
3435
3436static int efx_ef10_mtd_probe(struct efx_nic *efx)
3437{
3438 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
3439 struct efx_mcdi_mtd_partition *parts;
3440 size_t outlen, n_parts_total, i, n_parts;
3441 unsigned int type;
3442 int rc;
3443
3444 ASSERT_RTNL();
3445
3446 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
3447 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
3448 outbuf, sizeof(outbuf), &outlen);
3449 if (rc)
3450 return rc;
3451 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
3452 return -EIO;
3453
3454 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
3455 if (n_parts_total >
3456 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
3457 return -EIO;
3458
3459 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
3460 if (!parts)
3461 return -ENOMEM;
3462
3463 n_parts = 0;
3464 for (i = 0; i < n_parts_total; i++) {
3465 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
3466 i);
3467 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
3468 if (rc == 0)
3469 n_parts++;
3470 else if (rc != -ENODEV)
3471 goto fail;
3472 }
3473
3474 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
3475fail:
3476 if (rc)
3477 kfree(parts);
3478 return rc;
3479}
3480
3481#endif /* CONFIG_SFC_MTD */
3482
3483static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
3484{
3485 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
3486}
3487
3488static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
3489 bool temp)
3490{
3491 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
3492 int rc;
3493
3494 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
3495 channel->sync_events_state == SYNC_EVENTS_VALID ||
3496 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
3497 return 0;
3498 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
3499
3500 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
3501 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
3502 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
3503 channel->channel);
3504
3505 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
3506 inbuf, sizeof(inbuf), NULL, 0, NULL);
3507
3508 if (rc != 0)
3509 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
3510 SYNC_EVENTS_DISABLED;
3511
3512 return rc;
3513}
3514
3515static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
3516 bool temp)
3517{
3518 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
3519 int rc;
3520
3521 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
3522 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
3523 return 0;
3524 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
3525 channel->sync_events_state = SYNC_EVENTS_DISABLED;
3526 return 0;
3527 }
3528 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
3529 SYNC_EVENTS_DISABLED;
3530
3531 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
3532 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
3533 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
3534 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
3535 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
3536 channel->channel);
3537
3538 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
3539 inbuf, sizeof(inbuf), NULL, 0, NULL);
3540
3541 return rc;
3542}
3543
3544static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
3545 bool temp)
3546{
3547 int (*set)(struct efx_channel *channel, bool temp);
3548 struct efx_channel *channel;
3549
3550 set = en ?
3551 efx_ef10_rx_enable_timestamping :
3552 efx_ef10_rx_disable_timestamping;
3553
3554 efx_for_each_channel(channel, efx) {
3555 int rc = set(channel, temp);
3556 if (en && rc != 0) {
3557 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
3558 return rc;
3559 }
3560 }
3561
3562 return 0;
3563}
3564
3565static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
3566 struct hwtstamp_config *init)
3567{
3568 int rc;
3569
3570 switch (init->rx_filter) {
3571 case HWTSTAMP_FILTER_NONE:
3572 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
3573 /* if TX timestamping is still requested then leave PTP on */
3574 return efx_ptp_change_mode(efx,
3575 init->tx_type != HWTSTAMP_TX_OFF, 0);
3576 case HWTSTAMP_FILTER_ALL:
3577 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3578 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3579 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3580 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3581 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3582 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3583 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3584 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3585 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3586 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3587 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3588 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3589 init->rx_filter = HWTSTAMP_FILTER_ALL;
3590 rc = efx_ptp_change_mode(efx, true, 0);
3591 if (!rc)
3592 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
3593 if (rc)
3594 efx_ptp_change_mode(efx, false, 0);
3595 return rc;
3596 default:
3597 return -ERANGE;
3598 }
3599}
3600
3601const struct efx_nic_type efx_hunt_a0_nic_type = {
3602 .mem_map_size = efx_ef10_mem_map_size,
3603 .probe = efx_ef10_probe,
3604 .remove = efx_ef10_remove,
3605 .dimension_resources = efx_ef10_dimension_resources,
3606 .init = efx_ef10_init_nic,
3607 .fini = efx_port_dummy_op_void,
3608 .map_reset_reason = efx_mcdi_map_reset_reason,
3609 .map_reset_flags = efx_ef10_map_reset_flags,
3610 .reset = efx_ef10_reset,
3611 .probe_port = efx_mcdi_port_probe,
3612 .remove_port = efx_mcdi_port_remove,
3613 .fini_dmaq = efx_ef10_fini_dmaq,
3614 .prepare_flr = efx_ef10_prepare_flr,
3615 .finish_flr = efx_port_dummy_op_void,
3616 .describe_stats = efx_ef10_describe_stats,
3617 .update_stats = efx_ef10_update_stats,
3618 .start_stats = efx_mcdi_mac_start_stats,
3619 .pull_stats = efx_mcdi_mac_pull_stats,
3620 .stop_stats = efx_mcdi_mac_stop_stats,
3621 .set_id_led = efx_mcdi_set_id_led,
3622 .push_irq_moderation = efx_ef10_push_irq_moderation,
3623 .reconfigure_mac = efx_ef10_mac_reconfigure,
3624 .check_mac_fault = efx_mcdi_mac_check_fault,
3625 .reconfigure_port = efx_mcdi_port_reconfigure,
3626 .get_wol = efx_ef10_get_wol,
3627 .set_wol = efx_ef10_set_wol,
3628 .resume_wol = efx_port_dummy_op_void,
3629 .test_chip = efx_ef10_test_chip,
3630 .test_nvram = efx_mcdi_nvram_test_all,
3631 .mcdi_request = efx_ef10_mcdi_request,
3632 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
3633 .mcdi_read_response = efx_ef10_mcdi_read_response,
3634 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
3635 .irq_enable_master = efx_port_dummy_op_void,
3636 .irq_test_generate = efx_ef10_irq_test_generate,
3637 .irq_disable_non_ev = efx_port_dummy_op_void,
3638 .irq_handle_msi = efx_ef10_msi_interrupt,
3639 .irq_handle_legacy = efx_ef10_legacy_interrupt,
3640 .tx_probe = efx_ef10_tx_probe,
3641 .tx_init = efx_ef10_tx_init,
3642 .tx_remove = efx_ef10_tx_remove,
3643 .tx_write = efx_ef10_tx_write,
3644 .rx_push_rss_config = efx_ef10_rx_push_rss_config,
3645 .rx_probe = efx_ef10_rx_probe,
3646 .rx_init = efx_ef10_rx_init,
3647 .rx_remove = efx_ef10_rx_remove,
3648 .rx_write = efx_ef10_rx_write,
3649 .rx_defer_refill = efx_ef10_rx_defer_refill,
3650 .ev_probe = efx_ef10_ev_probe,
3651 .ev_init = efx_ef10_ev_init,
3652 .ev_fini = efx_ef10_ev_fini,
3653 .ev_remove = efx_ef10_ev_remove,
3654 .ev_process = efx_ef10_ev_process,
3655 .ev_read_ack = efx_ef10_ev_read_ack,
3656 .ev_test_generate = efx_ef10_ev_test_generate,
3657 .filter_table_probe = efx_ef10_filter_table_probe,
3658 .filter_table_restore = efx_ef10_filter_table_restore,
3659 .filter_table_remove = efx_ef10_filter_table_remove,
3660 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
3661 .filter_insert = efx_ef10_filter_insert,
3662 .filter_remove_safe = efx_ef10_filter_remove_safe,
3663 .filter_get_safe = efx_ef10_filter_get_safe,
3664 .filter_clear_rx = efx_ef10_filter_clear_rx,
3665 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
3666 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
3667 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
3668#ifdef CONFIG_RFS_ACCEL
3669 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
3670 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
3671#endif
3672#ifdef CONFIG_SFC_MTD
3673 .mtd_probe = efx_ef10_mtd_probe,
3674 .mtd_rename = efx_mcdi_mtd_rename,
3675 .mtd_read = efx_mcdi_mtd_read,
3676 .mtd_erase = efx_mcdi_mtd_erase,
3677 .mtd_write = efx_mcdi_mtd_write,
3678 .mtd_sync = efx_mcdi_mtd_sync,
3679#endif
3680 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
3681 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
3682 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
3683
3684 .revision = EFX_REV_HUNT_A0,
3685 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
3686 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
3687 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
3688 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
3689 .can_rx_scatter = true,
3690 .always_rx_scatter = true,
3691 .max_interrupt_mode = EFX_INT_MODE_MSIX,
3692 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
3693 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3694 NETIF_F_RXHASH | NETIF_F_NTUPLE),
3695 .mcdi_max_ver = 2,
3696 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
3697 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
3698 1 << HWTSTAMP_FILTER_ALL,
3699};