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1#include <linux/bootmem.h>
2#include <linux/linkage.h>
3#include <linux/bitops.h>
4#include <linux/kernel.h>
5#include <linux/export.h>
6#include <linux/percpu.h>
7#include <linux/string.h>
8#include <linux/ctype.h>
9#include <linux/delay.h>
10#include <linux/sched/mm.h>
11#include <linux/sched/clock.h>
12#include <linux/sched/task.h>
13#include <linux/init.h>
14#include <linux/kprobes.h>
15#include <linux/kgdb.h>
16#include <linux/smp.h>
17#include <linux/io.h>
18#include <linux/syscore_ops.h>
19
20#include <asm/stackprotector.h>
21#include <asm/perf_event.h>
22#include <asm/mmu_context.h>
23#include <asm/archrandom.h>
24#include <asm/hypervisor.h>
25#include <asm/processor.h>
26#include <asm/tlbflush.h>
27#include <asm/debugreg.h>
28#include <asm/sections.h>
29#include <asm/vsyscall.h>
30#include <linux/topology.h>
31#include <linux/cpumask.h>
32#include <asm/pgtable.h>
33#include <linux/atomic.h>
34#include <asm/proto.h>
35#include <asm/setup.h>
36#include <asm/apic.h>
37#include <asm/desc.h>
38#include <asm/fpu/internal.h>
39#include <asm/mtrr.h>
40#include <asm/hwcap2.h>
41#include <linux/numa.h>
42#include <asm/asm.h>
43#include <asm/bugs.h>
44#include <asm/cpu.h>
45#include <asm/mce.h>
46#include <asm/msr.h>
47#include <asm/pat.h>
48#include <asm/microcode.h>
49#include <asm/microcode_intel.h>
50#include <asm/intel-family.h>
51#include <asm/cpu_device_id.h>
52
53#ifdef CONFIG_X86_LOCAL_APIC
54#include <asm/uv/uv.h>
55#endif
56
57#include "cpu.h"
58
59u32 elf_hwcap2 __read_mostly;
60
61/* all of these masks are initialized in setup_cpu_local_masks() */
62cpumask_var_t cpu_initialized_mask;
63cpumask_var_t cpu_callout_mask;
64cpumask_var_t cpu_callin_mask;
65
66/* representing cpus for which sibling maps can be computed */
67cpumask_var_t cpu_sibling_setup_mask;
68
69/* correctly size the local cpu masks */
70void __init setup_cpu_local_masks(void)
71{
72 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
73 alloc_bootmem_cpumask_var(&cpu_callin_mask);
74 alloc_bootmem_cpumask_var(&cpu_callout_mask);
75 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
76}
77
78static void default_init(struct cpuinfo_x86 *c)
79{
80#ifdef CONFIG_X86_64
81 cpu_detect_cache_sizes(c);
82#else
83 /* Not much we can do here... */
84 /* Check if at least it has cpuid */
85 if (c->cpuid_level == -1) {
86 /* No cpuid. It must be an ancient CPU */
87 if (c->x86 == 4)
88 strcpy(c->x86_model_id, "486");
89 else if (c->x86 == 3)
90 strcpy(c->x86_model_id, "386");
91 }
92#endif
93}
94
95static const struct cpu_dev default_cpu = {
96 .c_init = default_init,
97 .c_vendor = "Unknown",
98 .c_x86_vendor = X86_VENDOR_UNKNOWN,
99};
100
101static const struct cpu_dev *this_cpu = &default_cpu;
102
103DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
104#ifdef CONFIG_X86_64
105 /*
106 * We need valid kernel segments for data and code in long mode too
107 * IRET will check the segment types kkeil 2000/10/28
108 * Also sysret mandates a special GDT layout
109 *
110 * TLS descriptors are currently at a different place compared to i386.
111 * Hopefully nobody expects them at a fixed place (Wine?)
112 */
113 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
114 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
115 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
116 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
117 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
118 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
119#else
120 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
121 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
122 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
123 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
124 /*
125 * Segments used for calling PnP BIOS have byte granularity.
126 * They code segments and data segments have fixed 64k limits,
127 * the transfer segment sizes are set at run time.
128 */
129 /* 32-bit code */
130 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
131 /* 16-bit code */
132 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
133 /* 16-bit data */
134 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
135 /* 16-bit data */
136 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
137 /* 16-bit data */
138 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
139 /*
140 * The APM segments have byte granularity and their bases
141 * are set at run time. All have 64k limits.
142 */
143 /* 32-bit code */
144 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
145 /* 16-bit code */
146 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
147 /* data */
148 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
149
150 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
151 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
152 GDT_STACK_CANARY_INIT
153#endif
154} };
155EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
156
157static int __init x86_mpx_setup(char *s)
158{
159 /* require an exact match without trailing characters */
160 if (strlen(s))
161 return 0;
162
163 /* do not emit a message if the feature is not present */
164 if (!boot_cpu_has(X86_FEATURE_MPX))
165 return 1;
166
167 setup_clear_cpu_cap(X86_FEATURE_MPX);
168 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
169 return 1;
170}
171__setup("nompx", x86_mpx_setup);
172
173#ifdef CONFIG_X86_64
174static int __init x86_nopcid_setup(char *s)
175{
176 /* nopcid doesn't accept parameters */
177 if (s)
178 return -EINVAL;
179
180 /* do not emit a message if the feature is not present */
181 if (!boot_cpu_has(X86_FEATURE_PCID))
182 return 0;
183
184 setup_clear_cpu_cap(X86_FEATURE_PCID);
185 pr_info("nopcid: PCID feature disabled\n");
186 return 0;
187}
188early_param("nopcid", x86_nopcid_setup);
189#endif
190
191static int __init x86_noinvpcid_setup(char *s)
192{
193 /* noinvpcid doesn't accept parameters */
194 if (s)
195 return -EINVAL;
196
197 /* do not emit a message if the feature is not present */
198 if (!boot_cpu_has(X86_FEATURE_INVPCID))
199 return 0;
200
201 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
202 pr_info("noinvpcid: INVPCID feature disabled\n");
203 return 0;
204}
205early_param("noinvpcid", x86_noinvpcid_setup);
206
207#ifdef CONFIG_X86_32
208static int cachesize_override = -1;
209static int disable_x86_serial_nr = 1;
210
211static int __init cachesize_setup(char *str)
212{
213 get_option(&str, &cachesize_override);
214 return 1;
215}
216__setup("cachesize=", cachesize_setup);
217
218static int __init x86_sep_setup(char *s)
219{
220 setup_clear_cpu_cap(X86_FEATURE_SEP);
221 return 1;
222}
223__setup("nosep", x86_sep_setup);
224
225/* Standard macro to see if a specific flag is changeable */
226static inline int flag_is_changeable_p(u32 flag)
227{
228 u32 f1, f2;
229
230 /*
231 * Cyrix and IDT cpus allow disabling of CPUID
232 * so the code below may return different results
233 * when it is executed before and after enabling
234 * the CPUID. Add "volatile" to not allow gcc to
235 * optimize the subsequent calls to this function.
236 */
237 asm volatile ("pushfl \n\t"
238 "pushfl \n\t"
239 "popl %0 \n\t"
240 "movl %0, %1 \n\t"
241 "xorl %2, %0 \n\t"
242 "pushl %0 \n\t"
243 "popfl \n\t"
244 "pushfl \n\t"
245 "popl %0 \n\t"
246 "popfl \n\t"
247
248 : "=&r" (f1), "=&r" (f2)
249 : "ir" (flag));
250
251 return ((f1^f2) & flag) != 0;
252}
253
254/* Probe for the CPUID instruction */
255int have_cpuid_p(void)
256{
257 return flag_is_changeable_p(X86_EFLAGS_ID);
258}
259
260static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
261{
262 unsigned long lo, hi;
263
264 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
265 return;
266
267 /* Disable processor serial number: */
268
269 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
270 lo |= 0x200000;
271 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
272
273 pr_notice("CPU serial number disabled.\n");
274 clear_cpu_cap(c, X86_FEATURE_PN);
275
276 /* Disabling the serial number may affect the cpuid level */
277 c->cpuid_level = cpuid_eax(0);
278}
279
280static int __init x86_serial_nr_setup(char *s)
281{
282 disable_x86_serial_nr = 0;
283 return 1;
284}
285__setup("serialnumber", x86_serial_nr_setup);
286#else
287static inline int flag_is_changeable_p(u32 flag)
288{
289 return 1;
290}
291static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
292{
293}
294#endif
295
296static __init int setup_disable_smep(char *arg)
297{
298 setup_clear_cpu_cap(X86_FEATURE_SMEP);
299 /* Check for things that depend on SMEP being enabled: */
300 check_mpx_erratum(&boot_cpu_data);
301 return 1;
302}
303__setup("nosmep", setup_disable_smep);
304
305static __always_inline void setup_smep(struct cpuinfo_x86 *c)
306{
307 if (cpu_has(c, X86_FEATURE_SMEP))
308 cr4_set_bits(X86_CR4_SMEP);
309}
310
311static __init int setup_disable_smap(char *arg)
312{
313 setup_clear_cpu_cap(X86_FEATURE_SMAP);
314 return 1;
315}
316__setup("nosmap", setup_disable_smap);
317
318static __always_inline void setup_smap(struct cpuinfo_x86 *c)
319{
320 unsigned long eflags = native_save_fl();
321
322 /* This should have been cleared long ago */
323 BUG_ON(eflags & X86_EFLAGS_AC);
324
325 if (cpu_has(c, X86_FEATURE_SMAP)) {
326#ifdef CONFIG_X86_SMAP
327 cr4_set_bits(X86_CR4_SMAP);
328#else
329 cr4_clear_bits(X86_CR4_SMAP);
330#endif
331 }
332}
333
334static __always_inline void setup_umip(struct cpuinfo_x86 *c)
335{
336 /* Check the boot processor, plus build option for UMIP. */
337 if (!cpu_feature_enabled(X86_FEATURE_UMIP))
338 goto out;
339
340 /* Check the current processor's cpuid bits. */
341 if (!cpu_has(c, X86_FEATURE_UMIP))
342 goto out;
343
344 cr4_set_bits(X86_CR4_UMIP);
345
346 pr_info("x86/cpu: Activated the Intel User Mode Instruction Prevention (UMIP) CPU feature\n");
347
348 return;
349
350out:
351 /*
352 * Make sure UMIP is disabled in case it was enabled in a
353 * previous boot (e.g., via kexec).
354 */
355 cr4_clear_bits(X86_CR4_UMIP);
356}
357
358/*
359 * Protection Keys are not available in 32-bit mode.
360 */
361static bool pku_disabled;
362
363static __always_inline void setup_pku(struct cpuinfo_x86 *c)
364{
365 /* check the boot processor, plus compile options for PKU: */
366 if (!cpu_feature_enabled(X86_FEATURE_PKU))
367 return;
368 /* checks the actual processor's cpuid bits: */
369 if (!cpu_has(c, X86_FEATURE_PKU))
370 return;
371 if (pku_disabled)
372 return;
373
374 cr4_set_bits(X86_CR4_PKE);
375 /*
376 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
377 * cpuid bit to be set. We need to ensure that we
378 * update that bit in this CPU's "cpu_info".
379 */
380 get_cpu_cap(c);
381}
382
383#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
384static __init int setup_disable_pku(char *arg)
385{
386 /*
387 * Do not clear the X86_FEATURE_PKU bit. All of the
388 * runtime checks are against OSPKE so clearing the
389 * bit does nothing.
390 *
391 * This way, we will see "pku" in cpuinfo, but not
392 * "ospke", which is exactly what we want. It shows
393 * that the CPU has PKU, but the OS has not enabled it.
394 * This happens to be exactly how a system would look
395 * if we disabled the config option.
396 */
397 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
398 pku_disabled = true;
399 return 1;
400}
401__setup("nopku", setup_disable_pku);
402#endif /* CONFIG_X86_64 */
403
404/*
405 * Some CPU features depend on higher CPUID levels, which may not always
406 * be available due to CPUID level capping or broken virtualization
407 * software. Add those features to this table to auto-disable them.
408 */
409struct cpuid_dependent_feature {
410 u32 feature;
411 u32 level;
412};
413
414static const struct cpuid_dependent_feature
415cpuid_dependent_features[] = {
416 { X86_FEATURE_MWAIT, 0x00000005 },
417 { X86_FEATURE_DCA, 0x00000009 },
418 { X86_FEATURE_XSAVE, 0x0000000d },
419 { 0, 0 }
420};
421
422static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
423{
424 const struct cpuid_dependent_feature *df;
425
426 for (df = cpuid_dependent_features; df->feature; df++) {
427
428 if (!cpu_has(c, df->feature))
429 continue;
430 /*
431 * Note: cpuid_level is set to -1 if unavailable, but
432 * extended_extended_level is set to 0 if unavailable
433 * and the legitimate extended levels are all negative
434 * when signed; hence the weird messing around with
435 * signs here...
436 */
437 if (!((s32)df->level < 0 ?
438 (u32)df->level > (u32)c->extended_cpuid_level :
439 (s32)df->level > (s32)c->cpuid_level))
440 continue;
441
442 clear_cpu_cap(c, df->feature);
443 if (!warn)
444 continue;
445
446 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
447 x86_cap_flag(df->feature), df->level);
448 }
449}
450
451/*
452 * Naming convention should be: <Name> [(<Codename>)]
453 * This table only is used unless init_<vendor>() below doesn't set it;
454 * in particular, if CPUID levels 0x80000002..4 are supported, this
455 * isn't used
456 */
457
458/* Look up CPU names by table lookup. */
459static const char *table_lookup_model(struct cpuinfo_x86 *c)
460{
461#ifdef CONFIG_X86_32
462 const struct legacy_cpu_model_info *info;
463
464 if (c->x86_model >= 16)
465 return NULL; /* Range check */
466
467 if (!this_cpu)
468 return NULL;
469
470 info = this_cpu->legacy_models;
471
472 while (info->family) {
473 if (info->family == c->x86)
474 return info->model_names[c->x86_model];
475 info++;
476 }
477#endif
478 return NULL; /* Not found */
479}
480
481__u32 cpu_caps_cleared[NCAPINTS + NBUGINTS];
482__u32 cpu_caps_set[NCAPINTS + NBUGINTS];
483
484void load_percpu_segment(int cpu)
485{
486#ifdef CONFIG_X86_32
487 loadsegment(fs, __KERNEL_PERCPU);
488#else
489 __loadsegment_simple(gs, 0);
490 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu));
491#endif
492 load_stack_canary_segment();
493}
494
495#ifdef CONFIG_X86_32
496/* The 32-bit entry code needs to find cpu_entry_area. */
497DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
498#endif
499
500#ifdef CONFIG_X86_64
501/*
502 * Special IST stacks which the CPU switches to when it calls
503 * an IST-marked descriptor entry. Up to 7 stacks (hardware
504 * limit), all of them are 4K, except the debug stack which
505 * is 8K.
506 */
507static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
508 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
509 [DEBUG_STACK - 1] = DEBUG_STKSZ
510};
511#endif
512
513/* Load the original GDT from the per-cpu structure */
514void load_direct_gdt(int cpu)
515{
516 struct desc_ptr gdt_descr;
517
518 gdt_descr.address = (long)get_cpu_gdt_rw(cpu);
519 gdt_descr.size = GDT_SIZE - 1;
520 load_gdt(&gdt_descr);
521}
522EXPORT_SYMBOL_GPL(load_direct_gdt);
523
524/* Load a fixmap remapping of the per-cpu GDT */
525void load_fixmap_gdt(int cpu)
526{
527 struct desc_ptr gdt_descr;
528
529 gdt_descr.address = (long)get_cpu_gdt_ro(cpu);
530 gdt_descr.size = GDT_SIZE - 1;
531 load_gdt(&gdt_descr);
532}
533EXPORT_SYMBOL_GPL(load_fixmap_gdt);
534
535/*
536 * Current gdt points %fs at the "master" per-cpu area: after this,
537 * it's on the real one.
538 */
539void switch_to_new_gdt(int cpu)
540{
541 /* Load the original GDT */
542 load_direct_gdt(cpu);
543 /* Reload the per-cpu base */
544 load_percpu_segment(cpu);
545}
546
547static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
548
549static void get_model_name(struct cpuinfo_x86 *c)
550{
551 unsigned int *v;
552 char *p, *q, *s;
553
554 if (c->extended_cpuid_level < 0x80000004)
555 return;
556
557 v = (unsigned int *)c->x86_model_id;
558 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
559 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
560 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
561 c->x86_model_id[48] = 0;
562
563 /* Trim whitespace */
564 p = q = s = &c->x86_model_id[0];
565
566 while (*p == ' ')
567 p++;
568
569 while (*p) {
570 /* Note the last non-whitespace index */
571 if (!isspace(*p))
572 s = q;
573
574 *q++ = *p++;
575 }
576
577 *(s + 1) = '\0';
578}
579
580void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
581{
582 unsigned int n, dummy, ebx, ecx, edx, l2size;
583
584 n = c->extended_cpuid_level;
585
586 if (n >= 0x80000005) {
587 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
588 c->x86_cache_size = (ecx>>24) + (edx>>24);
589#ifdef CONFIG_X86_64
590 /* On K8 L1 TLB is inclusive, so don't count it */
591 c->x86_tlbsize = 0;
592#endif
593 }
594
595 if (n < 0x80000006) /* Some chips just has a large L1. */
596 return;
597
598 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
599 l2size = ecx >> 16;
600
601#ifdef CONFIG_X86_64
602 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
603#else
604 /* do processor-specific cache resizing */
605 if (this_cpu->legacy_cache_size)
606 l2size = this_cpu->legacy_cache_size(c, l2size);
607
608 /* Allow user to override all this if necessary. */
609 if (cachesize_override != -1)
610 l2size = cachesize_override;
611
612 if (l2size == 0)
613 return; /* Again, no L2 cache is possible */
614#endif
615
616 c->x86_cache_size = l2size;
617}
618
619u16 __read_mostly tlb_lli_4k[NR_INFO];
620u16 __read_mostly tlb_lli_2m[NR_INFO];
621u16 __read_mostly tlb_lli_4m[NR_INFO];
622u16 __read_mostly tlb_lld_4k[NR_INFO];
623u16 __read_mostly tlb_lld_2m[NR_INFO];
624u16 __read_mostly tlb_lld_4m[NR_INFO];
625u16 __read_mostly tlb_lld_1g[NR_INFO];
626
627static void cpu_detect_tlb(struct cpuinfo_x86 *c)
628{
629 if (this_cpu->c_detect_tlb)
630 this_cpu->c_detect_tlb(c);
631
632 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
633 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
634 tlb_lli_4m[ENTRIES]);
635
636 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
637 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
638 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
639}
640
641void detect_ht(struct cpuinfo_x86 *c)
642{
643#ifdef CONFIG_SMP
644 u32 eax, ebx, ecx, edx;
645 int index_msb, core_bits;
646 static bool printed;
647
648 if (!cpu_has(c, X86_FEATURE_HT))
649 return;
650
651 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
652 goto out;
653
654 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
655 return;
656
657 cpuid(1, &eax, &ebx, &ecx, &edx);
658
659 smp_num_siblings = (ebx & 0xff0000) >> 16;
660
661 if (smp_num_siblings == 1) {
662 pr_info_once("CPU0: Hyper-Threading is disabled\n");
663 goto out;
664 }
665
666 if (smp_num_siblings <= 1)
667 goto out;
668
669 index_msb = get_count_order(smp_num_siblings);
670 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
671
672 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
673
674 index_msb = get_count_order(smp_num_siblings);
675
676 core_bits = get_count_order(c->x86_max_cores);
677
678 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
679 ((1 << core_bits) - 1);
680
681out:
682 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
683 pr_info("CPU: Physical Processor ID: %d\n",
684 c->phys_proc_id);
685 pr_info("CPU: Processor Core ID: %d\n",
686 c->cpu_core_id);
687 printed = 1;
688 }
689#endif
690}
691
692static void get_cpu_vendor(struct cpuinfo_x86 *c)
693{
694 char *v = c->x86_vendor_id;
695 int i;
696
697 for (i = 0; i < X86_VENDOR_NUM; i++) {
698 if (!cpu_devs[i])
699 break;
700
701 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
702 (cpu_devs[i]->c_ident[1] &&
703 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
704
705 this_cpu = cpu_devs[i];
706 c->x86_vendor = this_cpu->c_x86_vendor;
707 return;
708 }
709 }
710
711 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
712 "CPU: Your system may be unstable.\n", v);
713
714 c->x86_vendor = X86_VENDOR_UNKNOWN;
715 this_cpu = &default_cpu;
716}
717
718void cpu_detect(struct cpuinfo_x86 *c)
719{
720 /* Get vendor name */
721 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
722 (unsigned int *)&c->x86_vendor_id[0],
723 (unsigned int *)&c->x86_vendor_id[8],
724 (unsigned int *)&c->x86_vendor_id[4]);
725
726 c->x86 = 4;
727 /* Intel-defined flags: level 0x00000001 */
728 if (c->cpuid_level >= 0x00000001) {
729 u32 junk, tfms, cap0, misc;
730
731 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
732 c->x86 = x86_family(tfms);
733 c->x86_model = x86_model(tfms);
734 c->x86_stepping = x86_stepping(tfms);
735
736 if (cap0 & (1<<19)) {
737 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
738 c->x86_cache_alignment = c->x86_clflush_size;
739 }
740 }
741}
742
743static void apply_forced_caps(struct cpuinfo_x86 *c)
744{
745 int i;
746
747 for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
748 c->x86_capability[i] &= ~cpu_caps_cleared[i];
749 c->x86_capability[i] |= cpu_caps_set[i];
750 }
751}
752
753static void init_speculation_control(struct cpuinfo_x86 *c)
754{
755 /*
756 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
757 * and they also have a different bit for STIBP support. Also,
758 * a hypervisor might have set the individual AMD bits even on
759 * Intel CPUs, for finer-grained selection of what's available.
760 */
761 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
762 set_cpu_cap(c, X86_FEATURE_IBRS);
763 set_cpu_cap(c, X86_FEATURE_IBPB);
764 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
765 }
766
767 if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
768 set_cpu_cap(c, X86_FEATURE_STIBP);
769
770 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) ||
771 cpu_has(c, X86_FEATURE_VIRT_SSBD))
772 set_cpu_cap(c, X86_FEATURE_SSBD);
773
774 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) {
775 set_cpu_cap(c, X86_FEATURE_IBRS);
776 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
777 }
778
779 if (cpu_has(c, X86_FEATURE_AMD_IBPB))
780 set_cpu_cap(c, X86_FEATURE_IBPB);
781
782 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) {
783 set_cpu_cap(c, X86_FEATURE_STIBP);
784 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
785 }
786}
787
788void get_cpu_cap(struct cpuinfo_x86 *c)
789{
790 u32 eax, ebx, ecx, edx;
791
792 /* Intel-defined flags: level 0x00000001 */
793 if (c->cpuid_level >= 0x00000001) {
794 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
795
796 c->x86_capability[CPUID_1_ECX] = ecx;
797 c->x86_capability[CPUID_1_EDX] = edx;
798 }
799
800 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
801 if (c->cpuid_level >= 0x00000006)
802 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
803
804 /* Additional Intel-defined flags: level 0x00000007 */
805 if (c->cpuid_level >= 0x00000007) {
806 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
807 c->x86_capability[CPUID_7_0_EBX] = ebx;
808 c->x86_capability[CPUID_7_ECX] = ecx;
809 c->x86_capability[CPUID_7_EDX] = edx;
810 }
811
812 /* Extended state features: level 0x0000000d */
813 if (c->cpuid_level >= 0x0000000d) {
814 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
815
816 c->x86_capability[CPUID_D_1_EAX] = eax;
817 }
818
819 /* Additional Intel-defined flags: level 0x0000000F */
820 if (c->cpuid_level >= 0x0000000F) {
821
822 /* QoS sub-leaf, EAX=0Fh, ECX=0 */
823 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx);
824 c->x86_capability[CPUID_F_0_EDX] = edx;
825
826 if (cpu_has(c, X86_FEATURE_CQM_LLC)) {
827 /* will be overridden if occupancy monitoring exists */
828 c->x86_cache_max_rmid = ebx;
829
830 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
831 cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx);
832 c->x86_capability[CPUID_F_1_EDX] = edx;
833
834 if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) ||
835 ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) ||
836 (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) {
837 c->x86_cache_max_rmid = ecx;
838 c->x86_cache_occ_scale = ebx;
839 }
840 } else {
841 c->x86_cache_max_rmid = -1;
842 c->x86_cache_occ_scale = -1;
843 }
844 }
845
846 /* AMD-defined flags: level 0x80000001 */
847 eax = cpuid_eax(0x80000000);
848 c->extended_cpuid_level = eax;
849
850 if ((eax & 0xffff0000) == 0x80000000) {
851 if (eax >= 0x80000001) {
852 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
853
854 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
855 c->x86_capability[CPUID_8000_0001_EDX] = edx;
856 }
857 }
858
859 if (c->extended_cpuid_level >= 0x80000007) {
860 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
861
862 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
863 c->x86_power = edx;
864 }
865
866 if (c->extended_cpuid_level >= 0x80000008) {
867 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
868 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
869 }
870
871 if (c->extended_cpuid_level >= 0x8000000a)
872 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
873
874 init_scattered_cpuid_features(c);
875 init_speculation_control(c);
876
877 /*
878 * Clear/Set all flags overridden by options, after probe.
879 * This needs to happen each time we re-probe, which may happen
880 * several times during CPU initialization.
881 */
882 apply_forced_caps(c);
883}
884
885static void get_cpu_address_sizes(struct cpuinfo_x86 *c)
886{
887 u32 eax, ebx, ecx, edx;
888
889 if (c->extended_cpuid_level >= 0x80000008) {
890 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
891
892 c->x86_virt_bits = (eax >> 8) & 0xff;
893 c->x86_phys_bits = eax & 0xff;
894 }
895#ifdef CONFIG_X86_32
896 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
897 c->x86_phys_bits = 36;
898#endif
899}
900
901static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
902{
903#ifdef CONFIG_X86_32
904 int i;
905
906 /*
907 * First of all, decide if this is a 486 or higher
908 * It's a 486 if we can modify the AC flag
909 */
910 if (flag_is_changeable_p(X86_EFLAGS_AC))
911 c->x86 = 4;
912 else
913 c->x86 = 3;
914
915 for (i = 0; i < X86_VENDOR_NUM; i++)
916 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
917 c->x86_vendor_id[0] = 0;
918 cpu_devs[i]->c_identify(c);
919 if (c->x86_vendor_id[0]) {
920 get_cpu_vendor(c);
921 break;
922 }
923 }
924#endif
925}
926
927static const __initconst struct x86_cpu_id cpu_no_speculation[] = {
928 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CEDARVIEW, X86_FEATURE_ANY },
929 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CLOVERVIEW, X86_FEATURE_ANY },
930 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_LINCROFT, X86_FEATURE_ANY },
931 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PENWELL, X86_FEATURE_ANY },
932 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PINEVIEW, X86_FEATURE_ANY },
933 { X86_VENDOR_CENTAUR, 5 },
934 { X86_VENDOR_INTEL, 5 },
935 { X86_VENDOR_NSC, 5 },
936 { X86_VENDOR_ANY, 4 },
937 {}
938};
939
940static const __initconst struct x86_cpu_id cpu_no_meltdown[] = {
941 { X86_VENDOR_AMD },
942 {}
943};
944
945/* Only list CPUs which speculate but are non susceptible to SSB */
946static const __initconst struct x86_cpu_id cpu_no_spec_store_bypass[] = {
947 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT1 },
948 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT },
949 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT2 },
950 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_MERRIFIELD },
951 { X86_VENDOR_INTEL, 6, INTEL_FAM6_CORE_YONAH },
952 { X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNL },
953 { X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNM },
954 { X86_VENDOR_AMD, 0x12, },
955 { X86_VENDOR_AMD, 0x11, },
956 { X86_VENDOR_AMD, 0x10, },
957 { X86_VENDOR_AMD, 0xf, },
958 {}
959};
960
961static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
962{
963 u64 ia32_cap = 0;
964
965 if (x86_match_cpu(cpu_no_speculation))
966 return;
967
968 setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
969 setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
970
971 if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES))
972 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
973
974 if (!x86_match_cpu(cpu_no_spec_store_bypass) &&
975 !(ia32_cap & ARCH_CAP_SSB_NO))
976 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
977
978 if (x86_match_cpu(cpu_no_meltdown))
979 return;
980
981 /* Rogue Data Cache Load? No! */
982 if (ia32_cap & ARCH_CAP_RDCL_NO)
983 return;
984
985 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
986}
987
988/*
989 * Do minimum CPU detection early.
990 * Fields really needed: vendor, cpuid_level, family, model, mask,
991 * cache alignment.
992 * The others are not touched to avoid unwanted side effects.
993 *
994 * WARNING: this function is only called on the boot CPU. Don't add code
995 * here that is supposed to run on all CPUs.
996 */
997static void __init early_identify_cpu(struct cpuinfo_x86 *c)
998{
999#ifdef CONFIG_X86_64
1000 c->x86_clflush_size = 64;
1001 c->x86_phys_bits = 36;
1002 c->x86_virt_bits = 48;
1003#else
1004 c->x86_clflush_size = 32;
1005 c->x86_phys_bits = 32;
1006 c->x86_virt_bits = 32;
1007#endif
1008 c->x86_cache_alignment = c->x86_clflush_size;
1009
1010 memset(&c->x86_capability, 0, sizeof c->x86_capability);
1011 c->extended_cpuid_level = 0;
1012
1013 /* cyrix could have cpuid enabled via c_identify()*/
1014 if (have_cpuid_p()) {
1015 cpu_detect(c);
1016 get_cpu_vendor(c);
1017 get_cpu_cap(c);
1018 get_cpu_address_sizes(c);
1019 setup_force_cpu_cap(X86_FEATURE_CPUID);
1020
1021 if (this_cpu->c_early_init)
1022 this_cpu->c_early_init(c);
1023
1024 c->cpu_index = 0;
1025 filter_cpuid_features(c, false);
1026
1027 if (this_cpu->c_bsp_init)
1028 this_cpu->c_bsp_init(c);
1029 } else {
1030 identify_cpu_without_cpuid(c);
1031 setup_clear_cpu_cap(X86_FEATURE_CPUID);
1032 }
1033
1034 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
1035
1036 cpu_set_bug_bits(c);
1037
1038 fpu__init_system(c);
1039
1040#ifdef CONFIG_X86_32
1041 /*
1042 * Regardless of whether PCID is enumerated, the SDM says
1043 * that it can't be enabled in 32-bit mode.
1044 */
1045 setup_clear_cpu_cap(X86_FEATURE_PCID);
1046#endif
1047}
1048
1049void __init early_cpu_init(void)
1050{
1051 const struct cpu_dev *const *cdev;
1052 int count = 0;
1053
1054#ifdef CONFIG_PROCESSOR_SELECT
1055 pr_info("KERNEL supported cpus:\n");
1056#endif
1057
1058 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
1059 const struct cpu_dev *cpudev = *cdev;
1060
1061 if (count >= X86_VENDOR_NUM)
1062 break;
1063 cpu_devs[count] = cpudev;
1064 count++;
1065
1066#ifdef CONFIG_PROCESSOR_SELECT
1067 {
1068 unsigned int j;
1069
1070 for (j = 0; j < 2; j++) {
1071 if (!cpudev->c_ident[j])
1072 continue;
1073 pr_info(" %s %s\n", cpudev->c_vendor,
1074 cpudev->c_ident[j]);
1075 }
1076 }
1077#endif
1078 }
1079 early_identify_cpu(&boot_cpu_data);
1080}
1081
1082/*
1083 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1084 * unfortunately, that's not true in practice because of early VIA
1085 * chips and (more importantly) broken virtualizers that are not easy
1086 * to detect. In the latter case it doesn't even *fail* reliably, so
1087 * probing for it doesn't even work. Disable it completely on 32-bit
1088 * unless we can find a reliable way to detect all the broken cases.
1089 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1090 */
1091static void detect_nopl(struct cpuinfo_x86 *c)
1092{
1093#ifdef CONFIG_X86_32
1094 clear_cpu_cap(c, X86_FEATURE_NOPL);
1095#else
1096 set_cpu_cap(c, X86_FEATURE_NOPL);
1097#endif
1098}
1099
1100static void detect_null_seg_behavior(struct cpuinfo_x86 *c)
1101{
1102#ifdef CONFIG_X86_64
1103 /*
1104 * Empirically, writing zero to a segment selector on AMD does
1105 * not clear the base, whereas writing zero to a segment
1106 * selector on Intel does clear the base. Intel's behavior
1107 * allows slightly faster context switches in the common case
1108 * where GS is unused by the prev and next threads.
1109 *
1110 * Since neither vendor documents this anywhere that I can see,
1111 * detect it directly instead of hardcoding the choice by
1112 * vendor.
1113 *
1114 * I've designated AMD's behavior as the "bug" because it's
1115 * counterintuitive and less friendly.
1116 */
1117
1118 unsigned long old_base, tmp;
1119 rdmsrl(MSR_FS_BASE, old_base);
1120 wrmsrl(MSR_FS_BASE, 1);
1121 loadsegment(fs, 0);
1122 rdmsrl(MSR_FS_BASE, tmp);
1123 if (tmp != 0)
1124 set_cpu_bug(c, X86_BUG_NULL_SEG);
1125 wrmsrl(MSR_FS_BASE, old_base);
1126#endif
1127}
1128
1129static void generic_identify(struct cpuinfo_x86 *c)
1130{
1131 c->extended_cpuid_level = 0;
1132
1133 if (!have_cpuid_p())
1134 identify_cpu_without_cpuid(c);
1135
1136 /* cyrix could have cpuid enabled via c_identify()*/
1137 if (!have_cpuid_p())
1138 return;
1139
1140 cpu_detect(c);
1141
1142 get_cpu_vendor(c);
1143
1144 get_cpu_cap(c);
1145
1146 get_cpu_address_sizes(c);
1147
1148 if (c->cpuid_level >= 0x00000001) {
1149 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
1150#ifdef CONFIG_X86_32
1151# ifdef CONFIG_SMP
1152 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1153# else
1154 c->apicid = c->initial_apicid;
1155# endif
1156#endif
1157 c->phys_proc_id = c->initial_apicid;
1158 }
1159
1160 get_model_name(c); /* Default name */
1161
1162 detect_nopl(c);
1163
1164 detect_null_seg_behavior(c);
1165
1166 /*
1167 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1168 * systems that run Linux at CPL > 0 may or may not have the
1169 * issue, but, even if they have the issue, there's absolutely
1170 * nothing we can do about it because we can't use the real IRET
1171 * instruction.
1172 *
1173 * NB: For the time being, only 32-bit kernels support
1174 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1175 * whether to apply espfix using paravirt hooks. If any
1176 * non-paravirt system ever shows up that does *not* have the
1177 * ESPFIX issue, we can change this.
1178 */
1179#ifdef CONFIG_X86_32
1180# ifdef CONFIG_PARAVIRT
1181 do {
1182 extern void native_iret(void);
1183 if (pv_cpu_ops.iret == native_iret)
1184 set_cpu_bug(c, X86_BUG_ESPFIX);
1185 } while (0);
1186# else
1187 set_cpu_bug(c, X86_BUG_ESPFIX);
1188# endif
1189#endif
1190}
1191
1192static void x86_init_cache_qos(struct cpuinfo_x86 *c)
1193{
1194 /*
1195 * The heavy lifting of max_rmid and cache_occ_scale are handled
1196 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
1197 * in case CQM bits really aren't there in this CPU.
1198 */
1199 if (c != &boot_cpu_data) {
1200 boot_cpu_data.x86_cache_max_rmid =
1201 min(boot_cpu_data.x86_cache_max_rmid,
1202 c->x86_cache_max_rmid);
1203 }
1204}
1205
1206/*
1207 * Validate that ACPI/mptables have the same information about the
1208 * effective APIC id and update the package map.
1209 */
1210static void validate_apic_and_package_id(struct cpuinfo_x86 *c)
1211{
1212#ifdef CONFIG_SMP
1213 unsigned int apicid, cpu = smp_processor_id();
1214
1215 apicid = apic->cpu_present_to_apicid(cpu);
1216
1217 if (apicid != c->apicid) {
1218 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1219 cpu, apicid, c->initial_apicid);
1220 }
1221 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu));
1222#else
1223 c->logical_proc_id = 0;
1224#endif
1225}
1226
1227/*
1228 * This does the hard work of actually picking apart the CPU stuff...
1229 */
1230static void identify_cpu(struct cpuinfo_x86 *c)
1231{
1232 int i;
1233
1234 c->loops_per_jiffy = loops_per_jiffy;
1235 c->x86_cache_size = 0;
1236 c->x86_vendor = X86_VENDOR_UNKNOWN;
1237 c->x86_model = c->x86_stepping = 0; /* So far unknown... */
1238 c->x86_vendor_id[0] = '\0'; /* Unset */
1239 c->x86_model_id[0] = '\0'; /* Unset */
1240 c->x86_max_cores = 1;
1241 c->x86_coreid_bits = 0;
1242 c->cu_id = 0xff;
1243#ifdef CONFIG_X86_64
1244 c->x86_clflush_size = 64;
1245 c->x86_phys_bits = 36;
1246 c->x86_virt_bits = 48;
1247#else
1248 c->cpuid_level = -1; /* CPUID not detected */
1249 c->x86_clflush_size = 32;
1250 c->x86_phys_bits = 32;
1251 c->x86_virt_bits = 32;
1252#endif
1253 c->x86_cache_alignment = c->x86_clflush_size;
1254 memset(&c->x86_capability, 0, sizeof c->x86_capability);
1255
1256 generic_identify(c);
1257
1258 if (this_cpu->c_identify)
1259 this_cpu->c_identify(c);
1260
1261 /* Clear/Set all flags overridden by options, after probe */
1262 apply_forced_caps(c);
1263
1264#ifdef CONFIG_X86_64
1265 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1266#endif
1267
1268 /*
1269 * Vendor-specific initialization. In this section we
1270 * canonicalize the feature flags, meaning if there are
1271 * features a certain CPU supports which CPUID doesn't
1272 * tell us, CPUID claiming incorrect flags, or other bugs,
1273 * we handle them here.
1274 *
1275 * At the end of this section, c->x86_capability better
1276 * indicate the features this CPU genuinely supports!
1277 */
1278 if (this_cpu->c_init)
1279 this_cpu->c_init(c);
1280
1281 /* Disable the PN if appropriate */
1282 squash_the_stupid_serial_number(c);
1283
1284 /* Set up SMEP/SMAP/UMIP */
1285 setup_smep(c);
1286 setup_smap(c);
1287 setup_umip(c);
1288
1289 /*
1290 * The vendor-specific functions might have changed features.
1291 * Now we do "generic changes."
1292 */
1293
1294 /* Filter out anything that depends on CPUID levels we don't have */
1295 filter_cpuid_features(c, true);
1296
1297 /* If the model name is still unset, do table lookup. */
1298 if (!c->x86_model_id[0]) {
1299 const char *p;
1300 p = table_lookup_model(c);
1301 if (p)
1302 strcpy(c->x86_model_id, p);
1303 else
1304 /* Last resort... */
1305 sprintf(c->x86_model_id, "%02x/%02x",
1306 c->x86, c->x86_model);
1307 }
1308
1309#ifdef CONFIG_X86_64
1310 detect_ht(c);
1311#endif
1312
1313 x86_init_rdrand(c);
1314 x86_init_cache_qos(c);
1315 setup_pku(c);
1316
1317 /*
1318 * Clear/Set all flags overridden by options, need do it
1319 * before following smp all cpus cap AND.
1320 */
1321 apply_forced_caps(c);
1322
1323 /*
1324 * On SMP, boot_cpu_data holds the common feature set between
1325 * all CPUs; so make sure that we indicate which features are
1326 * common between the CPUs. The first time this routine gets
1327 * executed, c == &boot_cpu_data.
1328 */
1329 if (c != &boot_cpu_data) {
1330 /* AND the already accumulated flags with these */
1331 for (i = 0; i < NCAPINTS; i++)
1332 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1333
1334 /* OR, i.e. replicate the bug flags */
1335 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1336 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1337 }
1338
1339 /* Init Machine Check Exception if available. */
1340 mcheck_cpu_init(c);
1341
1342 select_idle_routine(c);
1343
1344#ifdef CONFIG_NUMA
1345 numa_add_cpu(smp_processor_id());
1346#endif
1347}
1348
1349/*
1350 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1351 * on 32-bit kernels:
1352 */
1353#ifdef CONFIG_X86_32
1354void enable_sep_cpu(void)
1355{
1356 struct tss_struct *tss;
1357 int cpu;
1358
1359 if (!boot_cpu_has(X86_FEATURE_SEP))
1360 return;
1361
1362 cpu = get_cpu();
1363 tss = &per_cpu(cpu_tss_rw, cpu);
1364
1365 /*
1366 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1367 * see the big comment in struct x86_hw_tss's definition.
1368 */
1369
1370 tss->x86_tss.ss1 = __KERNEL_CS;
1371 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1372 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0);
1373 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1374
1375 put_cpu();
1376}
1377#endif
1378
1379void __init identify_boot_cpu(void)
1380{
1381 identify_cpu(&boot_cpu_data);
1382#ifdef CONFIG_X86_32
1383 sysenter_setup();
1384 enable_sep_cpu();
1385#endif
1386 cpu_detect_tlb(&boot_cpu_data);
1387}
1388
1389void identify_secondary_cpu(struct cpuinfo_x86 *c)
1390{
1391 BUG_ON(c == &boot_cpu_data);
1392 identify_cpu(c);
1393#ifdef CONFIG_X86_32
1394 enable_sep_cpu();
1395#endif
1396 mtrr_ap_init();
1397 validate_apic_and_package_id(c);
1398 x86_spec_ctrl_setup_ap();
1399}
1400
1401static __init int setup_noclflush(char *arg)
1402{
1403 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1404 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1405 return 1;
1406}
1407__setup("noclflush", setup_noclflush);
1408
1409void print_cpu_info(struct cpuinfo_x86 *c)
1410{
1411 const char *vendor = NULL;
1412
1413 if (c->x86_vendor < X86_VENDOR_NUM) {
1414 vendor = this_cpu->c_vendor;
1415 } else {
1416 if (c->cpuid_level >= 0)
1417 vendor = c->x86_vendor_id;
1418 }
1419
1420 if (vendor && !strstr(c->x86_model_id, vendor))
1421 pr_cont("%s ", vendor);
1422
1423 if (c->x86_model_id[0])
1424 pr_cont("%s", c->x86_model_id);
1425 else
1426 pr_cont("%d86", c->x86);
1427
1428 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1429
1430 if (c->x86_stepping || c->cpuid_level >= 0)
1431 pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
1432 else
1433 pr_cont(")\n");
1434}
1435
1436/*
1437 * clearcpuid= was already parsed in fpu__init_parse_early_param.
1438 * But we need to keep a dummy __setup around otherwise it would
1439 * show up as an environment variable for init.
1440 */
1441static __init int setup_clearcpuid(char *arg)
1442{
1443 return 1;
1444}
1445__setup("clearcpuid=", setup_clearcpuid);
1446
1447#ifdef CONFIG_X86_64
1448DEFINE_PER_CPU_FIRST(union irq_stack_union,
1449 irq_stack_union) __aligned(PAGE_SIZE) __visible;
1450EXPORT_PER_CPU_SYMBOL_GPL(irq_stack_union);
1451
1452/*
1453 * The following percpu variables are hot. Align current_task to
1454 * cacheline size such that they fall in the same cacheline.
1455 */
1456DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1457 &init_task;
1458EXPORT_PER_CPU_SYMBOL(current_task);
1459
1460DEFINE_PER_CPU(char *, irq_stack_ptr) =
1461 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE;
1462
1463DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1464
1465DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1466EXPORT_PER_CPU_SYMBOL(__preempt_count);
1467
1468/* May not be marked __init: used by software suspend */
1469void syscall_init(void)
1470{
1471 extern char _entry_trampoline[];
1472 extern char entry_SYSCALL_64_trampoline[];
1473
1474 int cpu = smp_processor_id();
1475 unsigned long SYSCALL64_entry_trampoline =
1476 (unsigned long)get_cpu_entry_area(cpu)->entry_trampoline +
1477 (entry_SYSCALL_64_trampoline - _entry_trampoline);
1478
1479 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1480 if (static_cpu_has(X86_FEATURE_PTI))
1481 wrmsrl(MSR_LSTAR, SYSCALL64_entry_trampoline);
1482 else
1483 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1484
1485#ifdef CONFIG_IA32_EMULATION
1486 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1487 /*
1488 * This only works on Intel CPUs.
1489 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1490 * This does not cause SYSENTER to jump to the wrong location, because
1491 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1492 */
1493 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1494 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1));
1495 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1496#else
1497 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1498 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1499 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1500 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1501#endif
1502
1503 /* Flags to clear on syscall */
1504 wrmsrl(MSR_SYSCALL_MASK,
1505 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1506 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1507}
1508
1509/*
1510 * Copies of the original ist values from the tss are only accessed during
1511 * debugging, no special alignment required.
1512 */
1513DEFINE_PER_CPU(struct orig_ist, orig_ist);
1514
1515static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1516DEFINE_PER_CPU(int, debug_stack_usage);
1517
1518int is_debug_stack(unsigned long addr)
1519{
1520 return __this_cpu_read(debug_stack_usage) ||
1521 (addr <= __this_cpu_read(debug_stack_addr) &&
1522 addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ));
1523}
1524NOKPROBE_SYMBOL(is_debug_stack);
1525
1526DEFINE_PER_CPU(u32, debug_idt_ctr);
1527
1528void debug_stack_set_zero(void)
1529{
1530 this_cpu_inc(debug_idt_ctr);
1531 load_current_idt();
1532}
1533NOKPROBE_SYMBOL(debug_stack_set_zero);
1534
1535void debug_stack_reset(void)
1536{
1537 if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1538 return;
1539 if (this_cpu_dec_return(debug_idt_ctr) == 0)
1540 load_current_idt();
1541}
1542NOKPROBE_SYMBOL(debug_stack_reset);
1543
1544#else /* CONFIG_X86_64 */
1545
1546DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1547EXPORT_PER_CPU_SYMBOL(current_task);
1548DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1549EXPORT_PER_CPU_SYMBOL(__preempt_count);
1550
1551/*
1552 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1553 * the top of the kernel stack. Use an extra percpu variable to track the
1554 * top of the kernel stack directly.
1555 */
1556DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1557 (unsigned long)&init_thread_union + THREAD_SIZE;
1558EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1559
1560#ifdef CONFIG_CC_STACKPROTECTOR
1561DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1562#endif
1563
1564#endif /* CONFIG_X86_64 */
1565
1566/*
1567 * Clear all 6 debug registers:
1568 */
1569static void clear_all_debug_regs(void)
1570{
1571 int i;
1572
1573 for (i = 0; i < 8; i++) {
1574 /* Ignore db4, db5 */
1575 if ((i == 4) || (i == 5))
1576 continue;
1577
1578 set_debugreg(0, i);
1579 }
1580}
1581
1582#ifdef CONFIG_KGDB
1583/*
1584 * Restore debug regs if using kgdbwait and you have a kernel debugger
1585 * connection established.
1586 */
1587static void dbg_restore_debug_regs(void)
1588{
1589 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1590 arch_kgdb_ops.correct_hw_break();
1591}
1592#else /* ! CONFIG_KGDB */
1593#define dbg_restore_debug_regs()
1594#endif /* ! CONFIG_KGDB */
1595
1596static void wait_for_master_cpu(int cpu)
1597{
1598#ifdef CONFIG_SMP
1599 /*
1600 * wait for ACK from master CPU before continuing
1601 * with AP initialization
1602 */
1603 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1604 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1605 cpu_relax();
1606#endif
1607}
1608
1609/*
1610 * cpu_init() initializes state that is per-CPU. Some data is already
1611 * initialized (naturally) in the bootstrap process, such as the GDT
1612 * and IDT. We reload them nevertheless, this function acts as a
1613 * 'CPU state barrier', nothing should get across.
1614 * A lot of state is already set up in PDA init for 64 bit
1615 */
1616#ifdef CONFIG_X86_64
1617
1618void cpu_init(void)
1619{
1620 struct orig_ist *oist;
1621 struct task_struct *me;
1622 struct tss_struct *t;
1623 unsigned long v;
1624 int cpu = raw_smp_processor_id();
1625 int i;
1626
1627 wait_for_master_cpu(cpu);
1628
1629 /*
1630 * Initialize the CR4 shadow before doing anything that could
1631 * try to read it.
1632 */
1633 cr4_init_shadow();
1634
1635 if (cpu)
1636 load_ucode_ap();
1637
1638 t = &per_cpu(cpu_tss_rw, cpu);
1639 oist = &per_cpu(orig_ist, cpu);
1640
1641#ifdef CONFIG_NUMA
1642 if (this_cpu_read(numa_node) == 0 &&
1643 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1644 set_numa_node(early_cpu_to_node(cpu));
1645#endif
1646
1647 me = current;
1648
1649 pr_debug("Initializing CPU#%d\n", cpu);
1650
1651 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1652
1653 /*
1654 * Initialize the per-CPU GDT with the boot GDT,
1655 * and set up the GDT descriptor:
1656 */
1657
1658 switch_to_new_gdt(cpu);
1659 loadsegment(fs, 0);
1660
1661 load_current_idt();
1662
1663 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1664 syscall_init();
1665
1666 wrmsrl(MSR_FS_BASE, 0);
1667 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1668 barrier();
1669
1670 x86_configure_nx();
1671 x2apic_setup();
1672
1673 /*
1674 * set up and load the per-CPU TSS
1675 */
1676 if (!oist->ist[0]) {
1677 char *estacks = get_cpu_entry_area(cpu)->exception_stacks;
1678
1679 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1680 estacks += exception_stack_sizes[v];
1681 oist->ist[v] = t->x86_tss.ist[v] =
1682 (unsigned long)estacks;
1683 if (v == DEBUG_STACK-1)
1684 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1685 }
1686 }
1687
1688 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET;
1689
1690 /*
1691 * <= is required because the CPU will access up to
1692 * 8 bits beyond the end of the IO permission bitmap.
1693 */
1694 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1695 t->io_bitmap[i] = ~0UL;
1696
1697 mmgrab(&init_mm);
1698 me->active_mm = &init_mm;
1699 BUG_ON(me->mm);
1700 initialize_tlbstate_and_flush();
1701 enter_lazy_tlb(&init_mm, me);
1702
1703 /*
1704 * Initialize the TSS. sp0 points to the entry trampoline stack
1705 * regardless of what task is running.
1706 */
1707 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
1708 load_TR_desc();
1709 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
1710
1711 load_mm_ldt(&init_mm);
1712
1713 clear_all_debug_regs();
1714 dbg_restore_debug_regs();
1715
1716 fpu__init_cpu();
1717
1718 if (is_uv_system())
1719 uv_cpu_init();
1720
1721 load_fixmap_gdt(cpu);
1722}
1723
1724#else
1725
1726void cpu_init(void)
1727{
1728 int cpu = smp_processor_id();
1729 struct task_struct *curr = current;
1730 struct tss_struct *t = &per_cpu(cpu_tss_rw, cpu);
1731
1732 wait_for_master_cpu(cpu);
1733
1734 /*
1735 * Initialize the CR4 shadow before doing anything that could
1736 * try to read it.
1737 */
1738 cr4_init_shadow();
1739
1740 show_ucode_info_early();
1741
1742 pr_info("Initializing CPU#%d\n", cpu);
1743
1744 if (cpu_feature_enabled(X86_FEATURE_VME) ||
1745 boot_cpu_has(X86_FEATURE_TSC) ||
1746 boot_cpu_has(X86_FEATURE_DE))
1747 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1748
1749 load_current_idt();
1750 switch_to_new_gdt(cpu);
1751
1752 /*
1753 * Set up and load the per-CPU TSS and LDT
1754 */
1755 mmgrab(&init_mm);
1756 curr->active_mm = &init_mm;
1757 BUG_ON(curr->mm);
1758 initialize_tlbstate_and_flush();
1759 enter_lazy_tlb(&init_mm, curr);
1760
1761 /*
1762 * Initialize the TSS. Don't bother initializing sp0, as the initial
1763 * task never enters user mode.
1764 */
1765 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
1766 load_TR_desc();
1767
1768 load_mm_ldt(&init_mm);
1769
1770 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET;
1771
1772#ifdef CONFIG_DOUBLEFAULT
1773 /* Set up doublefault TSS pointer in the GDT */
1774 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1775#endif
1776
1777 clear_all_debug_regs();
1778 dbg_restore_debug_regs();
1779
1780 fpu__init_cpu();
1781
1782 load_fixmap_gdt(cpu);
1783}
1784#endif
1785
1786static void bsp_resume(void)
1787{
1788 if (this_cpu->c_bsp_resume)
1789 this_cpu->c_bsp_resume(&boot_cpu_data);
1790}
1791
1792static struct syscore_ops cpu_syscore_ops = {
1793 .resume = bsp_resume,
1794};
1795
1796static int __init init_cpu_syscore(void)
1797{
1798 register_syscore_ops(&cpu_syscore_ops);
1799 return 0;
1800}
1801core_initcall(init_cpu_syscore);
1802
1803/*
1804 * The microcode loader calls this upon late microcode load to recheck features,
1805 * only when microcode has been updated. Caller holds microcode_mutex and CPU
1806 * hotplug lock.
1807 */
1808void microcode_check(void)
1809{
1810 struct cpuinfo_x86 info;
1811
1812 perf_check_microcode();
1813
1814 /* Reload CPUID max function as it might've changed. */
1815 info.cpuid_level = cpuid_eax(0);
1816
1817 /*
1818 * Copy all capability leafs to pick up the synthetic ones so that
1819 * memcmp() below doesn't fail on that. The ones coming from CPUID will
1820 * get overwritten in get_cpu_cap().
1821 */
1822 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability));
1823
1824 get_cpu_cap(&info);
1825
1826 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)))
1827 return;
1828
1829 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
1830 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
1831}
1#include <linux/bootmem.h>
2#include <linux/linkage.h>
3#include <linux/bitops.h>
4#include <linux/kernel.h>
5#include <linux/module.h>
6#include <linux/percpu.h>
7#include <linux/string.h>
8#include <linux/delay.h>
9#include <linux/sched.h>
10#include <linux/init.h>
11#include <linux/kgdb.h>
12#include <linux/smp.h>
13#include <linux/io.h>
14
15#include <asm/stackprotector.h>
16#include <asm/perf_event.h>
17#include <asm/mmu_context.h>
18#include <asm/archrandom.h>
19#include <asm/hypervisor.h>
20#include <asm/processor.h>
21#include <asm/debugreg.h>
22#include <asm/sections.h>
23#include <linux/topology.h>
24#include <linux/cpumask.h>
25#include <asm/pgtable.h>
26#include <linux/atomic.h>
27#include <asm/proto.h>
28#include <asm/setup.h>
29#include <asm/apic.h>
30#include <asm/desc.h>
31#include <asm/i387.h>
32#include <asm/fpu-internal.h>
33#include <asm/mtrr.h>
34#include <linux/numa.h>
35#include <asm/asm.h>
36#include <asm/cpu.h>
37#include <asm/mce.h>
38#include <asm/msr.h>
39#include <asm/pat.h>
40#include <asm/microcode.h>
41#include <asm/microcode_intel.h>
42
43#ifdef CONFIG_X86_LOCAL_APIC
44#include <asm/uv/uv.h>
45#endif
46
47#include "cpu.h"
48
49/* all of these masks are initialized in setup_cpu_local_masks() */
50cpumask_var_t cpu_initialized_mask;
51cpumask_var_t cpu_callout_mask;
52cpumask_var_t cpu_callin_mask;
53
54/* representing cpus for which sibling maps can be computed */
55cpumask_var_t cpu_sibling_setup_mask;
56
57/* correctly size the local cpu masks */
58void __init setup_cpu_local_masks(void)
59{
60 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
61 alloc_bootmem_cpumask_var(&cpu_callin_mask);
62 alloc_bootmem_cpumask_var(&cpu_callout_mask);
63 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
64}
65
66static void default_init(struct cpuinfo_x86 *c)
67{
68#ifdef CONFIG_X86_64
69 cpu_detect_cache_sizes(c);
70#else
71 /* Not much we can do here... */
72 /* Check if at least it has cpuid */
73 if (c->cpuid_level == -1) {
74 /* No cpuid. It must be an ancient CPU */
75 if (c->x86 == 4)
76 strcpy(c->x86_model_id, "486");
77 else if (c->x86 == 3)
78 strcpy(c->x86_model_id, "386");
79 }
80#endif
81}
82
83static const struct cpu_dev default_cpu = {
84 .c_init = default_init,
85 .c_vendor = "Unknown",
86 .c_x86_vendor = X86_VENDOR_UNKNOWN,
87};
88
89static const struct cpu_dev *this_cpu = &default_cpu;
90
91DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
92#ifdef CONFIG_X86_64
93 /*
94 * We need valid kernel segments for data and code in long mode too
95 * IRET will check the segment types kkeil 2000/10/28
96 * Also sysret mandates a special GDT layout
97 *
98 * TLS descriptors are currently at a different place compared to i386.
99 * Hopefully nobody expects them at a fixed place (Wine?)
100 */
101 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
102 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
103 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
104 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
105 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
106 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
107#else
108 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
109 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
110 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
111 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
112 /*
113 * Segments used for calling PnP BIOS have byte granularity.
114 * They code segments and data segments have fixed 64k limits,
115 * the transfer segment sizes are set at run time.
116 */
117 /* 32-bit code */
118 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
119 /* 16-bit code */
120 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
121 /* 16-bit data */
122 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
123 /* 16-bit data */
124 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
125 /* 16-bit data */
126 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
127 /*
128 * The APM segments have byte granularity and their bases
129 * are set at run time. All have 64k limits.
130 */
131 /* 32-bit code */
132 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
133 /* 16-bit code */
134 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
135 /* data */
136 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
137
138 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
139 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
140 GDT_STACK_CANARY_INIT
141#endif
142} };
143EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
144
145static int __init x86_xsave_setup(char *s)
146{
147 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
148 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
149 setup_clear_cpu_cap(X86_FEATURE_AVX);
150 setup_clear_cpu_cap(X86_FEATURE_AVX2);
151 return 1;
152}
153__setup("noxsave", x86_xsave_setup);
154
155static int __init x86_xsaveopt_setup(char *s)
156{
157 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
158 return 1;
159}
160__setup("noxsaveopt", x86_xsaveopt_setup);
161
162#ifdef CONFIG_X86_32
163static int cachesize_override = -1;
164static int disable_x86_serial_nr = 1;
165
166static int __init cachesize_setup(char *str)
167{
168 get_option(&str, &cachesize_override);
169 return 1;
170}
171__setup("cachesize=", cachesize_setup);
172
173static int __init x86_fxsr_setup(char *s)
174{
175 setup_clear_cpu_cap(X86_FEATURE_FXSR);
176 setup_clear_cpu_cap(X86_FEATURE_XMM);
177 return 1;
178}
179__setup("nofxsr", x86_fxsr_setup);
180
181static int __init x86_sep_setup(char *s)
182{
183 setup_clear_cpu_cap(X86_FEATURE_SEP);
184 return 1;
185}
186__setup("nosep", x86_sep_setup);
187
188/* Standard macro to see if a specific flag is changeable */
189static inline int flag_is_changeable_p(u32 flag)
190{
191 u32 f1, f2;
192
193 /*
194 * Cyrix and IDT cpus allow disabling of CPUID
195 * so the code below may return different results
196 * when it is executed before and after enabling
197 * the CPUID. Add "volatile" to not allow gcc to
198 * optimize the subsequent calls to this function.
199 */
200 asm volatile ("pushfl \n\t"
201 "pushfl \n\t"
202 "popl %0 \n\t"
203 "movl %0, %1 \n\t"
204 "xorl %2, %0 \n\t"
205 "pushl %0 \n\t"
206 "popfl \n\t"
207 "pushfl \n\t"
208 "popl %0 \n\t"
209 "popfl \n\t"
210
211 : "=&r" (f1), "=&r" (f2)
212 : "ir" (flag));
213
214 return ((f1^f2) & flag) != 0;
215}
216
217/* Probe for the CPUID instruction */
218int have_cpuid_p(void)
219{
220 return flag_is_changeable_p(X86_EFLAGS_ID);
221}
222
223static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
224{
225 unsigned long lo, hi;
226
227 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
228 return;
229
230 /* Disable processor serial number: */
231
232 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
233 lo |= 0x200000;
234 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
235
236 printk(KERN_NOTICE "CPU serial number disabled.\n");
237 clear_cpu_cap(c, X86_FEATURE_PN);
238
239 /* Disabling the serial number may affect the cpuid level */
240 c->cpuid_level = cpuid_eax(0);
241}
242
243static int __init x86_serial_nr_setup(char *s)
244{
245 disable_x86_serial_nr = 0;
246 return 1;
247}
248__setup("serialnumber", x86_serial_nr_setup);
249#else
250static inline int flag_is_changeable_p(u32 flag)
251{
252 return 1;
253}
254static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
255{
256}
257#endif
258
259static __init int setup_disable_smep(char *arg)
260{
261 setup_clear_cpu_cap(X86_FEATURE_SMEP);
262 return 1;
263}
264__setup("nosmep", setup_disable_smep);
265
266static __always_inline void setup_smep(struct cpuinfo_x86 *c)
267{
268 if (cpu_has(c, X86_FEATURE_SMEP))
269 set_in_cr4(X86_CR4_SMEP);
270}
271
272static __init int setup_disable_smap(char *arg)
273{
274 setup_clear_cpu_cap(X86_FEATURE_SMAP);
275 return 1;
276}
277__setup("nosmap", setup_disable_smap);
278
279static __always_inline void setup_smap(struct cpuinfo_x86 *c)
280{
281 unsigned long eflags;
282
283 /* This should have been cleared long ago */
284 raw_local_save_flags(eflags);
285 BUG_ON(eflags & X86_EFLAGS_AC);
286
287 if (cpu_has(c, X86_FEATURE_SMAP)) {
288#ifdef CONFIG_X86_SMAP
289 set_in_cr4(X86_CR4_SMAP);
290#else
291 clear_in_cr4(X86_CR4_SMAP);
292#endif
293 }
294}
295
296/*
297 * Some CPU features depend on higher CPUID levels, which may not always
298 * be available due to CPUID level capping or broken virtualization
299 * software. Add those features to this table to auto-disable them.
300 */
301struct cpuid_dependent_feature {
302 u32 feature;
303 u32 level;
304};
305
306static const struct cpuid_dependent_feature
307cpuid_dependent_features[] = {
308 { X86_FEATURE_MWAIT, 0x00000005 },
309 { X86_FEATURE_DCA, 0x00000009 },
310 { X86_FEATURE_XSAVE, 0x0000000d },
311 { 0, 0 }
312};
313
314static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
315{
316 const struct cpuid_dependent_feature *df;
317
318 for (df = cpuid_dependent_features; df->feature; df++) {
319
320 if (!cpu_has(c, df->feature))
321 continue;
322 /*
323 * Note: cpuid_level is set to -1 if unavailable, but
324 * extended_extended_level is set to 0 if unavailable
325 * and the legitimate extended levels are all negative
326 * when signed; hence the weird messing around with
327 * signs here...
328 */
329 if (!((s32)df->level < 0 ?
330 (u32)df->level > (u32)c->extended_cpuid_level :
331 (s32)df->level > (s32)c->cpuid_level))
332 continue;
333
334 clear_cpu_cap(c, df->feature);
335 if (!warn)
336 continue;
337
338 printk(KERN_WARNING
339 "CPU: CPU feature %s disabled, no CPUID level 0x%x\n",
340 x86_cap_flags[df->feature], df->level);
341 }
342}
343
344/*
345 * Naming convention should be: <Name> [(<Codename>)]
346 * This table only is used unless init_<vendor>() below doesn't set it;
347 * in particular, if CPUID levels 0x80000002..4 are supported, this
348 * isn't used
349 */
350
351/* Look up CPU names by table lookup. */
352static const char *table_lookup_model(struct cpuinfo_x86 *c)
353{
354#ifdef CONFIG_X86_32
355 const struct legacy_cpu_model_info *info;
356
357 if (c->x86_model >= 16)
358 return NULL; /* Range check */
359
360 if (!this_cpu)
361 return NULL;
362
363 info = this_cpu->legacy_models;
364
365 while (info->family) {
366 if (info->family == c->x86)
367 return info->model_names[c->x86_model];
368 info++;
369 }
370#endif
371 return NULL; /* Not found */
372}
373
374__u32 cpu_caps_cleared[NCAPINTS];
375__u32 cpu_caps_set[NCAPINTS];
376
377void load_percpu_segment(int cpu)
378{
379#ifdef CONFIG_X86_32
380 loadsegment(fs, __KERNEL_PERCPU);
381#else
382 loadsegment(gs, 0);
383 wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
384#endif
385 load_stack_canary_segment();
386}
387
388/*
389 * Current gdt points %fs at the "master" per-cpu area: after this,
390 * it's on the real one.
391 */
392void switch_to_new_gdt(int cpu)
393{
394 struct desc_ptr gdt_descr;
395
396 gdt_descr.address = (long)get_cpu_gdt_table(cpu);
397 gdt_descr.size = GDT_SIZE - 1;
398 load_gdt(&gdt_descr);
399 /* Reload the per-cpu base */
400
401 load_percpu_segment(cpu);
402}
403
404static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
405
406static void get_model_name(struct cpuinfo_x86 *c)
407{
408 unsigned int *v;
409 char *p, *q;
410
411 if (c->extended_cpuid_level < 0x80000004)
412 return;
413
414 v = (unsigned int *)c->x86_model_id;
415 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
416 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
417 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
418 c->x86_model_id[48] = 0;
419
420 /*
421 * Intel chips right-justify this string for some dumb reason;
422 * undo that brain damage:
423 */
424 p = q = &c->x86_model_id[0];
425 while (*p == ' ')
426 p++;
427 if (p != q) {
428 while (*p)
429 *q++ = *p++;
430 while (q <= &c->x86_model_id[48])
431 *q++ = '\0'; /* Zero-pad the rest */
432 }
433}
434
435void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
436{
437 unsigned int n, dummy, ebx, ecx, edx, l2size;
438
439 n = c->extended_cpuid_level;
440
441 if (n >= 0x80000005) {
442 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
443 c->x86_cache_size = (ecx>>24) + (edx>>24);
444#ifdef CONFIG_X86_64
445 /* On K8 L1 TLB is inclusive, so don't count it */
446 c->x86_tlbsize = 0;
447#endif
448 }
449
450 if (n < 0x80000006) /* Some chips just has a large L1. */
451 return;
452
453 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
454 l2size = ecx >> 16;
455
456#ifdef CONFIG_X86_64
457 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
458#else
459 /* do processor-specific cache resizing */
460 if (this_cpu->legacy_cache_size)
461 l2size = this_cpu->legacy_cache_size(c, l2size);
462
463 /* Allow user to override all this if necessary. */
464 if (cachesize_override != -1)
465 l2size = cachesize_override;
466
467 if (l2size == 0)
468 return; /* Again, no L2 cache is possible */
469#endif
470
471 c->x86_cache_size = l2size;
472}
473
474u16 __read_mostly tlb_lli_4k[NR_INFO];
475u16 __read_mostly tlb_lli_2m[NR_INFO];
476u16 __read_mostly tlb_lli_4m[NR_INFO];
477u16 __read_mostly tlb_lld_4k[NR_INFO];
478u16 __read_mostly tlb_lld_2m[NR_INFO];
479u16 __read_mostly tlb_lld_4m[NR_INFO];
480u16 __read_mostly tlb_lld_1g[NR_INFO];
481
482/*
483 * tlb_flushall_shift shows the balance point in replacing cr3 write
484 * with multiple 'invlpg'. It will do this replacement when
485 * flush_tlb_lines <= active_lines/2^tlb_flushall_shift.
486 * If tlb_flushall_shift is -1, means the replacement will be disabled.
487 */
488s8 __read_mostly tlb_flushall_shift = -1;
489
490void cpu_detect_tlb(struct cpuinfo_x86 *c)
491{
492 if (this_cpu->c_detect_tlb)
493 this_cpu->c_detect_tlb(c);
494
495 printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n"
496 "Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n"
497 "tlb_flushall_shift: %d\n",
498 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
499 tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES],
500 tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES],
501 tlb_lld_1g[ENTRIES], tlb_flushall_shift);
502}
503
504void detect_ht(struct cpuinfo_x86 *c)
505{
506#ifdef CONFIG_X86_HT
507 u32 eax, ebx, ecx, edx;
508 int index_msb, core_bits;
509 static bool printed;
510
511 if (!cpu_has(c, X86_FEATURE_HT))
512 return;
513
514 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
515 goto out;
516
517 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
518 return;
519
520 cpuid(1, &eax, &ebx, &ecx, &edx);
521
522 smp_num_siblings = (ebx & 0xff0000) >> 16;
523
524 if (smp_num_siblings == 1) {
525 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n");
526 goto out;
527 }
528
529 if (smp_num_siblings <= 1)
530 goto out;
531
532 index_msb = get_count_order(smp_num_siblings);
533 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
534
535 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
536
537 index_msb = get_count_order(smp_num_siblings);
538
539 core_bits = get_count_order(c->x86_max_cores);
540
541 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
542 ((1 << core_bits) - 1);
543
544out:
545 if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
546 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
547 c->phys_proc_id);
548 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
549 c->cpu_core_id);
550 printed = 1;
551 }
552#endif
553}
554
555static void get_cpu_vendor(struct cpuinfo_x86 *c)
556{
557 char *v = c->x86_vendor_id;
558 int i;
559
560 for (i = 0; i < X86_VENDOR_NUM; i++) {
561 if (!cpu_devs[i])
562 break;
563
564 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
565 (cpu_devs[i]->c_ident[1] &&
566 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
567
568 this_cpu = cpu_devs[i];
569 c->x86_vendor = this_cpu->c_x86_vendor;
570 return;
571 }
572 }
573
574 printk_once(KERN_ERR
575 "CPU: vendor_id '%s' unknown, using generic init.\n" \
576 "CPU: Your system may be unstable.\n", v);
577
578 c->x86_vendor = X86_VENDOR_UNKNOWN;
579 this_cpu = &default_cpu;
580}
581
582void cpu_detect(struct cpuinfo_x86 *c)
583{
584 /* Get vendor name */
585 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
586 (unsigned int *)&c->x86_vendor_id[0],
587 (unsigned int *)&c->x86_vendor_id[8],
588 (unsigned int *)&c->x86_vendor_id[4]);
589
590 c->x86 = 4;
591 /* Intel-defined flags: level 0x00000001 */
592 if (c->cpuid_level >= 0x00000001) {
593 u32 junk, tfms, cap0, misc;
594
595 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
596 c->x86 = (tfms >> 8) & 0xf;
597 c->x86_model = (tfms >> 4) & 0xf;
598 c->x86_mask = tfms & 0xf;
599
600 if (c->x86 == 0xf)
601 c->x86 += (tfms >> 20) & 0xff;
602 if (c->x86 >= 0x6)
603 c->x86_model += ((tfms >> 16) & 0xf) << 4;
604
605 if (cap0 & (1<<19)) {
606 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
607 c->x86_cache_alignment = c->x86_clflush_size;
608 }
609 }
610}
611
612void get_cpu_cap(struct cpuinfo_x86 *c)
613{
614 u32 tfms, xlvl;
615 u32 ebx;
616
617 /* Intel-defined flags: level 0x00000001 */
618 if (c->cpuid_level >= 0x00000001) {
619 u32 capability, excap;
620
621 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
622 c->x86_capability[0] = capability;
623 c->x86_capability[4] = excap;
624 }
625
626 /* Additional Intel-defined flags: level 0x00000007 */
627 if (c->cpuid_level >= 0x00000007) {
628 u32 eax, ebx, ecx, edx;
629
630 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
631
632 c->x86_capability[9] = ebx;
633 }
634
635 /* AMD-defined flags: level 0x80000001 */
636 xlvl = cpuid_eax(0x80000000);
637 c->extended_cpuid_level = xlvl;
638
639 if ((xlvl & 0xffff0000) == 0x80000000) {
640 if (xlvl >= 0x80000001) {
641 c->x86_capability[1] = cpuid_edx(0x80000001);
642 c->x86_capability[6] = cpuid_ecx(0x80000001);
643 }
644 }
645
646 if (c->extended_cpuid_level >= 0x80000008) {
647 u32 eax = cpuid_eax(0x80000008);
648
649 c->x86_virt_bits = (eax >> 8) & 0xff;
650 c->x86_phys_bits = eax & 0xff;
651 }
652#ifdef CONFIG_X86_32
653 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
654 c->x86_phys_bits = 36;
655#endif
656
657 if (c->extended_cpuid_level >= 0x80000007)
658 c->x86_power = cpuid_edx(0x80000007);
659
660 init_scattered_cpuid_features(c);
661}
662
663static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
664{
665#ifdef CONFIG_X86_32
666 int i;
667
668 /*
669 * First of all, decide if this is a 486 or higher
670 * It's a 486 if we can modify the AC flag
671 */
672 if (flag_is_changeable_p(X86_EFLAGS_AC))
673 c->x86 = 4;
674 else
675 c->x86 = 3;
676
677 for (i = 0; i < X86_VENDOR_NUM; i++)
678 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
679 c->x86_vendor_id[0] = 0;
680 cpu_devs[i]->c_identify(c);
681 if (c->x86_vendor_id[0]) {
682 get_cpu_vendor(c);
683 break;
684 }
685 }
686#endif
687}
688
689/*
690 * Do minimum CPU detection early.
691 * Fields really needed: vendor, cpuid_level, family, model, mask,
692 * cache alignment.
693 * The others are not touched to avoid unwanted side effects.
694 *
695 * WARNING: this function is only called on the BP. Don't add code here
696 * that is supposed to run on all CPUs.
697 */
698static void __init early_identify_cpu(struct cpuinfo_x86 *c)
699{
700#ifdef CONFIG_X86_64
701 c->x86_clflush_size = 64;
702 c->x86_phys_bits = 36;
703 c->x86_virt_bits = 48;
704#else
705 c->x86_clflush_size = 32;
706 c->x86_phys_bits = 32;
707 c->x86_virt_bits = 32;
708#endif
709 c->x86_cache_alignment = c->x86_clflush_size;
710
711 memset(&c->x86_capability, 0, sizeof c->x86_capability);
712 c->extended_cpuid_level = 0;
713
714 if (!have_cpuid_p())
715 identify_cpu_without_cpuid(c);
716
717 /* cyrix could have cpuid enabled via c_identify()*/
718 if (!have_cpuid_p())
719 return;
720
721 cpu_detect(c);
722 get_cpu_vendor(c);
723 get_cpu_cap(c);
724 fpu_detect(c);
725
726 if (this_cpu->c_early_init)
727 this_cpu->c_early_init(c);
728
729 c->cpu_index = 0;
730 filter_cpuid_features(c, false);
731
732 if (this_cpu->c_bsp_init)
733 this_cpu->c_bsp_init(c);
734
735 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
736}
737
738void __init early_cpu_init(void)
739{
740 const struct cpu_dev *const *cdev;
741 int count = 0;
742
743#ifdef CONFIG_PROCESSOR_SELECT
744 printk(KERN_INFO "KERNEL supported cpus:\n");
745#endif
746
747 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
748 const struct cpu_dev *cpudev = *cdev;
749
750 if (count >= X86_VENDOR_NUM)
751 break;
752 cpu_devs[count] = cpudev;
753 count++;
754
755#ifdef CONFIG_PROCESSOR_SELECT
756 {
757 unsigned int j;
758
759 for (j = 0; j < 2; j++) {
760 if (!cpudev->c_ident[j])
761 continue;
762 printk(KERN_INFO " %s %s\n", cpudev->c_vendor,
763 cpudev->c_ident[j]);
764 }
765 }
766#endif
767 }
768 early_identify_cpu(&boot_cpu_data);
769}
770
771/*
772 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
773 * unfortunately, that's not true in practice because of early VIA
774 * chips and (more importantly) broken virtualizers that are not easy
775 * to detect. In the latter case it doesn't even *fail* reliably, so
776 * probing for it doesn't even work. Disable it completely on 32-bit
777 * unless we can find a reliable way to detect all the broken cases.
778 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
779 */
780static void detect_nopl(struct cpuinfo_x86 *c)
781{
782#ifdef CONFIG_X86_32
783 clear_cpu_cap(c, X86_FEATURE_NOPL);
784#else
785 set_cpu_cap(c, X86_FEATURE_NOPL);
786#endif
787}
788
789static void generic_identify(struct cpuinfo_x86 *c)
790{
791 c->extended_cpuid_level = 0;
792
793 if (!have_cpuid_p())
794 identify_cpu_without_cpuid(c);
795
796 /* cyrix could have cpuid enabled via c_identify()*/
797 if (!have_cpuid_p())
798 return;
799
800 cpu_detect(c);
801
802 get_cpu_vendor(c);
803
804 get_cpu_cap(c);
805
806 if (c->cpuid_level >= 0x00000001) {
807 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
808#ifdef CONFIG_X86_32
809# ifdef CONFIG_X86_HT
810 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
811# else
812 c->apicid = c->initial_apicid;
813# endif
814#endif
815 c->phys_proc_id = c->initial_apicid;
816 }
817
818 get_model_name(c); /* Default name */
819
820 detect_nopl(c);
821}
822
823/*
824 * This does the hard work of actually picking apart the CPU stuff...
825 */
826static void identify_cpu(struct cpuinfo_x86 *c)
827{
828 int i;
829
830 c->loops_per_jiffy = loops_per_jiffy;
831 c->x86_cache_size = -1;
832 c->x86_vendor = X86_VENDOR_UNKNOWN;
833 c->x86_model = c->x86_mask = 0; /* So far unknown... */
834 c->x86_vendor_id[0] = '\0'; /* Unset */
835 c->x86_model_id[0] = '\0'; /* Unset */
836 c->x86_max_cores = 1;
837 c->x86_coreid_bits = 0;
838#ifdef CONFIG_X86_64
839 c->x86_clflush_size = 64;
840 c->x86_phys_bits = 36;
841 c->x86_virt_bits = 48;
842#else
843 c->cpuid_level = -1; /* CPUID not detected */
844 c->x86_clflush_size = 32;
845 c->x86_phys_bits = 32;
846 c->x86_virt_bits = 32;
847#endif
848 c->x86_cache_alignment = c->x86_clflush_size;
849 memset(&c->x86_capability, 0, sizeof c->x86_capability);
850
851 generic_identify(c);
852
853 if (this_cpu->c_identify)
854 this_cpu->c_identify(c);
855
856 /* Clear/Set all flags overriden by options, after probe */
857 for (i = 0; i < NCAPINTS; i++) {
858 c->x86_capability[i] &= ~cpu_caps_cleared[i];
859 c->x86_capability[i] |= cpu_caps_set[i];
860 }
861
862#ifdef CONFIG_X86_64
863 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
864#endif
865
866 /*
867 * Vendor-specific initialization. In this section we
868 * canonicalize the feature flags, meaning if there are
869 * features a certain CPU supports which CPUID doesn't
870 * tell us, CPUID claiming incorrect flags, or other bugs,
871 * we handle them here.
872 *
873 * At the end of this section, c->x86_capability better
874 * indicate the features this CPU genuinely supports!
875 */
876 if (this_cpu->c_init)
877 this_cpu->c_init(c);
878
879 /* Disable the PN if appropriate */
880 squash_the_stupid_serial_number(c);
881
882 /* Set up SMEP/SMAP */
883 setup_smep(c);
884 setup_smap(c);
885
886 /*
887 * The vendor-specific functions might have changed features.
888 * Now we do "generic changes."
889 */
890
891 /* Filter out anything that depends on CPUID levels we don't have */
892 filter_cpuid_features(c, true);
893
894 /* If the model name is still unset, do table lookup. */
895 if (!c->x86_model_id[0]) {
896 const char *p;
897 p = table_lookup_model(c);
898 if (p)
899 strcpy(c->x86_model_id, p);
900 else
901 /* Last resort... */
902 sprintf(c->x86_model_id, "%02x/%02x",
903 c->x86, c->x86_model);
904 }
905
906#ifdef CONFIG_X86_64
907 detect_ht(c);
908#endif
909
910 init_hypervisor(c);
911 x86_init_rdrand(c);
912
913 /*
914 * Clear/Set all flags overriden by options, need do it
915 * before following smp all cpus cap AND.
916 */
917 for (i = 0; i < NCAPINTS; i++) {
918 c->x86_capability[i] &= ~cpu_caps_cleared[i];
919 c->x86_capability[i] |= cpu_caps_set[i];
920 }
921
922 /*
923 * On SMP, boot_cpu_data holds the common feature set between
924 * all CPUs; so make sure that we indicate which features are
925 * common between the CPUs. The first time this routine gets
926 * executed, c == &boot_cpu_data.
927 */
928 if (c != &boot_cpu_data) {
929 /* AND the already accumulated flags with these */
930 for (i = 0; i < NCAPINTS; i++)
931 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
932
933 /* OR, i.e. replicate the bug flags */
934 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
935 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
936 }
937
938 /* Init Machine Check Exception if available. */
939 mcheck_cpu_init(c);
940
941 select_idle_routine(c);
942
943#ifdef CONFIG_NUMA
944 numa_add_cpu(smp_processor_id());
945#endif
946}
947
948#ifdef CONFIG_X86_64
949static void vgetcpu_set_mode(void)
950{
951 if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP))
952 vgetcpu_mode = VGETCPU_RDTSCP;
953 else
954 vgetcpu_mode = VGETCPU_LSL;
955}
956#endif
957
958void __init identify_boot_cpu(void)
959{
960 identify_cpu(&boot_cpu_data);
961 init_amd_e400_c1e_mask();
962#ifdef CONFIG_X86_32
963 sysenter_setup();
964 enable_sep_cpu();
965#else
966 vgetcpu_set_mode();
967#endif
968 cpu_detect_tlb(&boot_cpu_data);
969}
970
971void identify_secondary_cpu(struct cpuinfo_x86 *c)
972{
973 BUG_ON(c == &boot_cpu_data);
974 identify_cpu(c);
975#ifdef CONFIG_X86_32
976 enable_sep_cpu();
977#endif
978 mtrr_ap_init();
979}
980
981struct msr_range {
982 unsigned min;
983 unsigned max;
984};
985
986static const struct msr_range msr_range_array[] = {
987 { 0x00000000, 0x00000418},
988 { 0xc0000000, 0xc000040b},
989 { 0xc0010000, 0xc0010142},
990 { 0xc0011000, 0xc001103b},
991};
992
993static void __print_cpu_msr(void)
994{
995 unsigned index_min, index_max;
996 unsigned index;
997 u64 val;
998 int i;
999
1000 for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
1001 index_min = msr_range_array[i].min;
1002 index_max = msr_range_array[i].max;
1003
1004 for (index = index_min; index < index_max; index++) {
1005 if (rdmsrl_safe(index, &val))
1006 continue;
1007 printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
1008 }
1009 }
1010}
1011
1012static int show_msr;
1013
1014static __init int setup_show_msr(char *arg)
1015{
1016 int num;
1017
1018 get_option(&arg, &num);
1019
1020 if (num > 0)
1021 show_msr = num;
1022 return 1;
1023}
1024__setup("show_msr=", setup_show_msr);
1025
1026static __init int setup_noclflush(char *arg)
1027{
1028 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1029 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1030 return 1;
1031}
1032__setup("noclflush", setup_noclflush);
1033
1034void print_cpu_info(struct cpuinfo_x86 *c)
1035{
1036 const char *vendor = NULL;
1037
1038 if (c->x86_vendor < X86_VENDOR_NUM) {
1039 vendor = this_cpu->c_vendor;
1040 } else {
1041 if (c->cpuid_level >= 0)
1042 vendor = c->x86_vendor_id;
1043 }
1044
1045 if (vendor && !strstr(c->x86_model_id, vendor))
1046 printk(KERN_CONT "%s ", vendor);
1047
1048 if (c->x86_model_id[0])
1049 printk(KERN_CONT "%s", strim(c->x86_model_id));
1050 else
1051 printk(KERN_CONT "%d86", c->x86);
1052
1053 printk(KERN_CONT " (fam: %02x, model: %02x", c->x86, c->x86_model);
1054
1055 if (c->x86_mask || c->cpuid_level >= 0)
1056 printk(KERN_CONT ", stepping: %02x)\n", c->x86_mask);
1057 else
1058 printk(KERN_CONT ")\n");
1059
1060 print_cpu_msr(c);
1061}
1062
1063void print_cpu_msr(struct cpuinfo_x86 *c)
1064{
1065 if (c->cpu_index < show_msr)
1066 __print_cpu_msr();
1067}
1068
1069static __init int setup_disablecpuid(char *arg)
1070{
1071 int bit;
1072
1073 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1074 setup_clear_cpu_cap(bit);
1075 else
1076 return 0;
1077
1078 return 1;
1079}
1080__setup("clearcpuid=", setup_disablecpuid);
1081
1082DEFINE_PER_CPU(unsigned long, kernel_stack) =
1083 (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE;
1084EXPORT_PER_CPU_SYMBOL(kernel_stack);
1085
1086#ifdef CONFIG_X86_64
1087struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table };
1088struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1,
1089 (unsigned long) debug_idt_table };
1090
1091DEFINE_PER_CPU_FIRST(union irq_stack_union,
1092 irq_stack_union) __aligned(PAGE_SIZE) __visible;
1093
1094/*
1095 * The following four percpu variables are hot. Align current_task to
1096 * cacheline size such that all four fall in the same cacheline.
1097 */
1098DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1099 &init_task;
1100EXPORT_PER_CPU_SYMBOL(current_task);
1101
1102DEFINE_PER_CPU(char *, irq_stack_ptr) =
1103 init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
1104
1105DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1106
1107DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1108EXPORT_PER_CPU_SYMBOL(__preempt_count);
1109
1110DEFINE_PER_CPU(struct task_struct *, fpu_owner_task);
1111
1112/*
1113 * Special IST stacks which the CPU switches to when it calls
1114 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1115 * limit), all of them are 4K, except the debug stack which
1116 * is 8K.
1117 */
1118static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1119 [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
1120 [DEBUG_STACK - 1] = DEBUG_STKSZ
1121};
1122
1123static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1124 [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1125
1126/* May not be marked __init: used by software suspend */
1127void syscall_init(void)
1128{
1129 /*
1130 * LSTAR and STAR live in a bit strange symbiosis.
1131 * They both write to the same internal register. STAR allows to
1132 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1133 */
1134 wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
1135 wrmsrl(MSR_LSTAR, system_call);
1136 wrmsrl(MSR_CSTAR, ignore_sysret);
1137
1138#ifdef CONFIG_IA32_EMULATION
1139 syscall32_cpu_init();
1140#endif
1141
1142 /* Flags to clear on syscall */
1143 wrmsrl(MSR_SYSCALL_MASK,
1144 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1145 X86_EFLAGS_IOPL|X86_EFLAGS_AC);
1146}
1147
1148/*
1149 * Copies of the original ist values from the tss are only accessed during
1150 * debugging, no special alignment required.
1151 */
1152DEFINE_PER_CPU(struct orig_ist, orig_ist);
1153
1154static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1155DEFINE_PER_CPU(int, debug_stack_usage);
1156
1157int is_debug_stack(unsigned long addr)
1158{
1159 return __get_cpu_var(debug_stack_usage) ||
1160 (addr <= __get_cpu_var(debug_stack_addr) &&
1161 addr > (__get_cpu_var(debug_stack_addr) - DEBUG_STKSZ));
1162}
1163
1164DEFINE_PER_CPU(u32, debug_idt_ctr);
1165
1166void debug_stack_set_zero(void)
1167{
1168 this_cpu_inc(debug_idt_ctr);
1169 load_current_idt();
1170}
1171
1172void debug_stack_reset(void)
1173{
1174 if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1175 return;
1176 if (this_cpu_dec_return(debug_idt_ctr) == 0)
1177 load_current_idt();
1178}
1179
1180#else /* CONFIG_X86_64 */
1181
1182DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1183EXPORT_PER_CPU_SYMBOL(current_task);
1184DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1185EXPORT_PER_CPU_SYMBOL(__preempt_count);
1186DEFINE_PER_CPU(struct task_struct *, fpu_owner_task);
1187
1188#ifdef CONFIG_CC_STACKPROTECTOR
1189DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1190#endif
1191
1192#endif /* CONFIG_X86_64 */
1193
1194/*
1195 * Clear all 6 debug registers:
1196 */
1197static void clear_all_debug_regs(void)
1198{
1199 int i;
1200
1201 for (i = 0; i < 8; i++) {
1202 /* Ignore db4, db5 */
1203 if ((i == 4) || (i == 5))
1204 continue;
1205
1206 set_debugreg(0, i);
1207 }
1208}
1209
1210#ifdef CONFIG_KGDB
1211/*
1212 * Restore debug regs if using kgdbwait and you have a kernel debugger
1213 * connection established.
1214 */
1215static void dbg_restore_debug_regs(void)
1216{
1217 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1218 arch_kgdb_ops.correct_hw_break();
1219}
1220#else /* ! CONFIG_KGDB */
1221#define dbg_restore_debug_regs()
1222#endif /* ! CONFIG_KGDB */
1223
1224/*
1225 * cpu_init() initializes state that is per-CPU. Some data is already
1226 * initialized (naturally) in the bootstrap process, such as the GDT
1227 * and IDT. We reload them nevertheless, this function acts as a
1228 * 'CPU state barrier', nothing should get across.
1229 * A lot of state is already set up in PDA init for 64 bit
1230 */
1231#ifdef CONFIG_X86_64
1232
1233void cpu_init(void)
1234{
1235 struct orig_ist *oist;
1236 struct task_struct *me;
1237 struct tss_struct *t;
1238 unsigned long v;
1239 int cpu;
1240 int i;
1241
1242 /*
1243 * Load microcode on this cpu if a valid microcode is available.
1244 * This is early microcode loading procedure.
1245 */
1246 load_ucode_ap();
1247
1248 cpu = stack_smp_processor_id();
1249 t = &per_cpu(init_tss, cpu);
1250 oist = &per_cpu(orig_ist, cpu);
1251
1252#ifdef CONFIG_NUMA
1253 if (this_cpu_read(numa_node) == 0 &&
1254 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1255 set_numa_node(early_cpu_to_node(cpu));
1256#endif
1257
1258 me = current;
1259
1260 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask))
1261 panic("CPU#%d already initialized!\n", cpu);
1262
1263 pr_debug("Initializing CPU#%d\n", cpu);
1264
1265 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1266
1267 /*
1268 * Initialize the per-CPU GDT with the boot GDT,
1269 * and set up the GDT descriptor:
1270 */
1271
1272 switch_to_new_gdt(cpu);
1273 loadsegment(fs, 0);
1274
1275 load_current_idt();
1276
1277 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1278 syscall_init();
1279
1280 wrmsrl(MSR_FS_BASE, 0);
1281 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1282 barrier();
1283
1284 x86_configure_nx();
1285 enable_x2apic();
1286
1287 /*
1288 * set up and load the per-CPU TSS
1289 */
1290 if (!oist->ist[0]) {
1291 char *estacks = per_cpu(exception_stacks, cpu);
1292
1293 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1294 estacks += exception_stack_sizes[v];
1295 oist->ist[v] = t->x86_tss.ist[v] =
1296 (unsigned long)estacks;
1297 if (v == DEBUG_STACK-1)
1298 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1299 }
1300 }
1301
1302 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1303
1304 /*
1305 * <= is required because the CPU will access up to
1306 * 8 bits beyond the end of the IO permission bitmap.
1307 */
1308 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1309 t->io_bitmap[i] = ~0UL;
1310
1311 atomic_inc(&init_mm.mm_count);
1312 me->active_mm = &init_mm;
1313 BUG_ON(me->mm);
1314 enter_lazy_tlb(&init_mm, me);
1315
1316 load_sp0(t, ¤t->thread);
1317 set_tss_desc(cpu, t);
1318 load_TR_desc();
1319 load_LDT(&init_mm.context);
1320
1321 clear_all_debug_regs();
1322 dbg_restore_debug_regs();
1323
1324 fpu_init();
1325
1326 if (is_uv_system())
1327 uv_cpu_init();
1328}
1329
1330#else
1331
1332void cpu_init(void)
1333{
1334 int cpu = smp_processor_id();
1335 struct task_struct *curr = current;
1336 struct tss_struct *t = &per_cpu(init_tss, cpu);
1337 struct thread_struct *thread = &curr->thread;
1338
1339 show_ucode_info_early();
1340
1341 if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) {
1342 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1343 for (;;)
1344 local_irq_enable();
1345 }
1346
1347 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1348
1349 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
1350 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1351
1352 load_current_idt();
1353 switch_to_new_gdt(cpu);
1354
1355 /*
1356 * Set up and load the per-CPU TSS and LDT
1357 */
1358 atomic_inc(&init_mm.mm_count);
1359 curr->active_mm = &init_mm;
1360 BUG_ON(curr->mm);
1361 enter_lazy_tlb(&init_mm, curr);
1362
1363 load_sp0(t, thread);
1364 set_tss_desc(cpu, t);
1365 load_TR_desc();
1366 load_LDT(&init_mm.context);
1367
1368 t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1369
1370#ifdef CONFIG_DOUBLEFAULT
1371 /* Set up doublefault TSS pointer in the GDT */
1372 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1373#endif
1374
1375 clear_all_debug_regs();
1376 dbg_restore_debug_regs();
1377
1378 fpu_init();
1379}
1380#endif
1381
1382#ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS
1383void warn_pre_alternatives(void)
1384{
1385 WARN(1, "You're using static_cpu_has before alternatives have run!\n");
1386}
1387EXPORT_SYMBOL_GPL(warn_pre_alternatives);
1388#endif
1389
1390inline bool __static_cpu_has_safe(u16 bit)
1391{
1392 return boot_cpu_has(bit);
1393}
1394EXPORT_SYMBOL_GPL(__static_cpu_has_safe);