1/* SPDX-License-Identifier: GPL-2.0 */
  2#include <linux/platform_device.h>
  3
  4#include <asm/cpu_type.h>
  5
  6struct irq_bucket {
  7        struct irq_bucket *next;
  8        unsigned int real_irq;
  9        unsigned int irq;
 10        unsigned int pil;
 11};
 12
 13#define SUN4M_HARD_INT(x)       (0x000000001 << (x))
 14#define SUN4M_SOFT_INT(x)       (0x000010000 << (x))
 15
 16#define SUN4D_MAX_BOARD 10
 17#define SUN4D_MAX_IRQ ((SUN4D_MAX_BOARD + 2) << 5)
 18
 19/* Map between the irq identifier used in hw to the
 20 * irq_bucket. The map is sufficient large to hold
 21 * the sun4d hw identifiers.
 22 */
 23extern struct irq_bucket *irq_map[SUN4D_MAX_IRQ];
 24
 25
 26/* sun4m specific type definitions */
 27
 28/* This maps direct to CPU specific interrupt registers */
 29struct sun4m_irq_percpu {
 30	u32	pending;
 31	u32	clear;
 32	u32	set;
 33};
 34
 35/* This maps direct to global interrupt registers */
 36struct sun4m_irq_global {
 37	u32	pending;
 38	u32	mask;
 39	u32	mask_clear;
 40	u32	mask_set;
 41	u32	interrupt_target;
 42};
 43
 44extern struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS];
 45extern struct sun4m_irq_global __iomem *sun4m_irq_global;
 46
 47/* The following definitions describe the individual platform features: */
 48#define FEAT_L10_CLOCKSOURCE (1 << 0) /* L10 timer is used as a clocksource */
 49#define FEAT_L10_CLOCKEVENT  (1 << 1) /* L10 timer is used as a clockevent */
 50#define FEAT_L14_ONESHOT     (1 << 2) /* L14 timer clockevent can oneshot */
 51
 52/*
 53 * Platform specific configuration
 54 * The individual platforms assign their platform
 55 * specifics in their init functions.
 56 */
 57struct sparc_config {
 58	void (*init_timers)(void);
 59	unsigned int (*build_device_irq)(struct platform_device *op,
 60	                                 unsigned int real_irq);
 61
 62	/* generic clockevent features - see FEAT_* above */
 63	int features;
 64
 65	/* clock rate used for clock event timer */
 66	int clock_rate;
 67
 68	/* one period for clock source timer */
 69	unsigned int cs_period;
 70
 71	/* function to obtain offsett for cs period */
 72	unsigned int (*get_cycles_offset)(void);
 73
 74	void (*clear_clock_irq)(void);
 75	void (*load_profile_irq)(int cpu, unsigned int limit);
 76};
 77extern struct sparc_config sparc_config;
 78
 79unsigned int irq_alloc(unsigned int real_irq, unsigned int pil);
 80void irq_link(unsigned int irq);
 81void irq_unlink(unsigned int irq);
 82void handler_irq(unsigned int pil, struct pt_regs *regs);
 83
 84unsigned long leon_get_irqmask(unsigned int irq);
 85
 86/* irq_32.c */
 87void sparc_floppy_irq(int irq, void *dev_id, struct pt_regs *regs);
 88
 89/* sun4m_irq.c */
 90void sun4m_nmi(struct pt_regs *regs);
 91
 92/* sun4d_irq.c */
 93void sun4d_handler_irq(unsigned int pil, struct pt_regs *regs);
 94
 95#ifdef CONFIG_SMP
 96
 97/* All SUN4D IPIs are sent on this IRQ, may be shared with hard IRQs */
 98#define SUN4D_IPI_IRQ 13
 99
100void sun4d_ipi_interrupt(void);
101
102#endif

 
 1#include <linux/platform_device.h>
 2
 3#include <asm/cpu_type.h>
 4
 5struct irq_bucket {
 6        struct irq_bucket *next;
 7        unsigned int real_irq;
 8        unsigned int irq;
 9        unsigned int pil;
10};
11
12#define SUN4M_HARD_INT(x)       (0x000000001 << (x))
13#define SUN4M_SOFT_INT(x)       (0x000010000 << (x))
14
15#define SUN4D_MAX_BOARD 10
16#define SUN4D_MAX_IRQ ((SUN4D_MAX_BOARD + 2) << 5)
17
18/* Map between the irq identifier used in hw to the
19 * irq_bucket. The map is sufficient large to hold
20 * the sun4d hw identifiers.
21 */
22extern struct irq_bucket *irq_map[SUN4D_MAX_IRQ];
23
24
25/* sun4m specific type definitions */
26
27/* This maps direct to CPU specific interrupt registers */
28struct sun4m_irq_percpu {
29	u32	pending;
30	u32	clear;
31	u32	set;
32};
33
34/* This maps direct to global interrupt registers */
35struct sun4m_irq_global {
36	u32	pending;
37	u32	mask;
38	u32	mask_clear;
39	u32	mask_set;
40	u32	interrupt_target;
41};
42
43extern struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS];
44extern struct sun4m_irq_global __iomem *sun4m_irq_global;
45
46/* The following definitions describe the individual platform features: */
47#define FEAT_L10_CLOCKSOURCE (1 << 0) /* L10 timer is used as a clocksource */
48#define FEAT_L10_CLOCKEVENT  (1 << 1) /* L10 timer is used as a clockevent */
49#define FEAT_L14_ONESHOT     (1 << 2) /* L14 timer clockevent can oneshot */
50
51/*
52 * Platform specific configuration
53 * The individual platforms assign their platform
54 * specifics in their init functions.
55 */
56struct sparc_config {
57	void (*init_timers)(void);
58	unsigned int (*build_device_irq)(struct platform_device *op,
59	                                 unsigned int real_irq);
60
61	/* generic clockevent features - see FEAT_* above */
62	int features;
63
64	/* clock rate used for clock event timer */
65	int clock_rate;
66
67	/* one period for clock source timer */
68	unsigned int cs_period;
69
70	/* function to obtain offsett for cs period */
71	unsigned int (*get_cycles_offset)(void);
72
73	void (*clear_clock_irq)(void);
74	void (*load_profile_irq)(int cpu, unsigned int limit);
75};
76extern struct sparc_config sparc_config;
77
78unsigned int irq_alloc(unsigned int real_irq, unsigned int pil);
79void irq_link(unsigned int irq);
80void irq_unlink(unsigned int irq);
81void handler_irq(unsigned int pil, struct pt_regs *regs);
82
83unsigned long leon_get_irqmask(unsigned int irq);
84
 
 
 
 
 
 
 
 
 
85#ifdef CONFIG_SMP
86
87/* All SUN4D IPIs are sent on this IRQ, may be shared with hard IRQs */
88#define SUN4D_IPI_IRQ 13
89
90extern void sun4d_ipi_interrupt(void);
91
92#endif