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1/* SPDX-License-Identifier: GPL-2.0 */
2#include <asm/processor.h>
3#include <asm/ppc_asm.h>
4#include <asm/reg.h>
5#include <asm/asm-offsets.h>
6#include <asm/cputable.h>
7#include <asm/thread_info.h>
8#include <asm/page.h>
9#include <asm/ptrace.h>
10#include <asm/export.h>
11
12/*
13 * Load state from memory into VMX registers including VSCR.
14 * Assumes the caller has enabled VMX in the MSR.
15 */
16_GLOBAL(load_vr_state)
17 li r4,VRSTATE_VSCR
18 lvx v0,r4,r3
19 mtvscr v0
20 REST_32VRS(0,r4,r3)
21 blr
22EXPORT_SYMBOL(load_vr_state)
23
24/*
25 * Store VMX state into memory, including VSCR.
26 * Assumes the caller has enabled VMX in the MSR.
27 */
28_GLOBAL(store_vr_state)
29 SAVE_32VRS(0, r4, r3)
30 mfvscr v0
31 li r4, VRSTATE_VSCR
32 stvx v0, r4, r3
33 blr
34EXPORT_SYMBOL(store_vr_state)
35
36/*
37 * Disable VMX for the task which had it previously,
38 * and save its vector registers in its thread_struct.
39 * Enables the VMX for use in the kernel on return.
40 * On SMP we know the VMX is free, since we give it up every
41 * switch (ie, no lazy save of the vector registers).
42 *
43 * Note that on 32-bit this can only use registers that will be
44 * restored by fast_exception_return, i.e. r3 - r6, r10 and r11.
45 */
46_GLOBAL(load_up_altivec)
47 mfmsr r5 /* grab the current MSR */
48 oris r5,r5,MSR_VEC@h
49 MTMSRD(r5) /* enable use of AltiVec now */
50 isync
51
52 /*
53 * While userspace in general ignores VRSAVE, glibc uses it as a boolean
54 * to optimise userspace context save/restore. Whenever we take an
55 * altivec unavailable exception we must set VRSAVE to something non
56 * zero. Set it to all 1s. See also the programming note in the ISA.
57 */
58 mfspr r4,SPRN_VRSAVE
59 cmpwi 0,r4,0
60 bne+ 1f
61 li r4,-1
62 mtspr SPRN_VRSAVE,r4
631:
64 /* enable use of VMX after return */
65#ifdef CONFIG_PPC32
66 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
67 oris r9,r9,MSR_VEC@h
68#else
69 ld r4,PACACURRENT(r13)
70 addi r5,r4,THREAD /* Get THREAD */
71 oris r12,r12,MSR_VEC@h
72 std r12,_MSR(r1)
73#endif
74 /* Don't care if r4 overflows, this is desired behaviour */
75 lbz r4,THREAD_LOAD_VEC(r5)
76 addi r4,r4,1
77 stb r4,THREAD_LOAD_VEC(r5)
78 addi r6,r5,THREAD_VRSTATE
79 li r4,1
80 li r10,VRSTATE_VSCR
81 stw r4,THREAD_USED_VR(r5)
82 lvx v0,r10,r6
83 mtvscr v0
84 REST_32VRS(0,r4,r6)
85 /* restore registers and return */
86 blr
87
88/*
89 * save_altivec(tsk)
90 * Save the vector registers to its thread_struct
91 */
92_GLOBAL(save_altivec)
93 addi r3,r3,THREAD /* want THREAD of task */
94 PPC_LL r7,THREAD_VRSAVEAREA(r3)
95 PPC_LL r5,PT_REGS(r3)
96 PPC_LCMPI 0,r7,0
97 bne 2f
98 addi r7,r3,THREAD_VRSTATE
992: SAVE_32VRS(0,r4,r7)
100 mfvscr v0
101 li r4,VRSTATE_VSCR
102 stvx v0,r4,r7
103 blr
104
105#ifdef CONFIG_VSX
106
107#ifdef CONFIG_PPC32
108#error This asm code isn't ready for 32-bit kernels
109#endif
110
111/*
112 * load_up_vsx(unused, unused, tsk)
113 * Disable VSX for the task which had it previously,
114 * and save its vector registers in its thread_struct.
115 * Reuse the fp and vsx saves, but first check to see if they have
116 * been saved already.
117 */
118_GLOBAL(load_up_vsx)
119/* Load FP and VSX registers if they haven't been done yet */
120 andi. r5,r12,MSR_FP
121 beql+ load_up_fpu /* skip if already loaded */
122 andis. r5,r12,MSR_VEC@h
123 beql+ load_up_altivec /* skip if already loaded */
124
125 ld r4,PACACURRENT(r13)
126 addi r4,r4,THREAD /* Get THREAD */
127 li r6,1
128 stw r6,THREAD_USED_VSR(r4) /* ... also set thread used vsr */
129 /* enable use of VSX after return */
130 oris r12,r12,MSR_VSX@h
131 std r12,_MSR(r1)
132 b fast_exception_return
133
134#endif /* CONFIG_VSX */
135
136
137/*
138 * The routines below are in assembler so we can closely control the
139 * usage of floating-point registers. These routines must be called
140 * with preempt disabled.
141 */
142#ifdef CONFIG_PPC32
143 .data
144fpzero:
145 .long 0
146fpone:
147 .long 0x3f800000 /* 1.0 in single-precision FP */
148fphalf:
149 .long 0x3f000000 /* 0.5 in single-precision FP */
150
151#define LDCONST(fr, name) \
152 lis r11,name@ha; \
153 lfs fr,name@l(r11)
154#else
155
156 .section ".toc","aw"
157fpzero:
158 .tc FD_0_0[TC],0
159fpone:
160 .tc FD_3ff00000_0[TC],0x3ff0000000000000 /* 1.0 */
161fphalf:
162 .tc FD_3fe00000_0[TC],0x3fe0000000000000 /* 0.5 */
163
164#define LDCONST(fr, name) \
165 lfd fr,name@toc(r2)
166#endif
167
168 .text
169/*
170 * Internal routine to enable floating point and set FPSCR to 0.
171 * Don't call it from C; it doesn't use the normal calling convention.
172 */
173fpenable:
174#ifdef CONFIG_PPC32
175 stwu r1,-64(r1)
176#else
177 stdu r1,-64(r1)
178#endif
179 mfmsr r10
180 ori r11,r10,MSR_FP
181 mtmsr r11
182 isync
183 stfd fr0,24(r1)
184 stfd fr1,16(r1)
185 stfd fr31,8(r1)
186 LDCONST(fr1, fpzero)
187 mffs fr31
188 MTFSF_L(fr1)
189 blr
190
191fpdisable:
192 mtlr r12
193 MTFSF_L(fr31)
194 lfd fr31,8(r1)
195 lfd fr1,16(r1)
196 lfd fr0,24(r1)
197 mtmsr r10
198 isync
199 addi r1,r1,64
200 blr
201
202/*
203 * Vector add, floating point.
204 */
205_GLOBAL(vaddfp)
206 mflr r12
207 bl fpenable
208 li r0,4
209 mtctr r0
210 li r6,0
2111: lfsx fr0,r4,r6
212 lfsx fr1,r5,r6
213 fadds fr0,fr0,fr1
214 stfsx fr0,r3,r6
215 addi r6,r6,4
216 bdnz 1b
217 b fpdisable
218
219/*
220 * Vector subtract, floating point.
221 */
222_GLOBAL(vsubfp)
223 mflr r12
224 bl fpenable
225 li r0,4
226 mtctr r0
227 li r6,0
2281: lfsx fr0,r4,r6
229 lfsx fr1,r5,r6
230 fsubs fr0,fr0,fr1
231 stfsx fr0,r3,r6
232 addi r6,r6,4
233 bdnz 1b
234 b fpdisable
235
236/*
237 * Vector multiply and add, floating point.
238 */
239_GLOBAL(vmaddfp)
240 mflr r12
241 bl fpenable
242 stfd fr2,32(r1)
243 li r0,4
244 mtctr r0
245 li r7,0
2461: lfsx fr0,r4,r7
247 lfsx fr1,r5,r7
248 lfsx fr2,r6,r7
249 fmadds fr0,fr0,fr2,fr1
250 stfsx fr0,r3,r7
251 addi r7,r7,4
252 bdnz 1b
253 lfd fr2,32(r1)
254 b fpdisable
255
256/*
257 * Vector negative multiply and subtract, floating point.
258 */
259_GLOBAL(vnmsubfp)
260 mflr r12
261 bl fpenable
262 stfd fr2,32(r1)
263 li r0,4
264 mtctr r0
265 li r7,0
2661: lfsx fr0,r4,r7
267 lfsx fr1,r5,r7
268 lfsx fr2,r6,r7
269 fnmsubs fr0,fr0,fr2,fr1
270 stfsx fr0,r3,r7
271 addi r7,r7,4
272 bdnz 1b
273 lfd fr2,32(r1)
274 b fpdisable
275
276/*
277 * Vector reciprocal estimate. We just compute 1.0/x.
278 * r3 -> destination, r4 -> source.
279 */
280_GLOBAL(vrefp)
281 mflr r12
282 bl fpenable
283 li r0,4
284 LDCONST(fr1, fpone)
285 mtctr r0
286 li r6,0
2871: lfsx fr0,r4,r6
288 fdivs fr0,fr1,fr0
289 stfsx fr0,r3,r6
290 addi r6,r6,4
291 bdnz 1b
292 b fpdisable
293
294/*
295 * Vector reciprocal square-root estimate, floating point.
296 * We use the frsqrte instruction for the initial estimate followed
297 * by 2 iterations of Newton-Raphson to get sufficient accuracy.
298 * r3 -> destination, r4 -> source.
299 */
300_GLOBAL(vrsqrtefp)
301 mflr r12
302 bl fpenable
303 stfd fr2,32(r1)
304 stfd fr3,40(r1)
305 stfd fr4,48(r1)
306 stfd fr5,56(r1)
307 li r0,4
308 LDCONST(fr4, fpone)
309 LDCONST(fr5, fphalf)
310 mtctr r0
311 li r6,0
3121: lfsx fr0,r4,r6
313 frsqrte fr1,fr0 /* r = frsqrte(s) */
314 fmuls fr3,fr1,fr0 /* r * s */
315 fmuls fr2,fr1,fr5 /* r * 0.5 */
316 fnmsubs fr3,fr1,fr3,fr4 /* 1 - s * r * r */
317 fmadds fr1,fr2,fr3,fr1 /* r = r + 0.5 * r * (1 - s * r * r) */
318 fmuls fr3,fr1,fr0 /* r * s */
319 fmuls fr2,fr1,fr5 /* r * 0.5 */
320 fnmsubs fr3,fr1,fr3,fr4 /* 1 - s * r * r */
321 fmadds fr1,fr2,fr3,fr1 /* r = r + 0.5 * r * (1 - s * r * r) */
322 stfsx fr1,r3,r6
323 addi r6,r6,4
324 bdnz 1b
325 lfd fr5,56(r1)
326 lfd fr4,48(r1)
327 lfd fr3,40(r1)
328 lfd fr2,32(r1)
329 b fpdisable
1#include <asm/processor.h>
2#include <asm/ppc_asm.h>
3#include <asm/reg.h>
4#include <asm/asm-offsets.h>
5#include <asm/cputable.h>
6#include <asm/thread_info.h>
7#include <asm/page.h>
8#include <asm/ptrace.h>
9
10#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
11/* void do_load_up_transact_altivec(struct thread_struct *thread)
12 *
13 * This is similar to load_up_altivec but for the transactional version of the
14 * vector regs. It doesn't mess with the task MSR or valid flags.
15 * Furthermore, VEC laziness is not supported with TM currently.
16 */
17_GLOBAL(do_load_up_transact_altivec)
18 mfmsr r6
19 oris r5,r6,MSR_VEC@h
20 MTMSRD(r5)
21 isync
22
23 li r4,1
24 stw r4,THREAD_USED_VR(r3)
25
26 li r10,THREAD_TRANSACT_VRSTATE+VRSTATE_VSCR
27 lvx vr0,r10,r3
28 mtvscr vr0
29 addi r10,r3,THREAD_TRANSACT_VRSTATE
30 REST_32VRS(0,r4,r10)
31
32 /* Disable VEC again. */
33 MTMSRD(r6)
34 isync
35
36 blr
37#endif
38
39/*
40 * Enable use of VMX/Altivec for the caller.
41 */
42_GLOBAL(vec_enable)
43 mfmsr r3
44 oris r3,r3,MSR_VEC@h
45 MTMSRD(r3)
46 isync
47 blr
48
49/*
50 * Load state from memory into VMX registers including VSCR.
51 * Assumes the caller has enabled VMX in the MSR.
52 */
53_GLOBAL(load_vr_state)
54 li r4,VRSTATE_VSCR
55 lvx vr0,r4,r3
56 mtvscr vr0
57 REST_32VRS(0,r4,r3)
58 blr
59
60/*
61 * Store VMX state into memory, including VSCR.
62 * Assumes the caller has enabled VMX in the MSR.
63 */
64_GLOBAL(store_vr_state)
65 SAVE_32VRS(0, r4, r3)
66 mfvscr vr0
67 li r4, VRSTATE_VSCR
68 stvx vr0, r4, r3
69 blr
70
71/*
72 * Disable VMX for the task which had it previously,
73 * and save its vector registers in its thread_struct.
74 * Enables the VMX for use in the kernel on return.
75 * On SMP we know the VMX is free, since we give it up every
76 * switch (ie, no lazy save of the vector registers).
77 *
78 * Note that on 32-bit this can only use registers that will be
79 * restored by fast_exception_return, i.e. r3 - r6, r10 and r11.
80 */
81_GLOBAL(load_up_altivec)
82 mfmsr r5 /* grab the current MSR */
83 oris r5,r5,MSR_VEC@h
84 MTMSRD(r5) /* enable use of AltiVec now */
85 isync
86
87/*
88 * For SMP, we don't do lazy VMX switching because it just gets too
89 * horrendously complex, especially when a task switches from one CPU
90 * to another. Instead we call giveup_altvec in switch_to.
91 * VRSAVE isn't dealt with here, that is done in the normal context
92 * switch code. Note that we could rely on vrsave value to eventually
93 * avoid saving all of the VREGs here...
94 */
95#ifndef CONFIG_SMP
96 LOAD_REG_ADDRBASE(r3, last_task_used_altivec)
97 toreal(r3)
98 PPC_LL r4,ADDROFF(last_task_used_altivec)(r3)
99 PPC_LCMPI 0,r4,0
100 beq 1f
101
102 /* Save VMX state to last_task_used_altivec's THREAD struct */
103 toreal(r4)
104 addi r4,r4,THREAD
105 addi r6,r4,THREAD_VRSTATE
106 SAVE_32VRS(0,r5,r6)
107 mfvscr vr0
108 li r10,VRSTATE_VSCR
109 stvx vr0,r10,r6
110 /* Disable VMX for last_task_used_altivec */
111 PPC_LL r5,PT_REGS(r4)
112 toreal(r5)
113 PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
114 lis r10,MSR_VEC@h
115 andc r4,r4,r10
116 PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1171:
118#endif /* CONFIG_SMP */
119
120 /* Hack: if we get an altivec unavailable trap with VRSAVE
121 * set to all zeros, we assume this is a broken application
122 * that fails to set it properly, and thus we switch it to
123 * all 1's
124 */
125 mfspr r4,SPRN_VRSAVE
126 cmpwi 0,r4,0
127 bne+ 1f
128 li r4,-1
129 mtspr SPRN_VRSAVE,r4
1301:
131 /* enable use of VMX after return */
132#ifdef CONFIG_PPC32
133 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
134 oris r9,r9,MSR_VEC@h
135#else
136 ld r4,PACACURRENT(r13)
137 addi r5,r4,THREAD /* Get THREAD */
138 oris r12,r12,MSR_VEC@h
139 std r12,_MSR(r1)
140#endif
141 addi r6,r5,THREAD_VRSTATE
142 li r4,1
143 li r10,VRSTATE_VSCR
144 stw r4,THREAD_USED_VR(r5)
145 lvx vr0,r10,r6
146 mtvscr vr0
147 REST_32VRS(0,r4,r6)
148#ifndef CONFIG_SMP
149 /* Update last_task_used_altivec to 'current' */
150 subi r4,r5,THREAD /* Back to 'current' */
151 fromreal(r4)
152 PPC_STL r4,ADDROFF(last_task_used_altivec)(r3)
153#endif /* CONFIG_SMP */
154 /* restore registers and return */
155 blr
156
157_GLOBAL(giveup_altivec_notask)
158 mfmsr r3
159 andis. r4,r3,MSR_VEC@h
160 bnelr /* Already enabled? */
161 oris r3,r3,MSR_VEC@h
162 SYNC
163 MTMSRD(r3) /* enable use of VMX now */
164 isync
165 blr
166
167/*
168 * giveup_altivec(tsk)
169 * Disable VMX for the task given as the argument,
170 * and save the vector registers in its thread_struct.
171 * Enables the VMX for use in the kernel on return.
172 */
173_GLOBAL(giveup_altivec)
174 mfmsr r5
175 oris r5,r5,MSR_VEC@h
176 SYNC
177 MTMSRD(r5) /* enable use of VMX now */
178 isync
179 PPC_LCMPI 0,r3,0
180 beqlr /* if no previous owner, done */
181 addi r3,r3,THREAD /* want THREAD of task */
182 PPC_LL r7,THREAD_VRSAVEAREA(r3)
183 PPC_LL r5,PT_REGS(r3)
184 PPC_LCMPI 0,r7,0
185 bne 2f
186 addi r7,r3,THREAD_VRSTATE
1872: PPC_LCMPI 0,r5,0
188 SAVE_32VRS(0,r4,r7)
189 mfvscr vr0
190 li r4,VRSTATE_VSCR
191 stvx vr0,r4,r7
192 beq 1f
193 PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
194#ifdef CONFIG_VSX
195BEGIN_FTR_SECTION
196 lis r3,(MSR_VEC|MSR_VSX)@h
197FTR_SECTION_ELSE
198 lis r3,MSR_VEC@h
199ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
200#else
201 lis r3,MSR_VEC@h
202#endif
203 andc r4,r4,r3 /* disable FP for previous task */
204 PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
2051:
206#ifndef CONFIG_SMP
207 li r5,0
208 LOAD_REG_ADDRBASE(r4,last_task_used_altivec)
209 PPC_STL r5,ADDROFF(last_task_used_altivec)(r4)
210#endif /* CONFIG_SMP */
211 blr
212
213#ifdef CONFIG_VSX
214
215#ifdef CONFIG_PPC32
216#error This asm code isn't ready for 32-bit kernels
217#endif
218
219/*
220 * load_up_vsx(unused, unused, tsk)
221 * Disable VSX for the task which had it previously,
222 * and save its vector registers in its thread_struct.
223 * Reuse the fp and vsx saves, but first check to see if they have
224 * been saved already.
225 */
226_GLOBAL(load_up_vsx)
227/* Load FP and VSX registers if they haven't been done yet */
228 andi. r5,r12,MSR_FP
229 beql+ load_up_fpu /* skip if already loaded */
230 andis. r5,r12,MSR_VEC@h
231 beql+ load_up_altivec /* skip if already loaded */
232
233#ifndef CONFIG_SMP
234 ld r3,last_task_used_vsx@got(r2)
235 ld r4,0(r3)
236 cmpdi 0,r4,0
237 beq 1f
238 /* Disable VSX for last_task_used_vsx */
239 addi r4,r4,THREAD
240 ld r5,PT_REGS(r4)
241 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
242 lis r6,MSR_VSX@h
243 andc r6,r4,r6
244 std r6,_MSR-STACK_FRAME_OVERHEAD(r5)
2451:
246#endif /* CONFIG_SMP */
247 ld r4,PACACURRENT(r13)
248 addi r4,r4,THREAD /* Get THREAD */
249 li r6,1
250 stw r6,THREAD_USED_VSR(r4) /* ... also set thread used vsr */
251 /* enable use of VSX after return */
252 oris r12,r12,MSR_VSX@h
253 std r12,_MSR(r1)
254#ifndef CONFIG_SMP
255 /* Update last_task_used_vsx to 'current' */
256 ld r4,PACACURRENT(r13)
257 std r4,0(r3)
258#endif /* CONFIG_SMP */
259 b fast_exception_return
260
261/*
262 * __giveup_vsx(tsk)
263 * Disable VSX for the task given as the argument.
264 * Does NOT save vsx registers.
265 * Enables the VSX for use in the kernel on return.
266 */
267_GLOBAL(__giveup_vsx)
268 mfmsr r5
269 oris r5,r5,MSR_VSX@h
270 mtmsrd r5 /* enable use of VSX now */
271 isync
272
273 cmpdi 0,r3,0
274 beqlr- /* if no previous owner, done */
275 addi r3,r3,THREAD /* want THREAD of task */
276 ld r5,PT_REGS(r3)
277 cmpdi 0,r5,0
278 beq 1f
279 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
280 lis r3,MSR_VSX@h
281 andc r4,r4,r3 /* disable VSX for previous task */
282 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
2831:
284#ifndef CONFIG_SMP
285 li r5,0
286 ld r4,last_task_used_vsx@got(r2)
287 std r5,0(r4)
288#endif /* CONFIG_SMP */
289 blr
290
291#endif /* CONFIG_VSX */
292
293
294/*
295 * The routines below are in assembler so we can closely control the
296 * usage of floating-point registers. These routines must be called
297 * with preempt disabled.
298 */
299#ifdef CONFIG_PPC32
300 .data
301fpzero:
302 .long 0
303fpone:
304 .long 0x3f800000 /* 1.0 in single-precision FP */
305fphalf:
306 .long 0x3f000000 /* 0.5 in single-precision FP */
307
308#define LDCONST(fr, name) \
309 lis r11,name@ha; \
310 lfs fr,name@l(r11)
311#else
312
313 .section ".toc","aw"
314fpzero:
315 .tc FD_0_0[TC],0
316fpone:
317 .tc FD_3ff00000_0[TC],0x3ff0000000000000 /* 1.0 */
318fphalf:
319 .tc FD_3fe00000_0[TC],0x3fe0000000000000 /* 0.5 */
320
321#define LDCONST(fr, name) \
322 lfd fr,name@toc(r2)
323#endif
324
325 .text
326/*
327 * Internal routine to enable floating point and set FPSCR to 0.
328 * Don't call it from C; it doesn't use the normal calling convention.
329 */
330fpenable:
331#ifdef CONFIG_PPC32
332 stwu r1,-64(r1)
333#else
334 stdu r1,-64(r1)
335#endif
336 mfmsr r10
337 ori r11,r10,MSR_FP
338 mtmsr r11
339 isync
340 stfd fr0,24(r1)
341 stfd fr1,16(r1)
342 stfd fr31,8(r1)
343 LDCONST(fr1, fpzero)
344 mffs fr31
345 MTFSF_L(fr1)
346 blr
347
348fpdisable:
349 mtlr r12
350 MTFSF_L(fr31)
351 lfd fr31,8(r1)
352 lfd fr1,16(r1)
353 lfd fr0,24(r1)
354 mtmsr r10
355 isync
356 addi r1,r1,64
357 blr
358
359/*
360 * Vector add, floating point.
361 */
362_GLOBAL(vaddfp)
363 mflr r12
364 bl fpenable
365 li r0,4
366 mtctr r0
367 li r6,0
3681: lfsx fr0,r4,r6
369 lfsx fr1,r5,r6
370 fadds fr0,fr0,fr1
371 stfsx fr0,r3,r6
372 addi r6,r6,4
373 bdnz 1b
374 b fpdisable
375
376/*
377 * Vector subtract, floating point.
378 */
379_GLOBAL(vsubfp)
380 mflr r12
381 bl fpenable
382 li r0,4
383 mtctr r0
384 li r6,0
3851: lfsx fr0,r4,r6
386 lfsx fr1,r5,r6
387 fsubs fr0,fr0,fr1
388 stfsx fr0,r3,r6
389 addi r6,r6,4
390 bdnz 1b
391 b fpdisable
392
393/*
394 * Vector multiply and add, floating point.
395 */
396_GLOBAL(vmaddfp)
397 mflr r12
398 bl fpenable
399 stfd fr2,32(r1)
400 li r0,4
401 mtctr r0
402 li r7,0
4031: lfsx fr0,r4,r7
404 lfsx fr1,r5,r7
405 lfsx fr2,r6,r7
406 fmadds fr0,fr0,fr2,fr1
407 stfsx fr0,r3,r7
408 addi r7,r7,4
409 bdnz 1b
410 lfd fr2,32(r1)
411 b fpdisable
412
413/*
414 * Vector negative multiply and subtract, floating point.
415 */
416_GLOBAL(vnmsubfp)
417 mflr r12
418 bl fpenable
419 stfd fr2,32(r1)
420 li r0,4
421 mtctr r0
422 li r7,0
4231: lfsx fr0,r4,r7
424 lfsx fr1,r5,r7
425 lfsx fr2,r6,r7
426 fnmsubs fr0,fr0,fr2,fr1
427 stfsx fr0,r3,r7
428 addi r7,r7,4
429 bdnz 1b
430 lfd fr2,32(r1)
431 b fpdisable
432
433/*
434 * Vector reciprocal estimate. We just compute 1.0/x.
435 * r3 -> destination, r4 -> source.
436 */
437_GLOBAL(vrefp)
438 mflr r12
439 bl fpenable
440 li r0,4
441 LDCONST(fr1, fpone)
442 mtctr r0
443 li r6,0
4441: lfsx fr0,r4,r6
445 fdivs fr0,fr1,fr0
446 stfsx fr0,r3,r6
447 addi r6,r6,4
448 bdnz 1b
449 b fpdisable
450
451/*
452 * Vector reciprocal square-root estimate, floating point.
453 * We use the frsqrte instruction for the initial estimate followed
454 * by 2 iterations of Newton-Raphson to get sufficient accuracy.
455 * r3 -> destination, r4 -> source.
456 */
457_GLOBAL(vrsqrtefp)
458 mflr r12
459 bl fpenable
460 stfd fr2,32(r1)
461 stfd fr3,40(r1)
462 stfd fr4,48(r1)
463 stfd fr5,56(r1)
464 li r0,4
465 LDCONST(fr4, fpone)
466 LDCONST(fr5, fphalf)
467 mtctr r0
468 li r6,0
4691: lfsx fr0,r4,r6
470 frsqrte fr1,fr0 /* r = frsqrte(s) */
471 fmuls fr3,fr1,fr0 /* r * s */
472 fmuls fr2,fr1,fr5 /* r * 0.5 */
473 fnmsubs fr3,fr1,fr3,fr4 /* 1 - s * r * r */
474 fmadds fr1,fr2,fr3,fr1 /* r = r + 0.5 * r * (1 - s * r * r) */
475 fmuls fr3,fr1,fr0 /* r * s */
476 fmuls fr2,fr1,fr5 /* r * 0.5 */
477 fnmsubs fr3,fr1,fr3,fr4 /* 1 - s * r * r */
478 fmadds fr1,fr2,fr3,fr1 /* r = r + 0.5 * r * (1 - s * r * r) */
479 stfsx fr1,r3,r6
480 addi r6,r6,4
481 bdnz 1b
482 lfd fr5,56(r1)
483 lfd fr4,48(r1)
484 lfd fr3,40(r1)
485 lfd fr2,32(r1)
486 b fpdisable