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1/*
2 * Switch a MMU context.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 */
11#ifndef _ASM_MMU_CONTEXT_H
12#define _ASM_MMU_CONTEXT_H
13
14#include <linux/errno.h>
15#include <linux/sched.h>
16#include <linux/mm_types.h>
17#include <linux/smp.h>
18#include <linux/slab.h>
19
20#include <asm/cacheflush.h>
21#include <asm/dsemul.h>
22#include <asm/hazards.h>
23#include <asm/tlbflush.h>
24#include <asm-generic/mm_hooks.h>
25
26#define htw_set_pwbase(pgd) \
27do { \
28 if (cpu_has_htw) { \
29 write_c0_pwbase(pgd); \
30 back_to_back_c0_hazard(); \
31 } \
32} while (0)
33
34extern void tlbmiss_handler_setup_pgd(unsigned long);
35
36/* Note: This is also implemented with uasm in arch/mips/kvm/entry.c */
37#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
38do { \
39 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \
40 htw_set_pwbase((unsigned long)pgd); \
41} while (0)
42
43#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
44
45#define TLBMISS_HANDLER_RESTORE() \
46 write_c0_xcontext((unsigned long) smp_processor_id() << \
47 SMP_CPUID_REGSHIFT)
48
49#define TLBMISS_HANDLER_SETUP() \
50 do { \
51 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \
52 TLBMISS_HANDLER_RESTORE(); \
53 } while (0)
54
55#else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/
56
57/*
58 * For the fast tlb miss handlers, we keep a per cpu array of pointers
59 * to the current pgd for each processor. Also, the proc. id is stuffed
60 * into the context register.
61 */
62extern unsigned long pgd_current[];
63
64#define TLBMISS_HANDLER_RESTORE() \
65 write_c0_context((unsigned long) smp_processor_id() << \
66 SMP_CPUID_REGSHIFT)
67
68#define TLBMISS_HANDLER_SETUP() \
69 TLBMISS_HANDLER_RESTORE(); \
70 back_to_back_c0_hazard(); \
71 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
72#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
73
74/*
75 * All unused by hardware upper bits will be considered
76 * as a software asid extension.
77 */
78static unsigned long asid_version_mask(unsigned int cpu)
79{
80 unsigned long asid_mask = cpu_asid_mask(&cpu_data[cpu]);
81
82 return ~(asid_mask | (asid_mask - 1));
83}
84
85static unsigned long asid_first_version(unsigned int cpu)
86{
87 return ~asid_version_mask(cpu) + 1;
88}
89
90#define cpu_context(cpu, mm) ((mm)->context.asid[cpu])
91#define asid_cache(cpu) (cpu_data[cpu].asid_cache)
92#define cpu_asid(cpu, mm) \
93 (cpu_context((cpu), (mm)) & cpu_asid_mask(&cpu_data[cpu]))
94
95static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
96{
97}
98
99
100/* Normal, classic MIPS get_new_mmu_context */
101static inline void
102get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
103{
104 unsigned long asid = asid_cache(cpu);
105
106 if (!((asid += cpu_asid_inc()) & cpu_asid_mask(&cpu_data[cpu]))) {
107 if (cpu_has_vtag_icache)
108 flush_icache_all();
109 local_flush_tlb_all(); /* start new asid cycle */
110 if (!asid) /* fix version if needed */
111 asid = asid_first_version(cpu);
112 }
113
114 cpu_context(cpu, mm) = asid_cache(cpu) = asid;
115}
116
117/*
118 * Initialize the context related info for a new mm_struct
119 * instance.
120 */
121static inline int
122init_new_context(struct task_struct *tsk, struct mm_struct *mm)
123{
124 int i;
125
126 for_each_possible_cpu(i)
127 cpu_context(i, mm) = 0;
128
129 atomic_set(&mm->context.fp_mode_switching, 0);
130
131 mm->context.bd_emupage_allocmap = NULL;
132 spin_lock_init(&mm->context.bd_emupage_lock);
133 init_waitqueue_head(&mm->context.bd_emupage_queue);
134
135 return 0;
136}
137
138static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
139 struct task_struct *tsk)
140{
141 unsigned int cpu = smp_processor_id();
142 unsigned long flags;
143 local_irq_save(flags);
144
145 htw_stop();
146 /* Check if our ASID is of an older version and thus invalid */
147 if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & asid_version_mask(cpu))
148 get_new_mmu_context(next, cpu);
149 write_c0_entryhi(cpu_asid(cpu, next));
150 TLBMISS_HANDLER_SETUP_PGD(next->pgd);
151
152 /*
153 * Mark current->active_mm as not "active" anymore.
154 * We don't want to mislead possible IPI tlb flush routines.
155 */
156 cpumask_clear_cpu(cpu, mm_cpumask(prev));
157 cpumask_set_cpu(cpu, mm_cpumask(next));
158 htw_start();
159
160 local_irq_restore(flags);
161}
162
163/*
164 * Destroy context related info for an mm_struct that is about
165 * to be put to rest.
166 */
167static inline void destroy_context(struct mm_struct *mm)
168{
169 dsemul_mm_cleanup(mm);
170}
171
172#define deactivate_mm(tsk, mm) do { } while (0)
173
174/*
175 * After we have set current->mm to a new value, this activates
176 * the context for the new mm so we see the new mappings.
177 */
178static inline void
179activate_mm(struct mm_struct *prev, struct mm_struct *next)
180{
181 unsigned long flags;
182 unsigned int cpu = smp_processor_id();
183
184 local_irq_save(flags);
185
186 htw_stop();
187 /* Unconditionally get a new ASID. */
188 get_new_mmu_context(next, cpu);
189
190 write_c0_entryhi(cpu_asid(cpu, next));
191 TLBMISS_HANDLER_SETUP_PGD(next->pgd);
192
193 /* mark mmu ownership change */
194 cpumask_clear_cpu(cpu, mm_cpumask(prev));
195 cpumask_set_cpu(cpu, mm_cpumask(next));
196 htw_start();
197
198 local_irq_restore(flags);
199}
200
201/*
202 * If mm is currently active_mm, we can't really drop it. Instead,
203 * we will get a new one for it.
204 */
205static inline void
206drop_mmu_context(struct mm_struct *mm, unsigned cpu)
207{
208 unsigned long flags;
209
210 local_irq_save(flags);
211 htw_stop();
212
213 if (cpumask_test_cpu(cpu, mm_cpumask(mm))) {
214 get_new_mmu_context(mm, cpu);
215 write_c0_entryhi(cpu_asid(cpu, mm));
216 } else {
217 /* will get a new context next time */
218 cpu_context(cpu, mm) = 0;
219 }
220 htw_start();
221 local_irq_restore(flags);
222}
223
224#endif /* _ASM_MMU_CONTEXT_H */
1/*
2 * Switch a MMU context.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 */
11#ifndef _ASM_MMU_CONTEXT_H
12#define _ASM_MMU_CONTEXT_H
13
14#include <linux/errno.h>
15#include <linux/sched.h>
16#include <linux/smp.h>
17#include <linux/slab.h>
18#include <asm/cacheflush.h>
19#include <asm/hazards.h>
20#include <asm/tlbflush.h>
21#ifdef CONFIG_MIPS_MT_SMTC
22#include <asm/mipsmtregs.h>
23#include <asm/smtc.h>
24#endif /* SMTC */
25#include <asm-generic/mm_hooks.h>
26
27#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
28do { \
29 extern void tlbmiss_handler_setup_pgd(unsigned long); \
30 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \
31} while (0)
32
33#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
34#define TLBMISS_HANDLER_SETUP() \
35 do { \
36 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \
37 write_c0_xcontext((unsigned long) smp_processor_id() << \
38 SMP_CPUID_REGSHIFT); \
39 } while (0)
40
41#else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/
42
43/*
44 * For the fast tlb miss handlers, we keep a per cpu array of pointers
45 * to the current pgd for each processor. Also, the proc. id is stuffed
46 * into the context register.
47 */
48extern unsigned long pgd_current[];
49
50#define TLBMISS_HANDLER_SETUP() \
51 write_c0_context((unsigned long) smp_processor_id() << \
52 SMP_CPUID_REGSHIFT); \
53 back_to_back_c0_hazard(); \
54 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
55#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
56#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
57
58#define ASID_INC 0x40
59#define ASID_MASK 0xfc0
60
61#elif defined(CONFIG_CPU_R8000)
62
63#define ASID_INC 0x10
64#define ASID_MASK 0xff0
65
66#elif defined(CONFIG_MIPS_MT_SMTC)
67
68#define ASID_INC 0x1
69extern unsigned long smtc_asid_mask;
70#define ASID_MASK (smtc_asid_mask)
71#define HW_ASID_MASK 0xff
72/* End SMTC/34K debug hack */
73#else /* FIXME: not correct for R6000 */
74
75#define ASID_INC 0x1
76#define ASID_MASK 0xff
77
78#endif
79
80#define cpu_context(cpu, mm) ((mm)->context.asid[cpu])
81#define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK)
82#define asid_cache(cpu) (cpu_data[cpu].asid_cache)
83
84static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
85{
86}
87
88/*
89 * All unused by hardware upper bits will be considered
90 * as a software asid extension.
91 */
92#define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1)))
93#define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)
94
95#ifndef CONFIG_MIPS_MT_SMTC
96/* Normal, classic MIPS get_new_mmu_context */
97static inline void
98get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
99{
100 extern void kvm_local_flush_tlb_all(void);
101 unsigned long asid = asid_cache(cpu);
102
103 if (! ((asid += ASID_INC) & ASID_MASK) ) {
104 if (cpu_has_vtag_icache)
105 flush_icache_all();
106#ifdef CONFIG_KVM
107 kvm_local_flush_tlb_all(); /* start new asid cycle */
108#else
109 local_flush_tlb_all(); /* start new asid cycle */
110#endif
111 if (!asid) /* fix version if needed */
112 asid = ASID_FIRST_VERSION;
113 }
114
115 cpu_context(cpu, mm) = asid_cache(cpu) = asid;
116}
117
118#else /* CONFIG_MIPS_MT_SMTC */
119
120#define get_new_mmu_context(mm, cpu) smtc_get_new_mmu_context((mm), (cpu))
121
122#endif /* CONFIG_MIPS_MT_SMTC */
123
124/*
125 * Initialize the context related info for a new mm_struct
126 * instance.
127 */
128static inline int
129init_new_context(struct task_struct *tsk, struct mm_struct *mm)
130{
131 int i;
132
133 for_each_possible_cpu(i)
134 cpu_context(i, mm) = 0;
135
136 return 0;
137}
138
139static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
140 struct task_struct *tsk)
141{
142 unsigned int cpu = smp_processor_id();
143 unsigned long flags;
144#ifdef CONFIG_MIPS_MT_SMTC
145 unsigned long oldasid;
146 unsigned long mtflags;
147 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
148 local_irq_save(flags);
149 mtflags = dvpe();
150#else /* Not SMTC */
151 local_irq_save(flags);
152#endif /* CONFIG_MIPS_MT_SMTC */
153
154 /* Check if our ASID is of an older version and thus invalid */
155 if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK)
156 get_new_mmu_context(next, cpu);
157#ifdef CONFIG_MIPS_MT_SMTC
158 /*
159 * If the EntryHi ASID being replaced happens to be
160 * the value flagged at ASID recycling time as having
161 * an extended life, clear the bit showing it being
162 * in use by this "CPU", and if that's the last bit,
163 * free up the ASID value for use and flush any old
164 * instances of it from the TLB.
165 */
166 oldasid = (read_c0_entryhi() & ASID_MASK);
167 if(smtc_live_asid[mytlb][oldasid]) {
168 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
169 if(smtc_live_asid[mytlb][oldasid] == 0)
170 smtc_flush_tlb_asid(oldasid);
171 }
172 /*
173 * Tread softly on EntryHi, and so long as we support
174 * having ASID_MASK smaller than the hardware maximum,
175 * make sure no "soft" bits become "hard"...
176 */
177 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
178 cpu_asid(cpu, next));
179 ehb(); /* Make sure it propagates to TCStatus */
180 evpe(mtflags);
181#else
182 write_c0_entryhi(cpu_asid(cpu, next));
183#endif /* CONFIG_MIPS_MT_SMTC */
184 TLBMISS_HANDLER_SETUP_PGD(next->pgd);
185
186 /*
187 * Mark current->active_mm as not "active" anymore.
188 * We don't want to mislead possible IPI tlb flush routines.
189 */
190 cpumask_clear_cpu(cpu, mm_cpumask(prev));
191 cpumask_set_cpu(cpu, mm_cpumask(next));
192
193 local_irq_restore(flags);
194}
195
196/*
197 * Destroy context related info for an mm_struct that is about
198 * to be put to rest.
199 */
200static inline void destroy_context(struct mm_struct *mm)
201{
202}
203
204#define deactivate_mm(tsk, mm) do { } while (0)
205
206/*
207 * After we have set current->mm to a new value, this activates
208 * the context for the new mm so we see the new mappings.
209 */
210static inline void
211activate_mm(struct mm_struct *prev, struct mm_struct *next)
212{
213 unsigned long flags;
214 unsigned int cpu = smp_processor_id();
215
216#ifdef CONFIG_MIPS_MT_SMTC
217 unsigned long oldasid;
218 unsigned long mtflags;
219 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
220#endif /* CONFIG_MIPS_MT_SMTC */
221
222 local_irq_save(flags);
223
224 /* Unconditionally get a new ASID. */
225 get_new_mmu_context(next, cpu);
226
227#ifdef CONFIG_MIPS_MT_SMTC
228 /* See comments for similar code above */
229 mtflags = dvpe();
230 oldasid = read_c0_entryhi() & ASID_MASK;
231 if(smtc_live_asid[mytlb][oldasid]) {
232 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
233 if(smtc_live_asid[mytlb][oldasid] == 0)
234 smtc_flush_tlb_asid(oldasid);
235 }
236 /* See comments for similar code above */
237 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
238 cpu_asid(cpu, next));
239 ehb(); /* Make sure it propagates to TCStatus */
240 evpe(mtflags);
241#else
242 write_c0_entryhi(cpu_asid(cpu, next));
243#endif /* CONFIG_MIPS_MT_SMTC */
244 TLBMISS_HANDLER_SETUP_PGD(next->pgd);
245
246 /* mark mmu ownership change */
247 cpumask_clear_cpu(cpu, mm_cpumask(prev));
248 cpumask_set_cpu(cpu, mm_cpumask(next));
249
250 local_irq_restore(flags);
251}
252
253/*
254 * If mm is currently active_mm, we can't really drop it. Instead,
255 * we will get a new one for it.
256 */
257static inline void
258drop_mmu_context(struct mm_struct *mm, unsigned cpu)
259{
260 unsigned long flags;
261#ifdef CONFIG_MIPS_MT_SMTC
262 unsigned long oldasid;
263 /* Can't use spinlock because called from TLB flush within DVPE */
264 unsigned int prevvpe;
265 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
266#endif /* CONFIG_MIPS_MT_SMTC */
267
268 local_irq_save(flags);
269
270 if (cpumask_test_cpu(cpu, mm_cpumask(mm))) {
271 get_new_mmu_context(mm, cpu);
272#ifdef CONFIG_MIPS_MT_SMTC
273 /* See comments for similar code above */
274 prevvpe = dvpe();
275 oldasid = (read_c0_entryhi() & ASID_MASK);
276 if (smtc_live_asid[mytlb][oldasid]) {
277 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
278 if(smtc_live_asid[mytlb][oldasid] == 0)
279 smtc_flush_tlb_asid(oldasid);
280 }
281 /* See comments for similar code above */
282 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK)
283 | cpu_asid(cpu, mm));
284 ehb(); /* Make sure it propagates to TCStatus */
285 evpe(prevvpe);
286#else /* not CONFIG_MIPS_MT_SMTC */
287 write_c0_entryhi(cpu_asid(cpu, mm));
288#endif /* CONFIG_MIPS_MT_SMTC */
289 } else {
290 /* will get a new context next time */
291#ifndef CONFIG_MIPS_MT_SMTC
292 cpu_context(cpu, mm) = 0;
293#else /* SMTC */
294 int i;
295
296 /* SMTC shares the TLB (and ASIDs) across VPEs */
297 for_each_online_cpu(i) {
298 if((smtc_status & SMTC_TLB_SHARED)
299 || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))
300 cpu_context(i, mm) = 0;
301 }
302#endif /* CONFIG_MIPS_MT_SMTC */
303 }
304 local_irq_restore(flags);
305}
306
307#endif /* _ASM_MMU_CONTEXT_H */