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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * cpu.h: Values of the PRId register used to match up
4 * various MIPS cpu types.
5 *
6 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
7 * Copyright (C) 2004, 2013 Maciej W. Rozycki
8 */
9#ifndef _ASM_CPU_H
10#define _ASM_CPU_H
11
12/*
13 As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0
14 register 15, select 0) is defined in this (backwards compatible) way:
15
16 +----------------+----------------+----------------+----------------+
17 | Company Options| Company ID | Processor ID | Revision |
18 +----------------+----------------+----------------+----------------+
19 31 24 23 16 15 8 7
20
21 I don't have docs for all the previous processors, but my impression is
22 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
23 spec.
24*/
25
26#define PRID_OPT_MASK 0xff000000
27
28/*
29 * Assigned Company values for bits 23:16 of the PRId register.
30 */
31
32#define PRID_COMP_MASK 0xff0000
33
34#define PRID_COMP_LEGACY 0x000000
35#define PRID_COMP_MIPS 0x010000
36#define PRID_COMP_BROADCOM 0x020000
37#define PRID_COMP_ALCHEMY 0x030000
38#define PRID_COMP_SIBYTE 0x040000
39#define PRID_COMP_SANDCRAFT 0x050000
40#define PRID_COMP_NXP 0x060000
41#define PRID_COMP_TOSHIBA 0x070000
42#define PRID_COMP_LSI 0x080000
43#define PRID_COMP_LEXRA 0x0b0000
44#define PRID_COMP_NETLOGIC 0x0c0000
45#define PRID_COMP_CAVIUM 0x0d0000
46#define PRID_COMP_LOONGSON 0x140000
47#define PRID_COMP_INGENIC_D0 0xd00000 /* JZ4740, JZ4750 */
48#define PRID_COMP_INGENIC_D1 0xd10000 /* JZ4770, JZ4775 */
49#define PRID_COMP_INGENIC_E1 0xe10000 /* JZ4780 */
50
51/*
52 * Assigned Processor ID (implementation) values for bits 15:8 of the PRId
53 * register. In order to detect a certain CPU type exactly eventually
54 * additional registers may need to be examined.
55 */
56
57#define PRID_IMP_MASK 0xff00
58
59/*
60 * These are valid when 23:16 == PRID_COMP_LEGACY
61 */
62
63#define PRID_IMP_R2000 0x0100
64#define PRID_IMP_AU1_REV1 0x0100
65#define PRID_IMP_AU1_REV2 0x0200
66#define PRID_IMP_R3000 0x0200 /* Same as R2000A */
67#define PRID_IMP_R6000 0x0300 /* Same as R3000A */
68#define PRID_IMP_R4000 0x0400
69#define PRID_IMP_R6000A 0x0600
70#define PRID_IMP_R10000 0x0900
71#define PRID_IMP_R4300 0x0b00
72#define PRID_IMP_VR41XX 0x0c00
73#define PRID_IMP_R12000 0x0e00
74#define PRID_IMP_R14000 0x0f00 /* R14K && R16K */
75#define PRID_IMP_R8000 0x1000
76#define PRID_IMP_PR4450 0x1200
77#define PRID_IMP_R4600 0x2000
78#define PRID_IMP_R4700 0x2100
79#define PRID_IMP_TX39 0x2200
80#define PRID_IMP_R4640 0x2200
81#define PRID_IMP_R4650 0x2200 /* Same as R4640 */
82#define PRID_IMP_R5000 0x2300
83#define PRID_IMP_TX49 0x2d00
84#define PRID_IMP_SONIC 0x2400
85#define PRID_IMP_MAGIC 0x2500
86#define PRID_IMP_RM7000 0x2700
87#define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
88#define PRID_IMP_RM9000 0x3400
89#define PRID_IMP_LOONGSON_32 0x4200 /* Loongson-1 */
90#define PRID_IMP_R5432 0x5400
91#define PRID_IMP_R5500 0x5500
92#define PRID_IMP_LOONGSON_64 0x6300 /* Loongson-2/3 */
93
94#define PRID_IMP_UNKNOWN 0xff00
95
96/*
97 * These are the PRID's for when 23:16 == PRID_COMP_MIPS
98 */
99
100#define PRID_IMP_QEMU_GENERIC 0x0000
101#define PRID_IMP_4KC 0x8000
102#define PRID_IMP_5KC 0x8100
103#define PRID_IMP_20KC 0x8200
104#define PRID_IMP_4KEC 0x8400
105#define PRID_IMP_4KSC 0x8600
106#define PRID_IMP_25KF 0x8800
107#define PRID_IMP_5KE 0x8900
108#define PRID_IMP_4KECR2 0x9000
109#define PRID_IMP_4KEMPR2 0x9100
110#define PRID_IMP_4KSD 0x9200
111#define PRID_IMP_24K 0x9300
112#define PRID_IMP_34K 0x9500
113#define PRID_IMP_24KE 0x9600
114#define PRID_IMP_74K 0x9700
115#define PRID_IMP_1004K 0x9900
116#define PRID_IMP_1074K 0x9a00
117#define PRID_IMP_M14KC 0x9c00
118#define PRID_IMP_M14KEC 0x9e00
119#define PRID_IMP_INTERAPTIV_UP 0xa000
120#define PRID_IMP_INTERAPTIV_MP 0xa100
121#define PRID_IMP_PROAPTIV_UP 0xa200
122#define PRID_IMP_PROAPTIV_MP 0xa300
123#define PRID_IMP_P6600 0xa400
124#define PRID_IMP_M5150 0xa700
125#define PRID_IMP_P5600 0xa800
126#define PRID_IMP_I6400 0xa900
127#define PRID_IMP_M6250 0xab00
128#define PRID_IMP_I6500 0xb000
129
130/*
131 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
132 */
133
134#define PRID_IMP_SB1 0x0100
135#define PRID_IMP_SB1A 0x1100
136
137/*
138 * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
139 */
140
141#define PRID_IMP_SR71000 0x0400
142
143/*
144 * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
145 */
146
147#define PRID_IMP_BMIPS32_REV4 0x4000
148#define PRID_IMP_BMIPS32_REV8 0x8000
149#define PRID_IMP_BMIPS3300 0x9000
150#define PRID_IMP_BMIPS3300_ALT 0x9100
151#define PRID_IMP_BMIPS3300_BUG 0x0000
152#define PRID_IMP_BMIPS43XX 0xa000
153#define PRID_IMP_BMIPS5000 0x5a00
154#define PRID_IMP_BMIPS5200 0x5b00
155
156#define PRID_REV_BMIPS4380_LO 0x0040
157#define PRID_REV_BMIPS4380_HI 0x006f
158
159/*
160 * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
161 */
162
163#define PRID_IMP_CAVIUM_CN38XX 0x0000
164#define PRID_IMP_CAVIUM_CN31XX 0x0100
165#define PRID_IMP_CAVIUM_CN30XX 0x0200
166#define PRID_IMP_CAVIUM_CN58XX 0x0300
167#define PRID_IMP_CAVIUM_CN56XX 0x0400
168#define PRID_IMP_CAVIUM_CN50XX 0x0600
169#define PRID_IMP_CAVIUM_CN52XX 0x0700
170#define PRID_IMP_CAVIUM_CN63XX 0x9000
171#define PRID_IMP_CAVIUM_CN68XX 0x9100
172#define PRID_IMP_CAVIUM_CN66XX 0x9200
173#define PRID_IMP_CAVIUM_CN61XX 0x9300
174#define PRID_IMP_CAVIUM_CNF71XX 0x9400
175#define PRID_IMP_CAVIUM_CN78XX 0x9500
176#define PRID_IMP_CAVIUM_CN70XX 0x9600
177#define PRID_IMP_CAVIUM_CN73XX 0x9700
178#define PRID_IMP_CAVIUM_CNF75XX 0x9800
179
180/*
181 * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
182 */
183
184#define PRID_IMP_JZRISC 0x0200
185
186/*
187 * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
188 */
189#define PRID_IMP_NETLOGIC_XLR732 0x0000
190#define PRID_IMP_NETLOGIC_XLR716 0x0200
191#define PRID_IMP_NETLOGIC_XLR532 0x0900
192#define PRID_IMP_NETLOGIC_XLR308 0x0600
193#define PRID_IMP_NETLOGIC_XLR532C 0x0800
194#define PRID_IMP_NETLOGIC_XLR516C 0x0a00
195#define PRID_IMP_NETLOGIC_XLR508C 0x0b00
196#define PRID_IMP_NETLOGIC_XLR308C 0x0f00
197#define PRID_IMP_NETLOGIC_XLS608 0x8000
198#define PRID_IMP_NETLOGIC_XLS408 0x8800
199#define PRID_IMP_NETLOGIC_XLS404 0x8c00
200#define PRID_IMP_NETLOGIC_XLS208 0x8e00
201#define PRID_IMP_NETLOGIC_XLS204 0x8f00
202#define PRID_IMP_NETLOGIC_XLS108 0xce00
203#define PRID_IMP_NETLOGIC_XLS104 0xcf00
204#define PRID_IMP_NETLOGIC_XLS616B 0x4000
205#define PRID_IMP_NETLOGIC_XLS608B 0x4a00
206#define PRID_IMP_NETLOGIC_XLS416B 0x4400
207#define PRID_IMP_NETLOGIC_XLS412B 0x4c00
208#define PRID_IMP_NETLOGIC_XLS408B 0x4e00
209#define PRID_IMP_NETLOGIC_XLS404B 0x4f00
210#define PRID_IMP_NETLOGIC_AU13XX 0x8000
211
212#define PRID_IMP_NETLOGIC_XLP8XX 0x1000
213#define PRID_IMP_NETLOGIC_XLP3XX 0x1100
214#define PRID_IMP_NETLOGIC_XLP2XX 0x1200
215#define PRID_IMP_NETLOGIC_XLP9XX 0x1500
216#define PRID_IMP_NETLOGIC_XLP5XX 0x1300
217
218/*
219 * Particular Revision values for bits 7:0 of the PRId register.
220 */
221
222#define PRID_REV_MASK 0x00ff
223
224/*
225 * Definitions for 7:0 on legacy processors
226 */
227
228#define PRID_REV_TX4927 0x0022
229#define PRID_REV_TX4937 0x0030
230#define PRID_REV_R4400 0x0040
231#define PRID_REV_R3000A 0x0030
232#define PRID_REV_R3000 0x0020
233#define PRID_REV_R2000A 0x0010
234#define PRID_REV_TX3912 0x0010
235#define PRID_REV_TX3922 0x0030
236#define PRID_REV_TX3927 0x0040
237#define PRID_REV_VR4111 0x0050
238#define PRID_REV_VR4181 0x0050 /* Same as VR4111 */
239#define PRID_REV_VR4121 0x0060
240#define PRID_REV_VR4122 0x0070
241#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
242#define PRID_REV_VR4130 0x0080
243#define PRID_REV_34K_V1_0_2 0x0022
244#define PRID_REV_LOONGSON1B 0x0020
245#define PRID_REV_LOONGSON1C 0x0020 /* Same as Loongson-1B */
246#define PRID_REV_LOONGSON2E 0x0002
247#define PRID_REV_LOONGSON2F 0x0003
248#define PRID_REV_LOONGSON3A_R1 0x0005
249#define PRID_REV_LOONGSON3B_R1 0x0006
250#define PRID_REV_LOONGSON3B_R2 0x0007
251#define PRID_REV_LOONGSON3A_R2 0x0008
252#define PRID_REV_LOONGSON3A_R3 0x0009
253
254/*
255 * Older processors used to encode processor version and revision in two
256 * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
257 * have switched to use the 8-bits as 3:3:2 bitfield with the last field as
258 * the patch number. *ARGH*
259 */
260#define PRID_REV_ENCODE_44(ver, rev) \
261 ((ver) << 4 | (rev))
262#define PRID_REV_ENCODE_332(ver, rev, patch) \
263 ((ver) << 5 | (rev) << 2 | (patch))
264
265/*
266 * FPU implementation/revision register (CP1 control register 0).
267 *
268 * +---------------------------------+----------------+----------------+
269 * | 0 | Implementation | Revision |
270 * +---------------------------------+----------------+----------------+
271 * 31 16 15 8 7 0
272 */
273
274#define FPIR_IMP_MASK 0xff00
275
276#define FPIR_IMP_NONE 0x0000
277
278#if !defined(__ASSEMBLY__)
279
280enum cpu_type_enum {
281 CPU_UNKNOWN,
282
283 /*
284 * R2000 class processors
285 */
286 CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052,
287 CPU_R3081, CPU_R3081E,
288
289 /*
290 * R4000 class processors
291 */
292 CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
293 CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
294 CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000,
295 CPU_R12000, CPU_R14000, CPU_R16000, CPU_VR41XX, CPU_VR4111, CPU_VR4121,
296 CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
297 CPU_SR71000, CPU_TX49XX,
298
299 /*
300 * R8000 class processors
301 */
302 CPU_R8000,
303
304 /*
305 * TX3900 class processors
306 */
307 CPU_TX3912, CPU_TX3922, CPU_TX3927,
308
309 /*
310 * MIPS32 class processors
311 */
312 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
313 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
314 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
315 CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K,
316 CPU_M5150, CPU_I6400, CPU_P6600, CPU_M6250,
317
318 /*
319 * MIPS64 class processors
320 */
321 CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
322 CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
323 CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, CPU_I6500,
324
325 CPU_QEMU_GENERIC,
326
327 CPU_LAST
328};
329
330#endif /* !__ASSEMBLY */
331
332/*
333 * ISA Level encodings
334 *
335 */
336#define MIPS_CPU_ISA_II 0x00000001
337#define MIPS_CPU_ISA_III 0x00000002
338#define MIPS_CPU_ISA_IV 0x00000004
339#define MIPS_CPU_ISA_V 0x00000008
340#define MIPS_CPU_ISA_M32R1 0x00000010
341#define MIPS_CPU_ISA_M32R2 0x00000020
342#define MIPS_CPU_ISA_M64R1 0x00000040
343#define MIPS_CPU_ISA_M64R2 0x00000080
344#define MIPS_CPU_ISA_M32R6 0x00000100
345#define MIPS_CPU_ISA_M64R6 0x00000200
346
347#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \
348 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M32R6)
349#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
350 MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2 | \
351 MIPS_CPU_ISA_M64R6)
352
353/*
354 * Private version of BIT_ULL() to escape include file recursion hell.
355 * We soon will have to switch to another mechanism that will work with
356 * more than 64 bits anyway.
357 */
358#define MBIT_ULL(bit) (1ULL << (bit))
359
360/*
361 * CPU Option encodings
362 */
363#define MIPS_CPU_TLB MBIT_ULL( 0) /* CPU has TLB */
364#define MIPS_CPU_4KEX MBIT_ULL( 1) /* "R4K" exception model */
365#define MIPS_CPU_3K_CACHE MBIT_ULL( 2) /* R3000-style caches */
366#define MIPS_CPU_4K_CACHE MBIT_ULL( 3) /* R4000-style caches */
367#define MIPS_CPU_TX39_CACHE MBIT_ULL( 4) /* TX3900-style caches */
368#define MIPS_CPU_FPU MBIT_ULL( 5) /* CPU has FPU */
369#define MIPS_CPU_32FPR MBIT_ULL( 6) /* 32 dbl. prec. FP registers */
370#define MIPS_CPU_COUNTER MBIT_ULL( 7) /* Cycle count/compare */
371#define MIPS_CPU_WATCH MBIT_ULL( 8) /* watchpoint registers */
372#define MIPS_CPU_DIVEC MBIT_ULL( 9) /* dedicated interrupt vector */
373#define MIPS_CPU_VCE MBIT_ULL(10) /* virt. coherence conflict possible */
374#define MIPS_CPU_CACHE_CDEX_P MBIT_ULL(11) /* Create_Dirty_Exclusive CACHE op */
375#define MIPS_CPU_CACHE_CDEX_S MBIT_ULL(12) /* ... same for seconary cache ... */
376#define MIPS_CPU_MCHECK MBIT_ULL(13) /* Machine check exception */
377#define MIPS_CPU_EJTAG MBIT_ULL(14) /* EJTAG exception */
378#define MIPS_CPU_NOFPUEX MBIT_ULL(15) /* no FPU exception */
379#define MIPS_CPU_LLSC MBIT_ULL(16) /* CPU has ll/sc instructions */
380#define MIPS_CPU_INCLUSIVE_CACHES MBIT_ULL(17) /* P-cache subset enforced */
381#define MIPS_CPU_PREFETCH MBIT_ULL(18) /* CPU has usable prefetch */
382#define MIPS_CPU_VINT MBIT_ULL(19) /* CPU supports MIPSR2 vectored interrupts */
383#define MIPS_CPU_VEIC MBIT_ULL(20) /* CPU supports MIPSR2 external interrupt controller mode */
384#define MIPS_CPU_ULRI MBIT_ULL(21) /* CPU has ULRI feature */
385#define MIPS_CPU_PCI MBIT_ULL(22) /* CPU has Perf Ctr Int indicator */
386#define MIPS_CPU_RIXI MBIT_ULL(23) /* CPU has TLB Read/eXec Inhibit */
387#define MIPS_CPU_MICROMIPS MBIT_ULL(24) /* CPU has microMIPS capability */
388#define MIPS_CPU_TLBINV MBIT_ULL(25) /* CPU supports TLBINV/F */
389#define MIPS_CPU_SEGMENTS MBIT_ULL(26) /* CPU supports Segmentation Control registers */
390#define MIPS_CPU_EVA MBIT_ULL(27) /* CPU supports Enhanced Virtual Addressing */
391#define MIPS_CPU_HTW MBIT_ULL(28) /* CPU support Hardware Page Table Walker */
392#define MIPS_CPU_RIXIEX MBIT_ULL(29) /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
393#define MIPS_CPU_MAAR MBIT_ULL(30) /* MAAR(I) registers are present */
394#define MIPS_CPU_FRE MBIT_ULL(31) /* FRE & UFE bits implemented */
395#define MIPS_CPU_RW_LLB MBIT_ULL(32) /* LLADDR/LLB writes are allowed */
396#define MIPS_CPU_LPA MBIT_ULL(33) /* CPU supports Large Physical Addressing */
397#define MIPS_CPU_CDMM MBIT_ULL(34) /* CPU has Common Device Memory Map */
398#define MIPS_CPU_BP_GHIST MBIT_ULL(35) /* R12K+ Branch Prediction Global History */
399#define MIPS_CPU_SP MBIT_ULL(36) /* Small (1KB) page support */
400#define MIPS_CPU_FTLB MBIT_ULL(37) /* CPU has Fixed-page-size TLB */
401#define MIPS_CPU_NAN_LEGACY MBIT_ULL(38) /* Legacy NaN implemented */
402#define MIPS_CPU_NAN_2008 MBIT_ULL(39) /* 2008 NaN implemented */
403#define MIPS_CPU_VP MBIT_ULL(40) /* MIPSr6 Virtual Processors (multi-threading) */
404#define MIPS_CPU_LDPTE MBIT_ULL(41) /* CPU has ldpte/lddir instructions */
405#define MIPS_CPU_MVH MBIT_ULL(42) /* CPU supports MFHC0/MTHC0 */
406#define MIPS_CPU_EBASE_WG MBIT_ULL(43) /* CPU has EBase.WG */
407#define MIPS_CPU_BADINSTR MBIT_ULL(44) /* CPU has BadInstr register */
408#define MIPS_CPU_BADINSTRP MBIT_ULL(45) /* CPU has BadInstrP register */
409#define MIPS_CPU_CTXTC MBIT_ULL(46) /* CPU has [X]ConfigContext registers */
410#define MIPS_CPU_PERF MBIT_ULL(47) /* CPU has MIPS performance counters */
411#define MIPS_CPU_GUESTCTL0EXT MBIT_ULL(48) /* CPU has VZ GuestCtl0Ext register */
412#define MIPS_CPU_GUESTCTL1 MBIT_ULL(49) /* CPU has VZ GuestCtl1 register */
413#define MIPS_CPU_GUESTCTL2 MBIT_ULL(50) /* CPU has VZ GuestCtl2 register */
414#define MIPS_CPU_GUESTID MBIT_ULL(51) /* CPU uses VZ ASE GuestID feature */
415#define MIPS_CPU_DRG MBIT_ULL(52) /* CPU has VZ Direct Root to Guest (DRG) */
416#define MIPS_CPU_UFR MBIT_ULL(53) /* CPU supports User mode FR switching */
417#define MIPS_CPU_SHARED_FTLB_RAM \
418 MBIT_ULL(54) /* CPU shares FTLB RAM with another */
419#define MIPS_CPU_SHARED_FTLB_ENTRIES \
420 MBIT_ULL(55) /* CPU shares FTLB entries with another */
421
422/*
423 * CPU ASE encodings
424 */
425#define MIPS_ASE_MIPS16 0x00000001 /* code compression */
426#define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */
427#define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */
428#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */
429#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */
430#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */
431#define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */
432#define MIPS_ASE_VZ 0x00000080 /* Virtualization ASE */
433#define MIPS_ASE_MSA 0x00000100 /* MIPS SIMD Architecture */
434#define MIPS_ASE_DSP3 0x00000200 /* Signal Processing ASE Rev 3*/
435#define MIPS_ASE_MIPS16E2 0x00000400 /* MIPS16e2 */
436
437#endif /* _ASM_CPU_H */
1/*
2 * cpu.h: Values of the PRId register used to match up
3 * various MIPS cpu types.
4 *
5 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
6 * Copyright (C) 2004, 2013 Maciej W. Rozycki
7 */
8#ifndef _ASM_CPU_H
9#define _ASM_CPU_H
10
11/*
12 As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0
13 register 15, select 0) is defined in this (backwards compatible) way:
14
15 +----------------+----------------+----------------+----------------+
16 | Company Options| Company ID | Processor ID | Revision |
17 +----------------+----------------+----------------+----------------+
18 31 24 23 16 15 8 7
19
20 I don't have docs for all the previous processors, but my impression is
21 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
22 spec.
23*/
24
25#define PRID_OPT_MASK 0xff000000
26
27/*
28 * Assigned Company values for bits 23:16 of the PRId register.
29 */
30
31#define PRID_COMP_MASK 0xff0000
32
33#define PRID_COMP_LEGACY 0x000000
34#define PRID_COMP_MIPS 0x010000
35#define PRID_COMP_BROADCOM 0x020000
36#define PRID_COMP_ALCHEMY 0x030000
37#define PRID_COMP_SIBYTE 0x040000
38#define PRID_COMP_SANDCRAFT 0x050000
39#define PRID_COMP_NXP 0x060000
40#define PRID_COMP_TOSHIBA 0x070000
41#define PRID_COMP_LSI 0x080000
42#define PRID_COMP_LEXRA 0x0b0000
43#define PRID_COMP_NETLOGIC 0x0c0000
44#define PRID_COMP_CAVIUM 0x0d0000
45#define PRID_COMP_INGENIC 0xd00000
46
47/*
48 * Assigned Processor ID (implementation) values for bits 15:8 of the PRId
49 * register. In order to detect a certain CPU type exactly eventually
50 * additional registers may need to be examined.
51 */
52
53#define PRID_IMP_MASK 0xff00
54
55/*
56 * These are valid when 23:16 == PRID_COMP_LEGACY
57 */
58
59#define PRID_IMP_R2000 0x0100
60#define PRID_IMP_AU1_REV1 0x0100
61#define PRID_IMP_AU1_REV2 0x0200
62#define PRID_IMP_R3000 0x0200 /* Same as R2000A */
63#define PRID_IMP_R6000 0x0300 /* Same as R3000A */
64#define PRID_IMP_R4000 0x0400
65#define PRID_IMP_R6000A 0x0600
66#define PRID_IMP_R10000 0x0900
67#define PRID_IMP_R4300 0x0b00
68#define PRID_IMP_VR41XX 0x0c00
69#define PRID_IMP_R12000 0x0e00
70#define PRID_IMP_R14000 0x0f00
71#define PRID_IMP_R8000 0x1000
72#define PRID_IMP_PR4450 0x1200
73#define PRID_IMP_R4600 0x2000
74#define PRID_IMP_R4700 0x2100
75#define PRID_IMP_TX39 0x2200
76#define PRID_IMP_R4640 0x2200
77#define PRID_IMP_R4650 0x2200 /* Same as R4640 */
78#define PRID_IMP_R5000 0x2300
79#define PRID_IMP_TX49 0x2d00
80#define PRID_IMP_SONIC 0x2400
81#define PRID_IMP_MAGIC 0x2500
82#define PRID_IMP_RM7000 0x2700
83#define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
84#define PRID_IMP_RM9000 0x3400
85#define PRID_IMP_LOONGSON_32 0x4200 /* Loongson-1 */
86#define PRID_IMP_R5432 0x5400
87#define PRID_IMP_R5500 0x5500
88#define PRID_IMP_LOONGSON_64 0x6300 /* Loongson-2/3 */
89
90#define PRID_IMP_UNKNOWN 0xff00
91
92/*
93 * These are the PRID's for when 23:16 == PRID_COMP_MIPS
94 */
95
96#define PRID_IMP_4KC 0x8000
97#define PRID_IMP_5KC 0x8100
98#define PRID_IMP_20KC 0x8200
99#define PRID_IMP_4KEC 0x8400
100#define PRID_IMP_4KSC 0x8600
101#define PRID_IMP_25KF 0x8800
102#define PRID_IMP_5KE 0x8900
103#define PRID_IMP_4KECR2 0x9000
104#define PRID_IMP_4KEMPR2 0x9100
105#define PRID_IMP_4KSD 0x9200
106#define PRID_IMP_24K 0x9300
107#define PRID_IMP_34K 0x9500
108#define PRID_IMP_24KE 0x9600
109#define PRID_IMP_74K 0x9700
110#define PRID_IMP_1004K 0x9900
111#define PRID_IMP_1074K 0x9a00
112#define PRID_IMP_M14KC 0x9c00
113#define PRID_IMP_M14KEC 0x9e00
114#define PRID_IMP_INTERAPTIV_UP 0xa000
115#define PRID_IMP_INTERAPTIV_MP 0xa100
116#define PRID_IMP_PROAPTIV_UP 0xa200
117#define PRID_IMP_PROAPTIV_MP 0xa300
118#define PRID_IMP_M5150 0xa700
119#define PRID_IMP_P5600 0xa800
120
121/*
122 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
123 */
124
125#define PRID_IMP_SB1 0x0100
126#define PRID_IMP_SB1A 0x1100
127
128/*
129 * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
130 */
131
132#define PRID_IMP_SR71000 0x0400
133
134/*
135 * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
136 */
137
138#define PRID_IMP_BMIPS32_REV4 0x4000
139#define PRID_IMP_BMIPS32_REV8 0x8000
140#define PRID_IMP_BMIPS3300 0x9000
141#define PRID_IMP_BMIPS3300_ALT 0x9100
142#define PRID_IMP_BMIPS3300_BUG 0x0000
143#define PRID_IMP_BMIPS43XX 0xa000
144#define PRID_IMP_BMIPS5000 0x5a00
145
146#define PRID_REV_BMIPS4380_LO 0x0040
147#define PRID_REV_BMIPS4380_HI 0x006f
148
149/*
150 * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
151 */
152
153#define PRID_IMP_CAVIUM_CN38XX 0x0000
154#define PRID_IMP_CAVIUM_CN31XX 0x0100
155#define PRID_IMP_CAVIUM_CN30XX 0x0200
156#define PRID_IMP_CAVIUM_CN58XX 0x0300
157#define PRID_IMP_CAVIUM_CN56XX 0x0400
158#define PRID_IMP_CAVIUM_CN50XX 0x0600
159#define PRID_IMP_CAVIUM_CN52XX 0x0700
160#define PRID_IMP_CAVIUM_CN63XX 0x9000
161#define PRID_IMP_CAVIUM_CN68XX 0x9100
162#define PRID_IMP_CAVIUM_CN66XX 0x9200
163#define PRID_IMP_CAVIUM_CN61XX 0x9300
164#define PRID_IMP_CAVIUM_CNF71XX 0x9400
165#define PRID_IMP_CAVIUM_CN78XX 0x9500
166#define PRID_IMP_CAVIUM_CN70XX 0x9600
167
168/*
169 * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
170 */
171
172#define PRID_IMP_JZRISC 0x0200
173
174/*
175 * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
176 */
177#define PRID_IMP_NETLOGIC_XLR732 0x0000
178#define PRID_IMP_NETLOGIC_XLR716 0x0200
179#define PRID_IMP_NETLOGIC_XLR532 0x0900
180#define PRID_IMP_NETLOGIC_XLR308 0x0600
181#define PRID_IMP_NETLOGIC_XLR532C 0x0800
182#define PRID_IMP_NETLOGIC_XLR516C 0x0a00
183#define PRID_IMP_NETLOGIC_XLR508C 0x0b00
184#define PRID_IMP_NETLOGIC_XLR308C 0x0f00
185#define PRID_IMP_NETLOGIC_XLS608 0x8000
186#define PRID_IMP_NETLOGIC_XLS408 0x8800
187#define PRID_IMP_NETLOGIC_XLS404 0x8c00
188#define PRID_IMP_NETLOGIC_XLS208 0x8e00
189#define PRID_IMP_NETLOGIC_XLS204 0x8f00
190#define PRID_IMP_NETLOGIC_XLS108 0xce00
191#define PRID_IMP_NETLOGIC_XLS104 0xcf00
192#define PRID_IMP_NETLOGIC_XLS616B 0x4000
193#define PRID_IMP_NETLOGIC_XLS608B 0x4a00
194#define PRID_IMP_NETLOGIC_XLS416B 0x4400
195#define PRID_IMP_NETLOGIC_XLS412B 0x4c00
196#define PRID_IMP_NETLOGIC_XLS408B 0x4e00
197#define PRID_IMP_NETLOGIC_XLS404B 0x4f00
198#define PRID_IMP_NETLOGIC_AU13XX 0x8000
199
200#define PRID_IMP_NETLOGIC_XLP8XX 0x1000
201#define PRID_IMP_NETLOGIC_XLP3XX 0x1100
202#define PRID_IMP_NETLOGIC_XLP2XX 0x1200
203#define PRID_IMP_NETLOGIC_XLP9XX 0x1500
204
205/*
206 * Particular Revision values for bits 7:0 of the PRId register.
207 */
208
209#define PRID_REV_MASK 0x00ff
210
211/*
212 * Definitions for 7:0 on legacy processors
213 */
214
215#define PRID_REV_TX4927 0x0022
216#define PRID_REV_TX4937 0x0030
217#define PRID_REV_R4400 0x0040
218#define PRID_REV_R3000A 0x0030
219#define PRID_REV_R3000 0x0020
220#define PRID_REV_R2000A 0x0010
221#define PRID_REV_TX3912 0x0010
222#define PRID_REV_TX3922 0x0030
223#define PRID_REV_TX3927 0x0040
224#define PRID_REV_VR4111 0x0050
225#define PRID_REV_VR4181 0x0050 /* Same as VR4111 */
226#define PRID_REV_VR4121 0x0060
227#define PRID_REV_VR4122 0x0070
228#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
229#define PRID_REV_VR4130 0x0080
230#define PRID_REV_34K_V1_0_2 0x0022
231#define PRID_REV_LOONGSON1B 0x0020
232#define PRID_REV_LOONGSON2E 0x0002
233#define PRID_REV_LOONGSON2F 0x0003
234#define PRID_REV_LOONGSON3A 0x0005
235
236/*
237 * Older processors used to encode processor version and revision in two
238 * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
239 * have switched to use the 8-bits as 3:3:2 bitfield with the last field as
240 * the patch number. *ARGH*
241 */
242#define PRID_REV_ENCODE_44(ver, rev) \
243 ((ver) << 4 | (rev))
244#define PRID_REV_ENCODE_332(ver, rev, patch) \
245 ((ver) << 5 | (rev) << 2 | (patch))
246
247/*
248 * FPU implementation/revision register (CP1 control register 0).
249 *
250 * +---------------------------------+----------------+----------------+
251 * | 0 | Implementation | Revision |
252 * +---------------------------------+----------------+----------------+
253 * 31 16 15 8 7 0
254 */
255
256#define FPIR_IMP_MASK 0xff00
257
258#define FPIR_IMP_NONE 0x0000
259
260#if !defined(__ASSEMBLY__)
261
262enum cpu_type_enum {
263 CPU_UNKNOWN,
264
265 /*
266 * R2000 class processors
267 */
268 CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052,
269 CPU_R3081, CPU_R3081E,
270
271 /*
272 * R6000 class processors
273 */
274 CPU_R6000, CPU_R6000A,
275
276 /*
277 * R4000 class processors
278 */
279 CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
280 CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
281 CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000,
282 CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, CPU_VR4122,
283 CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
284 CPU_SR71000, CPU_RM9000, CPU_TX49XX,
285
286 /*
287 * R8000 class processors
288 */
289 CPU_R8000,
290
291 /*
292 * TX3900 class processors
293 */
294 CPU_TX3912, CPU_TX3922, CPU_TX3927,
295
296 /*
297 * MIPS32 class processors
298 */
299 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
300 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
301 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
302 CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K, CPU_M5150,
303
304 /*
305 * MIPS64 class processors
306 */
307 CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
308 CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
309 CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP,
310
311 CPU_LAST
312};
313
314#endif /* !__ASSEMBLY */
315
316/*
317 * ISA Level encodings
318 *
319 */
320#define MIPS_CPU_ISA_II 0x00000001
321#define MIPS_CPU_ISA_III 0x00000002
322#define MIPS_CPU_ISA_IV 0x00000004
323#define MIPS_CPU_ISA_V 0x00000008
324#define MIPS_CPU_ISA_M32R1 0x00000010
325#define MIPS_CPU_ISA_M32R2 0x00000020
326#define MIPS_CPU_ISA_M64R1 0x00000040
327#define MIPS_CPU_ISA_M64R2 0x00000080
328
329#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \
330 MIPS_CPU_ISA_M32R2)
331#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
332 MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)
333
334/*
335 * CPU Option encodings
336 */
337#define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */
338#define MIPS_CPU_4KEX 0x00000002 /* "R4K" exception model */
339#define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */
340#define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */
341#define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */
342#define MIPS_CPU_FPU 0x00000020 /* CPU has FPU */
343#define MIPS_CPU_32FPR 0x00000040 /* 32 dbl. prec. FP registers */
344#define MIPS_CPU_COUNTER 0x00000080 /* Cycle count/compare */
345#define MIPS_CPU_WATCH 0x00000100 /* watchpoint registers */
346#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */
347#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */
348#define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */
349#define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */
350#define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */
351#define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */
352#define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */
353#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */
354#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000 /* P-cache subset enforced */
355#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */
356#define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */
357#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
358#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */
359#define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */
360#define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */
361#define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */
362#define MIPS_CPU_TLBINV 0x02000000 /* CPU supports TLBINV/F */
363#define MIPS_CPU_SEGMENTS 0x04000000 /* CPU supports Segmentation Control registers */
364#define MIPS_CPU_EVA 0x80000000 /* CPU supports Enhanced Virtual Addressing */
365
366/*
367 * CPU ASE encodings
368 */
369#define MIPS_ASE_MIPS16 0x00000001 /* code compression */
370#define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */
371#define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */
372#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */
373#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */
374#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */
375#define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */
376#define MIPS_ASE_VZ 0x00000080 /* Virtualization ASE */
377#define MIPS_ASE_MSA 0x00000100 /* MIPS SIMD Architecture */
378
379#endif /* _ASM_CPU_H */