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1/*
2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44#include <dt-bindings/thermal/thermal.h>
45#include <dt-bindings/dma/sun4i-a10.h>
46#include <dt-bindings/clock/sun4i-a10-ccu.h>
47#include <dt-bindings/reset/sun4i-a10-ccu.h>
48
49/ {
50 #address-cells = <1>;
51 #size-cells = <1>;
52 interrupt-parent = <&intc>;
53
54 aliases {
55 ethernet0 = &emac;
56 };
57
58 chosen {
59 #address-cells = <1>;
60 #size-cells = <1>;
61 ranges;
62
63 framebuffer-lcd0-hdmi {
64 compatible = "allwinner,simple-framebuffer",
65 "simple-framebuffer";
66 allwinner,pipeline = "de_be0-lcd0-hdmi";
67 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
68 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
69 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>;
70 status = "disabled";
71 };
72
73 framebuffer-fe0-lcd0-hdmi {
74 compatible = "allwinner,simple-framebuffer",
75 "simple-framebuffer";
76 allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
77 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
78 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
79 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
80 <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>,
81 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
82 status = "disabled";
83 };
84
85 framebuffer-fe0-lcd0 {
86 compatible = "allwinner,simple-framebuffer",
87 "simple-framebuffer";
88 allwinner,pipeline = "de_fe0-de_be0-lcd0";
89 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
90 <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>,
91 <&ccu CLK_DE_FE0>, <&ccu CLK_TCON0_CH0>,
92 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
93 status = "disabled";
94 };
95
96 framebuffer-fe0-lcd0-tve0 {
97 compatible = "allwinner,simple-framebuffer",
98 "simple-framebuffer";
99 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
100 clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
101 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
102 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
103 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>,
104 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
105 status = "disabled";
106 };
107 };
108
109 cpus {
110 #address-cells = <1>;
111 #size-cells = <0>;
112 cpu0: cpu@0 {
113 device_type = "cpu";
114 compatible = "arm,cortex-a8";
115 reg = <0x0>;
116 clocks = <&ccu CLK_CPU>;
117 clock-latency = <244144>; /* 8 32k periods */
118 operating-points = <
119 /* kHz uV */
120 1008000 1400000
121 912000 1350000
122 864000 1300000
123 624000 1250000
124 >;
125 #cooling-cells = <2>;
126 };
127 };
128
129 thermal-zones {
130 cpu-thermal {
131 /* milliseconds */
132 polling-delay-passive = <250>;
133 polling-delay = <1000>;
134 thermal-sensors = <&rtp>;
135
136 cooling-maps {
137 map0 {
138 trip = <&cpu_alert0>;
139 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
140 };
141 };
142
143 trips {
144 cpu_alert0: cpu-alert0 {
145 /* milliCelsius */
146 temperature = <850000>;
147 hysteresis = <2000>;
148 type = "passive";
149 };
150
151 cpu_crit: cpu-crit {
152 /* milliCelsius */
153 temperature = <100000>;
154 hysteresis = <2000>;
155 type = "critical";
156 };
157 };
158 };
159 };
160
161 clocks {
162 #address-cells = <1>;
163 #size-cells = <1>;
164 ranges;
165
166 osc24M: clk-24M {
167 #clock-cells = <0>;
168 compatible = "fixed-clock";
169 clock-frequency = <24000000>;
170 clock-output-names = "osc24M";
171 };
172
173 osc32k: clk-32k {
174 #clock-cells = <0>;
175 compatible = "fixed-clock";
176 clock-frequency = <32768>;
177 clock-output-names = "osc32k";
178 };
179 };
180
181 de: display-engine {
182 compatible = "allwinner,sun4i-a10-display-engine";
183 allwinner,pipelines = <&fe0>, <&fe1>;
184 status = "disabled";
185 };
186
187 soc {
188 compatible = "simple-bus";
189 #address-cells = <1>;
190 #size-cells = <1>;
191 ranges;
192
193 sram-controller@1c00000 {
194 compatible = "allwinner,sun4i-a10-sram-controller";
195 reg = <0x01c00000 0x30>;
196 #address-cells = <1>;
197 #size-cells = <1>;
198 ranges;
199
200 sram_a: sram@0 {
201 compatible = "mmio-sram";
202 reg = <0x00000000 0xc000>;
203 #address-cells = <1>;
204 #size-cells = <1>;
205 ranges = <0 0x00000000 0xc000>;
206
207 emac_sram: sram-section@8000 {
208 compatible = "allwinner,sun4i-a10-sram-a3-a4";
209 reg = <0x8000 0x4000>;
210 status = "disabled";
211 };
212 };
213
214 sram_d: sram@10000 {
215 compatible = "mmio-sram";
216 reg = <0x00010000 0x1000>;
217 #address-cells = <1>;
218 #size-cells = <1>;
219 ranges = <0 0x00010000 0x1000>;
220
221 otg_sram: sram-section@0 {
222 compatible = "allwinner,sun4i-a10-sram-d";
223 reg = <0x0000 0x1000>;
224 status = "disabled";
225 };
226 };
227 };
228
229 dma: dma-controller@1c02000 {
230 compatible = "allwinner,sun4i-a10-dma";
231 reg = <0x01c02000 0x1000>;
232 interrupts = <27>;
233 clocks = <&ccu CLK_AHB_DMA>;
234 #dma-cells = <2>;
235 };
236
237 nfc: nand@1c03000 {
238 compatible = "allwinner,sun4i-a10-nand";
239 reg = <0x01c03000 0x1000>;
240 interrupts = <37>;
241 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
242 clock-names = "ahb", "mod";
243 dmas = <&dma SUN4I_DMA_DEDICATED 3>;
244 dma-names = "rxtx";
245 status = "disabled";
246 #address-cells = <1>;
247 #size-cells = <0>;
248 };
249
250 spi0: spi@1c05000 {
251 compatible = "allwinner,sun4i-a10-spi";
252 reg = <0x01c05000 0x1000>;
253 interrupts = <10>;
254 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
255 clock-names = "ahb", "mod";
256 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
257 <&dma SUN4I_DMA_DEDICATED 26>;
258 dma-names = "rx", "tx";
259 status = "disabled";
260 #address-cells = <1>;
261 #size-cells = <0>;
262 };
263
264 spi1: spi@1c06000 {
265 compatible = "allwinner,sun4i-a10-spi";
266 reg = <0x01c06000 0x1000>;
267 interrupts = <11>;
268 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
269 clock-names = "ahb", "mod";
270 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
271 <&dma SUN4I_DMA_DEDICATED 8>;
272 dma-names = "rx", "tx";
273 pinctrl-names = "default";
274 pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>;
275 status = "disabled";
276 #address-cells = <1>;
277 #size-cells = <0>;
278 };
279
280 emac: ethernet@1c0b000 {
281 compatible = "allwinner,sun4i-a10-emac";
282 reg = <0x01c0b000 0x1000>;
283 interrupts = <55>;
284 clocks = <&ccu CLK_AHB_EMAC>;
285 allwinner,sram = <&emac_sram 1>;
286 pinctrl-names = "default";
287 pinctrl-0 = <&emac_pins>;
288 status = "disabled";
289 };
290
291 mdio: mdio@1c0b080 {
292 compatible = "allwinner,sun4i-a10-mdio";
293 reg = <0x01c0b080 0x14>;
294 status = "disabled";
295 #address-cells = <1>;
296 #size-cells = <0>;
297 };
298
299 tcon0: lcd-controller@1c0c000 {
300 compatible = "allwinner,sun4i-a10-tcon";
301 reg = <0x01c0c000 0x1000>;
302 interrupts = <44>;
303 resets = <&ccu RST_TCON0>;
304 reset-names = "lcd";
305 clocks = <&ccu CLK_AHB_LCD0>,
306 <&ccu CLK_TCON0_CH0>,
307 <&ccu CLK_TCON0_CH1>;
308 clock-names = "ahb",
309 "tcon-ch0",
310 "tcon-ch1";
311 clock-output-names = "tcon0-pixel-clock";
312 dmas = <&dma SUN4I_DMA_DEDICATED 14>;
313
314 ports {
315 #address-cells = <1>;
316 #size-cells = <0>;
317
318 tcon0_in: port@0 {
319 #address-cells = <1>;
320 #size-cells = <0>;
321 reg = <0>;
322
323 tcon0_in_be0: endpoint@0 {
324 reg = <0>;
325 remote-endpoint = <&be0_out_tcon0>;
326 };
327
328 tcon0_in_be1: endpoint@1 {
329 reg = <1>;
330 remote-endpoint = <&be1_out_tcon0>;
331 };
332 };
333
334 tcon0_out: port@1 {
335 #address-cells = <1>;
336 #size-cells = <0>;
337 reg = <1>;
338
339 tcon0_out_hdmi: endpoint@1 {
340 reg = <1>;
341 remote-endpoint = <&hdmi_in_tcon0>;
342 allwinner,tcon-channel = <1>;
343 };
344 };
345 };
346 };
347
348 tcon1: lcd-controller@1c0d000 {
349 compatible = "allwinner,sun4i-a10-tcon";
350 reg = <0x01c0d000 0x1000>;
351 interrupts = <45>;
352 resets = <&ccu RST_TCON1>;
353 reset-names = "lcd";
354 clocks = <&ccu CLK_AHB_LCD1>,
355 <&ccu CLK_TCON1_CH0>,
356 <&ccu CLK_TCON1_CH1>;
357 clock-names = "ahb",
358 "tcon-ch0",
359 "tcon-ch1";
360 clock-output-names = "tcon1-pixel-clock";
361 dmas = <&dma SUN4I_DMA_DEDICATED 15>;
362
363 ports {
364 #address-cells = <1>;
365 #size-cells = <0>;
366
367 tcon1_in: port@0 {
368 #address-cells = <1>;
369 #size-cells = <0>;
370 reg = <0>;
371
372 tcon1_in_be0: endpoint@0 {
373 reg = <0>;
374 remote-endpoint = <&be0_out_tcon1>;
375 };
376
377 tcon1_in_be1: endpoint@1 {
378 reg = <1>;
379 remote-endpoint = <&be1_out_tcon1>;
380 };
381 };
382
383 tcon1_out: port@1 {
384 #address-cells = <1>;
385 #size-cells = <0>;
386 reg = <1>;
387
388 tcon1_out_hdmi: endpoint@1 {
389 reg = <1>;
390 remote-endpoint = <&hdmi_in_tcon1>;
391 allwinner,tcon-channel = <1>;
392 };
393 };
394 };
395 };
396
397 mmc0: mmc@1c0f000 {
398 compatible = "allwinner,sun4i-a10-mmc";
399 reg = <0x01c0f000 0x1000>;
400 clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
401 clock-names = "ahb", "mmc";
402 interrupts = <32>;
403 pinctrl-names = "default";
404 pinctrl-0 = <&mmc0_pins>;
405 status = "disabled";
406 #address-cells = <1>;
407 #size-cells = <0>;
408 };
409
410 mmc1: mmc@1c10000 {
411 compatible = "allwinner,sun4i-a10-mmc";
412 reg = <0x01c10000 0x1000>;
413 clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
414 clock-names = "ahb", "mmc";
415 interrupts = <33>;
416 status = "disabled";
417 #address-cells = <1>;
418 #size-cells = <0>;
419 };
420
421 mmc2: mmc@1c11000 {
422 compatible = "allwinner,sun4i-a10-mmc";
423 reg = <0x01c11000 0x1000>;
424 clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
425 clock-names = "ahb", "mmc";
426 interrupts = <34>;
427 status = "disabled";
428 #address-cells = <1>;
429 #size-cells = <0>;
430 };
431
432 mmc3: mmc@1c12000 {
433 compatible = "allwinner,sun4i-a10-mmc";
434 reg = <0x01c12000 0x1000>;
435 clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>;
436 clock-names = "ahb", "mmc";
437 interrupts = <35>;
438 status = "disabled";
439 #address-cells = <1>;
440 #size-cells = <0>;
441 };
442
443 usb_otg: usb@1c13000 {
444 compatible = "allwinner,sun4i-a10-musb";
445 reg = <0x01c13000 0x0400>;
446 clocks = <&ccu CLK_AHB_OTG>;
447 interrupts = <38>;
448 interrupt-names = "mc";
449 phys = <&usbphy 0>;
450 phy-names = "usb";
451 extcon = <&usbphy 0>;
452 allwinner,sram = <&otg_sram 1>;
453 status = "disabled";
454 };
455
456 usbphy: phy@1c13400 {
457 #phy-cells = <1>;
458 compatible = "allwinner,sun4i-a10-usb-phy";
459 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
460 reg-names = "phy_ctrl", "pmu1", "pmu2";
461 clocks = <&ccu CLK_USB_PHY>;
462 clock-names = "usb_phy";
463 resets = <&ccu RST_USB_PHY0>,
464 <&ccu RST_USB_PHY1>,
465 <&ccu RST_USB_PHY2>;
466 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
467 status = "disabled";
468 };
469
470 ehci0: usb@1c14000 {
471 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
472 reg = <0x01c14000 0x100>;
473 interrupts = <39>;
474 clocks = <&ccu CLK_AHB_EHCI0>;
475 phys = <&usbphy 1>;
476 phy-names = "usb";
477 status = "disabled";
478 };
479
480 ohci0: usb@1c14400 {
481 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
482 reg = <0x01c14400 0x100>;
483 interrupts = <64>;
484 clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
485 phys = <&usbphy 1>;
486 phy-names = "usb";
487 status = "disabled";
488 };
489
490 crypto: crypto-engine@1c15000 {
491 compatible = "allwinner,sun4i-a10-crypto";
492 reg = <0x01c15000 0x1000>;
493 interrupts = <86>;
494 clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
495 clock-names = "ahb", "mod";
496 };
497
498 hdmi: hdmi@1c16000 {
499 compatible = "allwinner,sun4i-a10-hdmi";
500 reg = <0x01c16000 0x1000>;
501 interrupts = <58>;
502 clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
503 <&ccu CLK_PLL_VIDEO0_2X>,
504 <&ccu CLK_PLL_VIDEO1_2X>;
505 clock-names = "ahb", "mod", "pll-0", "pll-1";
506 dmas = <&dma SUN4I_DMA_NORMAL 16>,
507 <&dma SUN4I_DMA_NORMAL 16>,
508 <&dma SUN4I_DMA_DEDICATED 24>;
509 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
510 status = "disabled";
511
512 ports {
513 #address-cells = <1>;
514 #size-cells = <0>;
515
516 hdmi_in: port@0 {
517 #address-cells = <1>;
518 #size-cells = <0>;
519 reg = <0>;
520
521 hdmi_in_tcon0: endpoint@0 {
522 reg = <0>;
523 remote-endpoint = <&tcon0_out_hdmi>;
524 };
525
526 hdmi_in_tcon1: endpoint@1 {
527 reg = <1>;
528 remote-endpoint = <&tcon1_out_hdmi>;
529 };
530 };
531
532 hdmi_out: port@1 {
533 #address-cells = <1>;
534 #size-cells = <0>;
535 reg = <1>;
536 };
537 };
538 };
539
540 spi2: spi@1c17000 {
541 compatible = "allwinner,sun4i-a10-spi";
542 reg = <0x01c17000 0x1000>;
543 interrupts = <12>;
544 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
545 clock-names = "ahb", "mod";
546 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
547 <&dma SUN4I_DMA_DEDICATED 28>;
548 dma-names = "rx", "tx";
549 status = "disabled";
550 #address-cells = <1>;
551 #size-cells = <0>;
552 };
553
554 ahci: sata@1c18000 {
555 compatible = "allwinner,sun4i-a10-ahci";
556 reg = <0x01c18000 0x1000>;
557 interrupts = <56>;
558 clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
559 status = "disabled";
560 };
561
562 ehci1: usb@1c1c000 {
563 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
564 reg = <0x01c1c000 0x100>;
565 interrupts = <40>;
566 clocks = <&ccu CLK_AHB_EHCI1>;
567 phys = <&usbphy 2>;
568 phy-names = "usb";
569 status = "disabled";
570 };
571
572 ohci1: usb@1c1c400 {
573 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
574 reg = <0x01c1c400 0x100>;
575 interrupts = <65>;
576 clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
577 phys = <&usbphy 2>;
578 phy-names = "usb";
579 status = "disabled";
580 };
581
582 spi3: spi@1c1f000 {
583 compatible = "allwinner,sun4i-a10-spi";
584 reg = <0x01c1f000 0x1000>;
585 interrupts = <50>;
586 clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
587 clock-names = "ahb", "mod";
588 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
589 <&dma SUN4I_DMA_DEDICATED 30>;
590 dma-names = "rx", "tx";
591 status = "disabled";
592 #address-cells = <1>;
593 #size-cells = <0>;
594 };
595
596 ccu: clock@1c20000 {
597 compatible = "allwinner,sun4i-a10-ccu";
598 reg = <0x01c20000 0x400>;
599 clocks = <&osc24M>, <&osc32k>;
600 clock-names = "hosc", "losc";
601 #clock-cells = <1>;
602 #reset-cells = <1>;
603 };
604
605 intc: interrupt-controller@1c20400 {
606 compatible = "allwinner,sun4i-a10-ic";
607 reg = <0x01c20400 0x400>;
608 interrupt-controller;
609 #interrupt-cells = <1>;
610 };
611
612 pio: pinctrl@1c20800 {
613 compatible = "allwinner,sun4i-a10-pinctrl";
614 reg = <0x01c20800 0x400>;
615 interrupts = <28>;
616 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
617 clock-names = "apb", "hosc", "losc";
618 gpio-controller;
619 interrupt-controller;
620 #interrupt-cells = <3>;
621 #gpio-cells = <3>;
622
623 can0_ph_pins: can0-ph-pins {
624 pins = "PH20", "PH21";
625 function = "can";
626 };
627
628 emac_pins: emac0-pins {
629 pins = "PA0", "PA1", "PA2",
630 "PA3", "PA4", "PA5", "PA6",
631 "PA7", "PA8", "PA9", "PA10",
632 "PA11", "PA12", "PA13", "PA14",
633 "PA15", "PA16";
634 function = "emac";
635 };
636
637 i2c0_pins: i2c0-pins {
638 pins = "PB0", "PB1";
639 function = "i2c0";
640 };
641
642 i2c1_pins: i2c1-pins {
643 pins = "PB18", "PB19";
644 function = "i2c1";
645 };
646
647 i2c2_pins: i2c2-pins {
648 pins = "PB20", "PB21";
649 function = "i2c2";
650 };
651
652 ir0_rx_pins: ir0-rx-pin {
653 pins = "PB4";
654 function = "ir0";
655 };
656
657 ir0_tx_pins: ir0-tx-pin {
658 pins = "PB3";
659 function = "ir0";
660 };
661
662 ir1_rx_pins: ir1-rx-pin {
663 pins = "PB23";
664 function = "ir1";
665 };
666
667 ir1_tx_pins: ir1-tx-pin {
668 pins = "PB22";
669 function = "ir1";
670 };
671
672 mmc0_pins: mmc0-pins {
673 pins = "PF0", "PF1", "PF2",
674 "PF3", "PF4", "PF5";
675 function = "mmc0";
676 drive-strength = <30>;
677 bias-pull-up;
678 };
679
680 ps2_ch0_pins: ps2-ch0-pins {
681 pins = "PI20", "PI21";
682 function = "ps2";
683 };
684
685 ps2_ch1_ph_pins: ps2-ch1-ph-pins {
686 pins = "PH12", "PH13";
687 function = "ps2";
688 };
689
690 pwm0_pin: pwm0-pin {
691 pins = "PB2";
692 function = "pwm";
693 };
694
695 pwm1_pin: pwm1-pin {
696 pins = "PI3";
697 function = "pwm";
698 };
699
700 spdif_tx_pin: spdif-tx-pin {
701 pins = "PB13";
702 function = "spdif";
703 bias-pull-up;
704 };
705
706 spi0_pi_pins: spi0-pi-pins {
707 pins = "PI11", "PI12", "PI13";
708 function = "spi0";
709 };
710
711 spi0_cs0_pi_pin: spi0-cs0-pi-pin {
712 pins = "PI10";
713 function = "spi0";
714 };
715
716 spi1_pins: spi1-pins {
717 pins = "PI17", "PI18", "PI19";
718 function = "spi1";
719 };
720
721 spi1_cs0_pin: spi1-cs0-pin {
722 pins = "PI16";
723 function = "spi1";
724 };
725
726 spi2_pb_pins: spi2-pb-pins {
727 pins = "PB15", "PB16", "PB17";
728 function = "spi2";
729 };
730
731 spi2_pc_pins: spi2-pc-pins {
732 pins = "PC20", "PC21", "PC22";
733 function = "spi2";
734 };
735
736 spi2_cs0_pb_pin: spi2-cs0-pb-pin {
737 pins = "PB14";
738 function = "spi2";
739 };
740
741 spi2_cs0_pc_pins: spi2-cs0-pc-pin {
742 pins = "PC19";
743 function = "spi2";
744 };
745
746 uart0_pb_pins: uart0-pb-pins {
747 pins = "PB22", "PB23";
748 function = "uart0";
749 };
750
751 uart0_pf_pins: uart0-pf-pins {
752 pins = "PF2", "PF4";
753 function = "uart0";
754 };
755
756 uart1_pins: uart1-pins {
757 pins = "PA10", "PA11";
758 function = "uart1";
759 };
760 };
761
762 timer@1c20c00 {
763 compatible = "allwinner,sun4i-a10-timer";
764 reg = <0x01c20c00 0x90>;
765 interrupts = <22>;
766 clocks = <&osc24M>;
767 };
768
769 wdt: watchdog@1c20c90 {
770 compatible = "allwinner,sun4i-a10-wdt";
771 reg = <0x01c20c90 0x10>;
772 };
773
774 rtc: rtc@1c20d00 {
775 compatible = "allwinner,sun4i-a10-rtc";
776 reg = <0x01c20d00 0x20>;
777 interrupts = <24>;
778 };
779
780 pwm: pwm@1c20e00 {
781 compatible = "allwinner,sun4i-a10-pwm";
782 reg = <0x01c20e00 0xc>;
783 clocks = <&osc24M>;
784 #pwm-cells = <3>;
785 status = "disabled";
786 };
787
788 spdif: spdif@1c21000 {
789 #sound-dai-cells = <0>;
790 compatible = "allwinner,sun4i-a10-spdif";
791 reg = <0x01c21000 0x400>;
792 interrupts = <13>;
793 clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
794 clock-names = "apb", "spdif";
795 dmas = <&dma SUN4I_DMA_NORMAL 2>,
796 <&dma SUN4I_DMA_NORMAL 2>;
797 dma-names = "rx", "tx";
798 status = "disabled";
799 };
800
801 ir0: ir@1c21800 {
802 compatible = "allwinner,sun4i-a10-ir";
803 clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
804 clock-names = "apb", "ir";
805 interrupts = <5>;
806 reg = <0x01c21800 0x40>;
807 status = "disabled";
808 };
809
810 ir1: ir@1c21c00 {
811 compatible = "allwinner,sun4i-a10-ir";
812 clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
813 clock-names = "apb", "ir";
814 interrupts = <6>;
815 reg = <0x01c21c00 0x40>;
816 status = "disabled";
817 };
818
819 i2s0: i2s@1c22400 {
820 #sound-dai-cells = <0>;
821 compatible = "allwinner,sun4i-a10-i2s";
822 reg = <0x01c22400 0x400>;
823 interrupts = <16>;
824 clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
825 clock-names = "apb", "mod";
826 dmas = <&dma SUN4I_DMA_NORMAL 3>,
827 <&dma SUN4I_DMA_NORMAL 3>;
828 dma-names = "rx", "tx";
829 status = "disabled";
830 };
831
832 lradc: lradc@1c22800 {
833 compatible = "allwinner,sun4i-a10-lradc-keys";
834 reg = <0x01c22800 0x100>;
835 interrupts = <31>;
836 status = "disabled";
837 };
838
839 codec: codec@1c22c00 {
840 #sound-dai-cells = <0>;
841 compatible = "allwinner,sun4i-a10-codec";
842 reg = <0x01c22c00 0x40>;
843 interrupts = <30>;
844 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
845 clock-names = "apb", "codec";
846 dmas = <&dma SUN4I_DMA_NORMAL 19>,
847 <&dma SUN4I_DMA_NORMAL 19>;
848 dma-names = "rx", "tx";
849 status = "disabled";
850 };
851
852 sid: eeprom@1c23800 {
853 compatible = "allwinner,sun4i-a10-sid";
854 reg = <0x01c23800 0x10>;
855 };
856
857 rtp: rtp@1c25000 {
858 compatible = "allwinner,sun4i-a10-ts";
859 reg = <0x01c25000 0x100>;
860 interrupts = <29>;
861 #thermal-sensor-cells = <0>;
862 };
863
864 uart0: serial@1c28000 {
865 compatible = "snps,dw-apb-uart";
866 reg = <0x01c28000 0x400>;
867 interrupts = <1>;
868 reg-shift = <2>;
869 reg-io-width = <4>;
870 clocks = <&ccu CLK_APB1_UART0>;
871 status = "disabled";
872 };
873
874 uart1: serial@1c28400 {
875 compatible = "snps,dw-apb-uart";
876 reg = <0x01c28400 0x400>;
877 interrupts = <2>;
878 reg-shift = <2>;
879 reg-io-width = <4>;
880 clocks = <&ccu CLK_APB1_UART1>;
881 status = "disabled";
882 };
883
884 uart2: serial@1c28800 {
885 compatible = "snps,dw-apb-uart";
886 reg = <0x01c28800 0x400>;
887 interrupts = <3>;
888 reg-shift = <2>;
889 reg-io-width = <4>;
890 clocks = <&ccu CLK_APB1_UART2>;
891 status = "disabled";
892 };
893
894 uart3: serial@1c28c00 {
895 compatible = "snps,dw-apb-uart";
896 reg = <0x01c28c00 0x400>;
897 interrupts = <4>;
898 reg-shift = <2>;
899 reg-io-width = <4>;
900 clocks = <&ccu CLK_APB1_UART3>;
901 status = "disabled";
902 };
903
904 uart4: serial@1c29000 {
905 compatible = "snps,dw-apb-uart";
906 reg = <0x01c29000 0x400>;
907 interrupts = <17>;
908 reg-shift = <2>;
909 reg-io-width = <4>;
910 clocks = <&ccu CLK_APB1_UART4>;
911 status = "disabled";
912 };
913
914 uart5: serial@1c29400 {
915 compatible = "snps,dw-apb-uart";
916 reg = <0x01c29400 0x400>;
917 interrupts = <18>;
918 reg-shift = <2>;
919 reg-io-width = <4>;
920 clocks = <&ccu CLK_APB1_UART5>;
921 status = "disabled";
922 };
923
924 uart6: serial@1c29800 {
925 compatible = "snps,dw-apb-uart";
926 reg = <0x01c29800 0x400>;
927 interrupts = <19>;
928 reg-shift = <2>;
929 reg-io-width = <4>;
930 clocks = <&ccu CLK_APB1_UART6>;
931 status = "disabled";
932 };
933
934 uart7: serial@1c29c00 {
935 compatible = "snps,dw-apb-uart";
936 reg = <0x01c29c00 0x400>;
937 interrupts = <20>;
938 reg-shift = <2>;
939 reg-io-width = <4>;
940 clocks = <&ccu CLK_APB1_UART7>;
941 status = "disabled";
942 };
943
944 ps20: ps2@1c2a000 {
945 compatible = "allwinner,sun4i-a10-ps2";
946 reg = <0x01c2a000 0x400>;
947 interrupts = <62>;
948 clocks = <&ccu CLK_APB1_PS20>;
949 status = "disabled";
950 };
951
952 ps21: ps2@1c2a400 {
953 compatible = "allwinner,sun4i-a10-ps2";
954 reg = <0x01c2a400 0x400>;
955 interrupts = <63>;
956 clocks = <&ccu CLK_APB1_PS21>;
957 status = "disabled";
958 };
959
960 i2c0: i2c@1c2ac00 {
961 compatible = "allwinner,sun4i-a10-i2c";
962 reg = <0x01c2ac00 0x400>;
963 interrupts = <7>;
964 clocks = <&ccu CLK_APB1_I2C0>;
965 pinctrl-names = "default";
966 pinctrl-0 = <&i2c0_pins>;
967 status = "disabled";
968 #address-cells = <1>;
969 #size-cells = <0>;
970 };
971
972 i2c1: i2c@1c2b000 {
973 compatible = "allwinner,sun4i-a10-i2c";
974 reg = <0x01c2b000 0x400>;
975 interrupts = <8>;
976 clocks = <&ccu CLK_APB1_I2C1>;
977 pinctrl-names = "default";
978 pinctrl-0 = <&i2c1_pins>;
979 status = "disabled";
980 #address-cells = <1>;
981 #size-cells = <0>;
982 };
983
984 i2c2: i2c@1c2b400 {
985 compatible = "allwinner,sun4i-a10-i2c";
986 reg = <0x01c2b400 0x400>;
987 interrupts = <9>;
988 clocks = <&ccu CLK_APB1_I2C2>;
989 pinctrl-names = "default";
990 pinctrl-0 = <&i2c2_pins>;
991 status = "disabled";
992 #address-cells = <1>;
993 #size-cells = <0>;
994 };
995
996 can0: can@1c2bc00 {
997 compatible = "allwinner,sun4i-a10-can";
998 reg = <0x01c2bc00 0x400>;
999 interrupts = <26>;
1000 clocks = <&ccu CLK_APB1_CAN>;
1001 status = "disabled";
1002 };
1003
1004 fe0: display-frontend@1e00000 {
1005 compatible = "allwinner,sun4i-a10-display-frontend";
1006 reg = <0x01e00000 0x20000>;
1007 interrupts = <47>;
1008 clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1009 <&ccu CLK_DRAM_DE_FE0>;
1010 clock-names = "ahb", "mod",
1011 "ram";
1012 resets = <&ccu RST_DE_FE0>;
1013
1014 ports {
1015 #address-cells = <1>;
1016 #size-cells = <0>;
1017
1018 fe0_out: port@1 {
1019 #address-cells = <1>;
1020 #size-cells = <0>;
1021 reg = <1>;
1022
1023 fe0_out_be0: endpoint@0 {
1024 reg = <0>;
1025 remote-endpoint = <&be0_in_fe0>;
1026 };
1027
1028 fe0_out_be1: endpoint@1 {
1029 reg = <1>;
1030 remote-endpoint = <&be1_in_fe0>;
1031 };
1032 };
1033 };
1034 };
1035
1036 fe1: display-frontend@1e20000 {
1037 compatible = "allwinner,sun4i-a10-display-frontend";
1038 reg = <0x01e20000 0x20000>;
1039 interrupts = <48>;
1040 clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1041 <&ccu CLK_DRAM_DE_FE1>;
1042 clock-names = "ahb", "mod",
1043 "ram";
1044 resets = <&ccu RST_DE_FE1>;
1045
1046 ports {
1047 #address-cells = <1>;
1048 #size-cells = <0>;
1049
1050 fe1_out: port@1 {
1051 #address-cells = <1>;
1052 #size-cells = <0>;
1053 reg = <1>;
1054
1055 fe1_out_be0: endpoint@0 {
1056 reg = <0>;
1057 remote-endpoint = <&be0_in_fe1>;
1058 };
1059
1060 fe1_out_be1: endpoint@1 {
1061 reg = <1>;
1062 remote-endpoint = <&be1_in_fe1>;
1063 };
1064 };
1065 };
1066 };
1067
1068 be1: display-backend@1e40000 {
1069 compatible = "allwinner,sun4i-a10-display-backend";
1070 reg = <0x01e40000 0x10000>;
1071 interrupts = <48>;
1072 clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1073 <&ccu CLK_DRAM_DE_BE1>;
1074 clock-names = "ahb", "mod",
1075 "ram";
1076 resets = <&ccu RST_DE_BE1>;
1077
1078 ports {
1079 #address-cells = <1>;
1080 #size-cells = <0>;
1081
1082 be1_in: port@0 {
1083 #address-cells = <1>;
1084 #size-cells = <0>;
1085 reg = <0>;
1086
1087 be1_in_fe0: endpoint@0 {
1088 reg = <0>;
1089 remote-endpoint = <&fe0_out_be1>;
1090 };
1091
1092 be1_in_fe1: endpoint@1 {
1093 reg = <1>;
1094 remote-endpoint = <&fe1_out_be1>;
1095 };
1096 };
1097
1098 be1_out: port@1 {
1099 #address-cells = <1>;
1100 #size-cells = <0>;
1101 reg = <1>;
1102
1103 be1_out_tcon0: endpoint@0 {
1104 reg = <0>;
1105 remote-endpoint = <&tcon0_in_be1>;
1106 };
1107
1108 be1_out_tcon1: endpoint@1 {
1109 reg = <1>;
1110 remote-endpoint = <&tcon1_in_be1>;
1111 };
1112 };
1113 };
1114 };
1115
1116 be0: display-backend@1e60000 {
1117 compatible = "allwinner,sun4i-a10-display-backend";
1118 reg = <0x01e60000 0x10000>;
1119 interrupts = <47>;
1120 clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1121 <&ccu CLK_DRAM_DE_BE0>;
1122 clock-names = "ahb", "mod",
1123 "ram";
1124 resets = <&ccu RST_DE_BE0>;
1125
1126 ports {
1127 #address-cells = <1>;
1128 #size-cells = <0>;
1129
1130 be0_in: port@0 {
1131 #address-cells = <1>;
1132 #size-cells = <0>;
1133 reg = <0>;
1134
1135 be0_in_fe0: endpoint@0 {
1136 reg = <0>;
1137 remote-endpoint = <&fe0_out_be0>;
1138 };
1139
1140 be0_in_fe1: endpoint@1 {
1141 reg = <1>;
1142 remote-endpoint = <&fe1_out_be0>;
1143 };
1144 };
1145
1146 be0_out: port@1 {
1147 #address-cells = <1>;
1148 #size-cells = <0>;
1149 reg = <1>;
1150
1151 be0_out_tcon0: endpoint@0 {
1152 reg = <0>;
1153 remote-endpoint = <&tcon0_in_be0>;
1154 };
1155
1156 be0_out_tcon1: endpoint@1 {
1157 reg = <1>;
1158 remote-endpoint = <&tcon1_in_be0>;
1159 };
1160 };
1161 };
1162 };
1163 };
1164};
1/*
2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 interrupt-parent = <&intc>;
17
18 aliases {
19 ethernet0 = &emac;
20 serial0 = &uart0;
21 serial1 = &uart1;
22 serial2 = &uart2;
23 serial3 = &uart3;
24 serial4 = &uart4;
25 serial5 = &uart5;
26 serial6 = &uart6;
27 serial7 = &uart7;
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33 cpu@0 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a8";
36 reg = <0x0>;
37 };
38 };
39
40 memory {
41 reg = <0x40000000 0x80000000>;
42 };
43
44 clocks {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 ranges;
48
49 /*
50 * This is a dummy clock, to be used as placeholder on
51 * other mux clocks when a specific parent clock is not
52 * yet implemented. It should be dropped when the driver
53 * is complete.
54 */
55 dummy: dummy {
56 #clock-cells = <0>;
57 compatible = "fixed-clock";
58 clock-frequency = <0>;
59 };
60
61 osc24M: clk@01c20050 {
62 #clock-cells = <0>;
63 compatible = "allwinner,sun4i-a10-osc-clk";
64 reg = <0x01c20050 0x4>;
65 clock-frequency = <24000000>;
66 clock-output-names = "osc24M";
67 };
68
69 osc32k: clk@0 {
70 #clock-cells = <0>;
71 compatible = "fixed-clock";
72 clock-frequency = <32768>;
73 clock-output-names = "osc32k";
74 };
75
76 pll1: clk@01c20000 {
77 #clock-cells = <0>;
78 compatible = "allwinner,sun4i-a10-pll1-clk";
79 reg = <0x01c20000 0x4>;
80 clocks = <&osc24M>;
81 clock-output-names = "pll1";
82 };
83
84 pll4: clk@01c20018 {
85 #clock-cells = <0>;
86 compatible = "allwinner,sun4i-a10-pll1-clk";
87 reg = <0x01c20018 0x4>;
88 clocks = <&osc24M>;
89 clock-output-names = "pll4";
90 };
91
92 pll5: clk@01c20020 {
93 #clock-cells = <1>;
94 compatible = "allwinner,sun4i-a10-pll5-clk";
95 reg = <0x01c20020 0x4>;
96 clocks = <&osc24M>;
97 clock-output-names = "pll5_ddr", "pll5_other";
98 };
99
100 pll6: clk@01c20028 {
101 #clock-cells = <1>;
102 compatible = "allwinner,sun4i-a10-pll6-clk";
103 reg = <0x01c20028 0x4>;
104 clocks = <&osc24M>;
105 clock-output-names = "pll6_sata", "pll6_other", "pll6";
106 };
107
108 /* dummy is 200M */
109 cpu: cpu@01c20054 {
110 #clock-cells = <0>;
111 compatible = "allwinner,sun4i-a10-cpu-clk";
112 reg = <0x01c20054 0x4>;
113 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
114 clock-output-names = "cpu";
115 };
116
117 axi: axi@01c20054 {
118 #clock-cells = <0>;
119 compatible = "allwinner,sun4i-a10-axi-clk";
120 reg = <0x01c20054 0x4>;
121 clocks = <&cpu>;
122 clock-output-names = "axi";
123 };
124
125 axi_gates: clk@01c2005c {
126 #clock-cells = <1>;
127 compatible = "allwinner,sun4i-a10-axi-gates-clk";
128 reg = <0x01c2005c 0x4>;
129 clocks = <&axi>;
130 clock-output-names = "axi_dram";
131 };
132
133 ahb: ahb@01c20054 {
134 #clock-cells = <0>;
135 compatible = "allwinner,sun4i-a10-ahb-clk";
136 reg = <0x01c20054 0x4>;
137 clocks = <&axi>;
138 clock-output-names = "ahb";
139 };
140
141 ahb_gates: clk@01c20060 {
142 #clock-cells = <1>;
143 compatible = "allwinner,sun4i-a10-ahb-gates-clk";
144 reg = <0x01c20060 0x8>;
145 clocks = <&ahb>;
146 clock-output-names = "ahb_usb0", "ahb_ehci0",
147 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
148 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
149 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
150 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
151 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
152 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
153 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
154 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
155 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
156 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
157 };
158
159 apb0: apb0@01c20054 {
160 #clock-cells = <0>;
161 compatible = "allwinner,sun4i-a10-apb0-clk";
162 reg = <0x01c20054 0x4>;
163 clocks = <&ahb>;
164 clock-output-names = "apb0";
165 };
166
167 apb0_gates: clk@01c20068 {
168 #clock-cells = <1>;
169 compatible = "allwinner,sun4i-a10-apb0-gates-clk";
170 reg = <0x01c20068 0x4>;
171 clocks = <&apb0>;
172 clock-output-names = "apb0_codec", "apb0_spdif",
173 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
174 "apb0_ir1", "apb0_keypad";
175 };
176
177 apb1_mux: apb1_mux@01c20058 {
178 #clock-cells = <0>;
179 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
180 reg = <0x01c20058 0x4>;
181 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
182 clock-output-names = "apb1_mux";
183 };
184
185 apb1: apb1@01c20058 {
186 #clock-cells = <0>;
187 compatible = "allwinner,sun4i-a10-apb1-clk";
188 reg = <0x01c20058 0x4>;
189 clocks = <&apb1_mux>;
190 clock-output-names = "apb1";
191 };
192
193 apb1_gates: clk@01c2006c {
194 #clock-cells = <1>;
195 compatible = "allwinner,sun4i-a10-apb1-gates-clk";
196 reg = <0x01c2006c 0x4>;
197 clocks = <&apb1>;
198 clock-output-names = "apb1_i2c0", "apb1_i2c1",
199 "apb1_i2c2", "apb1_can", "apb1_scr",
200 "apb1_ps20", "apb1_ps21", "apb1_uart0",
201 "apb1_uart1", "apb1_uart2", "apb1_uart3",
202 "apb1_uart4", "apb1_uart5", "apb1_uart6",
203 "apb1_uart7";
204 };
205
206 nand_clk: clk@01c20080 {
207 #clock-cells = <0>;
208 compatible = "allwinner,sun4i-a10-mod0-clk";
209 reg = <0x01c20080 0x4>;
210 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
211 clock-output-names = "nand";
212 };
213
214 ms_clk: clk@01c20084 {
215 #clock-cells = <0>;
216 compatible = "allwinner,sun4i-a10-mod0-clk";
217 reg = <0x01c20084 0x4>;
218 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
219 clock-output-names = "ms";
220 };
221
222 mmc0_clk: clk@01c20088 {
223 #clock-cells = <0>;
224 compatible = "allwinner,sun4i-a10-mod0-clk";
225 reg = <0x01c20088 0x4>;
226 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
227 clock-output-names = "mmc0";
228 };
229
230 mmc1_clk: clk@01c2008c {
231 #clock-cells = <0>;
232 compatible = "allwinner,sun4i-a10-mod0-clk";
233 reg = <0x01c2008c 0x4>;
234 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
235 clock-output-names = "mmc1";
236 };
237
238 mmc2_clk: clk@01c20090 {
239 #clock-cells = <0>;
240 compatible = "allwinner,sun4i-a10-mod0-clk";
241 reg = <0x01c20090 0x4>;
242 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
243 clock-output-names = "mmc2";
244 };
245
246 mmc3_clk: clk@01c20094 {
247 #clock-cells = <0>;
248 compatible = "allwinner,sun4i-a10-mod0-clk";
249 reg = <0x01c20094 0x4>;
250 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
251 clock-output-names = "mmc3";
252 };
253
254 ts_clk: clk@01c20098 {
255 #clock-cells = <0>;
256 compatible = "allwinner,sun4i-a10-mod0-clk";
257 reg = <0x01c20098 0x4>;
258 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
259 clock-output-names = "ts";
260 };
261
262 ss_clk: clk@01c2009c {
263 #clock-cells = <0>;
264 compatible = "allwinner,sun4i-a10-mod0-clk";
265 reg = <0x01c2009c 0x4>;
266 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
267 clock-output-names = "ss";
268 };
269
270 spi0_clk: clk@01c200a0 {
271 #clock-cells = <0>;
272 compatible = "allwinner,sun4i-a10-mod0-clk";
273 reg = <0x01c200a0 0x4>;
274 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
275 clock-output-names = "spi0";
276 };
277
278 spi1_clk: clk@01c200a4 {
279 #clock-cells = <0>;
280 compatible = "allwinner,sun4i-a10-mod0-clk";
281 reg = <0x01c200a4 0x4>;
282 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
283 clock-output-names = "spi1";
284 };
285
286 spi2_clk: clk@01c200a8 {
287 #clock-cells = <0>;
288 compatible = "allwinner,sun4i-a10-mod0-clk";
289 reg = <0x01c200a8 0x4>;
290 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
291 clock-output-names = "spi2";
292 };
293
294 pata_clk: clk@01c200ac {
295 #clock-cells = <0>;
296 compatible = "allwinner,sun4i-a10-mod0-clk";
297 reg = <0x01c200ac 0x4>;
298 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
299 clock-output-names = "pata";
300 };
301
302 ir0_clk: clk@01c200b0 {
303 #clock-cells = <0>;
304 compatible = "allwinner,sun4i-a10-mod0-clk";
305 reg = <0x01c200b0 0x4>;
306 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
307 clock-output-names = "ir0";
308 };
309
310 ir1_clk: clk@01c200b4 {
311 #clock-cells = <0>;
312 compatible = "allwinner,sun4i-a10-mod0-clk";
313 reg = <0x01c200b4 0x4>;
314 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
315 clock-output-names = "ir1";
316 };
317
318 usb_clk: clk@01c200cc {
319 #clock-cells = <1>;
320 #reset-cells = <1>;
321 compatible = "allwinner,sun4i-a10-usb-clk";
322 reg = <0x01c200cc 0x4>;
323 clocks = <&pll6 1>;
324 clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
325 };
326
327 spi3_clk: clk@01c200d4 {
328 #clock-cells = <0>;
329 compatible = "allwinner,sun4i-a10-mod0-clk";
330 reg = <0x01c200d4 0x4>;
331 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
332 clock-output-names = "spi3";
333 };
334 };
335
336 soc@01c00000 {
337 compatible = "simple-bus";
338 #address-cells = <1>;
339 #size-cells = <1>;
340 ranges;
341
342 spi0: spi@01c05000 {
343 compatible = "allwinner,sun4i-a10-spi";
344 reg = <0x01c05000 0x1000>;
345 interrupts = <10>;
346 clocks = <&ahb_gates 20>, <&spi0_clk>;
347 clock-names = "ahb", "mod";
348 status = "disabled";
349 #address-cells = <1>;
350 #size-cells = <0>;
351 };
352
353 spi1: spi@01c06000 {
354 compatible = "allwinner,sun4i-a10-spi";
355 reg = <0x01c06000 0x1000>;
356 interrupts = <11>;
357 clocks = <&ahb_gates 21>, <&spi1_clk>;
358 clock-names = "ahb", "mod";
359 status = "disabled";
360 #address-cells = <1>;
361 #size-cells = <0>;
362 };
363
364 emac: ethernet@01c0b000 {
365 compatible = "allwinner,sun4i-a10-emac";
366 reg = <0x01c0b000 0x1000>;
367 interrupts = <55>;
368 clocks = <&ahb_gates 17>;
369 status = "disabled";
370 };
371
372 mdio@01c0b080 {
373 compatible = "allwinner,sun4i-a10-mdio";
374 reg = <0x01c0b080 0x14>;
375 status = "disabled";
376 #address-cells = <1>;
377 #size-cells = <0>;
378 };
379
380 usbphy: phy@01c13400 {
381 #phy-cells = <1>;
382 compatible = "allwinner,sun4i-a10-usb-phy";
383 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
384 reg-names = "phy_ctrl", "pmu1", "pmu2";
385 clocks = <&usb_clk 8>;
386 clock-names = "usb_phy";
387 resets = <&usb_clk 1>, <&usb_clk 2>;
388 reset-names = "usb1_reset", "usb2_reset";
389 status = "disabled";
390 };
391
392 ehci0: usb@01c14000 {
393 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
394 reg = <0x01c14000 0x100>;
395 interrupts = <39>;
396 clocks = <&ahb_gates 1>;
397 phys = <&usbphy 1>;
398 phy-names = "usb";
399 status = "disabled";
400 };
401
402 ohci0: usb@01c14400 {
403 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
404 reg = <0x01c14400 0x100>;
405 interrupts = <64>;
406 clocks = <&usb_clk 6>, <&ahb_gates 2>;
407 phys = <&usbphy 1>;
408 phy-names = "usb";
409 status = "disabled";
410 };
411
412 spi2: spi@01c17000 {
413 compatible = "allwinner,sun4i-a10-spi";
414 reg = <0x01c17000 0x1000>;
415 interrupts = <12>;
416 clocks = <&ahb_gates 22>, <&spi2_clk>;
417 clock-names = "ahb", "mod";
418 status = "disabled";
419 #address-cells = <1>;
420 #size-cells = <0>;
421 };
422
423 ahci: sata@01c18000 {
424 compatible = "allwinner,sun4i-a10-ahci";
425 reg = <0x01c18000 0x1000>;
426 interrupts = <56>;
427 clocks = <&pll6 0>, <&ahb_gates 25>;
428 status = "disabled";
429 };
430
431 ehci1: usb@01c1c000 {
432 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
433 reg = <0x01c1c000 0x100>;
434 interrupts = <40>;
435 clocks = <&ahb_gates 3>;
436 phys = <&usbphy 2>;
437 phy-names = "usb";
438 status = "disabled";
439 };
440
441 ohci1: usb@01c1c400 {
442 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
443 reg = <0x01c1c400 0x100>;
444 interrupts = <65>;
445 clocks = <&usb_clk 7>, <&ahb_gates 4>;
446 phys = <&usbphy 2>;
447 phy-names = "usb";
448 status = "disabled";
449 };
450
451 spi3: spi@01c1f000 {
452 compatible = "allwinner,sun4i-a10-spi";
453 reg = <0x01c1f000 0x1000>;
454 interrupts = <50>;
455 clocks = <&ahb_gates 23>, <&spi3_clk>;
456 clock-names = "ahb", "mod";
457 status = "disabled";
458 #address-cells = <1>;
459 #size-cells = <0>;
460 };
461
462 intc: interrupt-controller@01c20400 {
463 compatible = "allwinner,sun4i-a10-ic";
464 reg = <0x01c20400 0x400>;
465 interrupt-controller;
466 #interrupt-cells = <1>;
467 };
468
469 pio: pinctrl@01c20800 {
470 compatible = "allwinner,sun4i-a10-pinctrl";
471 reg = <0x01c20800 0x400>;
472 interrupts = <28>;
473 clocks = <&apb0_gates 5>;
474 gpio-controller;
475 interrupt-controller;
476 #address-cells = <1>;
477 #size-cells = <0>;
478 #gpio-cells = <3>;
479
480 uart0_pins_a: uart0@0 {
481 allwinner,pins = "PB22", "PB23";
482 allwinner,function = "uart0";
483 allwinner,drive = <0>;
484 allwinner,pull = <0>;
485 };
486
487 uart0_pins_b: uart0@1 {
488 allwinner,pins = "PF2", "PF4";
489 allwinner,function = "uart0";
490 allwinner,drive = <0>;
491 allwinner,pull = <0>;
492 };
493
494 uart1_pins_a: uart1@0 {
495 allwinner,pins = "PA10", "PA11";
496 allwinner,function = "uart1";
497 allwinner,drive = <0>;
498 allwinner,pull = <0>;
499 };
500
501 i2c0_pins_a: i2c0@0 {
502 allwinner,pins = "PB0", "PB1";
503 allwinner,function = "i2c0";
504 allwinner,drive = <0>;
505 allwinner,pull = <0>;
506 };
507
508 i2c1_pins_a: i2c1@0 {
509 allwinner,pins = "PB18", "PB19";
510 allwinner,function = "i2c1";
511 allwinner,drive = <0>;
512 allwinner,pull = <0>;
513 };
514
515 i2c2_pins_a: i2c2@0 {
516 allwinner,pins = "PB20", "PB21";
517 allwinner,function = "i2c2";
518 allwinner,drive = <0>;
519 allwinner,pull = <0>;
520 };
521
522 emac_pins_a: emac0@0 {
523 allwinner,pins = "PA0", "PA1", "PA2",
524 "PA3", "PA4", "PA5", "PA6",
525 "PA7", "PA8", "PA9", "PA10",
526 "PA11", "PA12", "PA13", "PA14",
527 "PA15", "PA16";
528 allwinner,function = "emac";
529 allwinner,drive = <0>;
530 allwinner,pull = <0>;
531 };
532 };
533
534 timer@01c20c00 {
535 compatible = "allwinner,sun4i-a10-timer";
536 reg = <0x01c20c00 0x90>;
537 interrupts = <22>;
538 clocks = <&osc24M>;
539 };
540
541 wdt: watchdog@01c20c90 {
542 compatible = "allwinner,sun4i-a10-wdt";
543 reg = <0x01c20c90 0x10>;
544 };
545
546 rtc: rtc@01c20d00 {
547 compatible = "allwinner,sun4i-a10-rtc";
548 reg = <0x01c20d00 0x20>;
549 interrupts = <24>;
550 };
551
552 sid: eeprom@01c23800 {
553 compatible = "allwinner,sun4i-a10-sid";
554 reg = <0x01c23800 0x10>;
555 };
556
557 rtp: rtp@01c25000 {
558 compatible = "allwinner,sun4i-a10-ts";
559 reg = <0x01c25000 0x100>;
560 interrupts = <29>;
561 };
562
563 uart0: serial@01c28000 {
564 compatible = "snps,dw-apb-uart";
565 reg = <0x01c28000 0x400>;
566 interrupts = <1>;
567 reg-shift = <2>;
568 reg-io-width = <4>;
569 clocks = <&apb1_gates 16>;
570 status = "disabled";
571 };
572
573 uart1: serial@01c28400 {
574 compatible = "snps,dw-apb-uart";
575 reg = <0x01c28400 0x400>;
576 interrupts = <2>;
577 reg-shift = <2>;
578 reg-io-width = <4>;
579 clocks = <&apb1_gates 17>;
580 status = "disabled";
581 };
582
583 uart2: serial@01c28800 {
584 compatible = "snps,dw-apb-uart";
585 reg = <0x01c28800 0x400>;
586 interrupts = <3>;
587 reg-shift = <2>;
588 reg-io-width = <4>;
589 clocks = <&apb1_gates 18>;
590 status = "disabled";
591 };
592
593 uart3: serial@01c28c00 {
594 compatible = "snps,dw-apb-uart";
595 reg = <0x01c28c00 0x400>;
596 interrupts = <4>;
597 reg-shift = <2>;
598 reg-io-width = <4>;
599 clocks = <&apb1_gates 19>;
600 status = "disabled";
601 };
602
603 uart4: serial@01c29000 {
604 compatible = "snps,dw-apb-uart";
605 reg = <0x01c29000 0x400>;
606 interrupts = <17>;
607 reg-shift = <2>;
608 reg-io-width = <4>;
609 clocks = <&apb1_gates 20>;
610 status = "disabled";
611 };
612
613 uart5: serial@01c29400 {
614 compatible = "snps,dw-apb-uart";
615 reg = <0x01c29400 0x400>;
616 interrupts = <18>;
617 reg-shift = <2>;
618 reg-io-width = <4>;
619 clocks = <&apb1_gates 21>;
620 status = "disabled";
621 };
622
623 uart6: serial@01c29800 {
624 compatible = "snps,dw-apb-uart";
625 reg = <0x01c29800 0x400>;
626 interrupts = <19>;
627 reg-shift = <2>;
628 reg-io-width = <4>;
629 clocks = <&apb1_gates 22>;
630 status = "disabled";
631 };
632
633 uart7: serial@01c29c00 {
634 compatible = "snps,dw-apb-uart";
635 reg = <0x01c29c00 0x400>;
636 interrupts = <20>;
637 reg-shift = <2>;
638 reg-io-width = <4>;
639 clocks = <&apb1_gates 23>;
640 status = "disabled";
641 };
642
643 i2c0: i2c@01c2ac00 {
644 compatible = "allwinner,sun4i-i2c";
645 reg = <0x01c2ac00 0x400>;
646 interrupts = <7>;
647 clocks = <&apb1_gates 0>;
648 clock-frequency = <100000>;
649 status = "disabled";
650 };
651
652 i2c1: i2c@01c2b000 {
653 compatible = "allwinner,sun4i-i2c";
654 reg = <0x01c2b000 0x400>;
655 interrupts = <8>;
656 clocks = <&apb1_gates 1>;
657 clock-frequency = <100000>;
658 status = "disabled";
659 };
660
661 i2c2: i2c@01c2b400 {
662 compatible = "allwinner,sun4i-i2c";
663 reg = <0x01c2b400 0x400>;
664 interrupts = <9>;
665 clocks = <&apb1_gates 2>;
666 clock-frequency = <100000>;
667 status = "disabled";
668 };
669 };
670};