Loading...
1/*
2 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx53-m53.dtsi"
14
15/ {
16 model = "Aries/DENX M53EVK";
17 compatible = "aries,imx53-m53evk", "denx,imx53-m53evk", "fsl,imx53";
18
19 display1: disp1 {
20 compatible = "fsl,imx-parallel-display";
21 interface-pix-fmt = "bgr666";
22 pinctrl-names = "default";
23 pinctrl-0 = <&pinctrl_ipu_disp1>;
24
25 display-timings {
26 800x480p60 {
27 native-mode;
28 clock-frequency = <31500000>;
29 hactive = <800>;
30 vactive = <480>;
31 hfront-porch = <40>;
32 hback-porch = <88>;
33 hsync-len = <128>;
34 vback-porch = <33>;
35 vfront-porch = <9>;
36 vsync-len = <3>;
37 vsync-active = <1>;
38 };
39 };
40
41 port {
42 display1_in: endpoint {
43 remote-endpoint = <&ipu_di1_disp1>;
44 };
45 };
46 };
47
48 backlight {
49 compatible = "pwm-backlight";
50 pwms = <&pwm1 0 3000>;
51 brightness-levels = <0 4 8 16 32 64 128 255>;
52 default-brightness-level = <6>;
53 power-supply = <®_backlight>;
54 };
55
56 leds {
57 compatible = "gpio-leds";
58 pinctrl-names = "default";
59 pinctrl-0 = <&led_pin_gpio>;
60
61 user1 {
62 label = "user1";
63 gpios = <&gpio2 8 0>;
64 linux,default-trigger = "heartbeat";
65 };
66
67 user2 {
68 label = "user2";
69 gpios = <&gpio2 9 0>;
70 linux,default-trigger = "heartbeat";
71 };
72 };
73
74 regulators {
75 compatible = "simple-bus";
76 #address-cells = <1>;
77 #size-cells = <0>;
78
79 reg_usbh1_vbus: regulator@3 {
80 compatible = "regulator-fixed";
81 reg = <3>;
82 regulator-name = "vbus";
83 regulator-min-microvolt = <5000000>;
84 regulator-max-microvolt = <5000000>;
85 gpio = <&gpio1 2 0>;
86 };
87
88 reg_usb_otg_vbus: regulator@4 {
89 compatible = "regulator-fixed";
90 reg = <4>;
91 regulator-name = "usb_otg_vbus";
92 regulator-min-microvolt = <5000000>;
93 regulator-max-microvolt = <5000000>;
94 gpio = <&gpio1 4 0>;
95 };
96 };
97
98 sound {
99 compatible = "fsl,imx53-m53evk-sgtl5000",
100 "fsl,imx-audio-sgtl5000";
101 model = "imx53-m53evk-sgtl5000";
102 ssi-controller = <&ssi2>;
103 audio-codec = <&sgtl5000>;
104 audio-routing =
105 "MIC_IN", "Mic Jack",
106 "Mic Jack", "Mic Bias",
107 "LINE_IN", "Line In Jack",
108 "Headphone Jack", "HP_OUT",
109 "Ext Spk", "LINE_OUT";
110 mux-int-port = <2>;
111 mux-ext-port = <4>;
112 };
113};
114
115&audmux {
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_audmux>;
118 status = "okay";
119};
120
121&can1 {
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_can1>;
124 status = "okay";
125};
126
127&can2 {
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_can2>;
130 status = "okay";
131};
132
133&esdhc1 {
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_esdhc1>;
136 cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
137 wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
138 status = "okay";
139};
140
141&fec {
142 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_fec>;
144 phy-mode = "rmii";
145 status = "okay";
146};
147
148&i2c1 {
149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_i2c1>;
151 status = "okay";
152
153 sgtl5000: codec@a {
154 compatible = "fsl,sgtl5000";
155 reg = <0x0a>;
156 #sound-dai-cells = <0>;
157 VDDA-supply = <®_3p2v>;
158 VDDIO-supply = <®_3p2v>;
159 clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
160 };
161};
162
163&i2c3 {
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_i2c3>;
166 status = "okay";
167};
168
169&iomuxc {
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_hog>;
172
173 imx53-m53evk {
174 pinctrl_usb: usbgrp {
175 fsl,pins = <
176 MX53_PAD_GPIO_2__GPIO1_2 0x80000000
177 MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x80000000
178 >;
179 };
180
181 pinctrl_usbotg: usbotggrp {
182 fsl,pins = <
183 MX53_PAD_GPIO_4__GPIO1_4 0x000b0
184 >;
185 };
186
187 led_pin_gpio: led_gpio {
188 fsl,pins = <
189 MX53_PAD_PATA_DATA8__GPIO2_8 0x80000000
190 MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000
191 >;
192 };
193
194 pinctrl_audmux: audmuxgrp {
195 fsl,pins = <
196 MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000
197 MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000
198 MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000
199 MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000
200 >;
201 };
202
203 pinctrl_can1: can1grp {
204 fsl,pins = <
205 MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000
206 MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000
207 >;
208 };
209
210 pinctrl_can2: can2grp {
211 fsl,pins = <
212 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
213 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
214 >;
215 };
216
217 pinctrl_esdhc1: esdhc1grp {
218 fsl,pins = <
219 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
220 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
221 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
222 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
223 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
224 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
225 >;
226 };
227
228 pinctrl_fec: fecgrp {
229 fsl,pins = <
230 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
231 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
232 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
233 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
234 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
235 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
236 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
237 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
238 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
239 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
240 >;
241 };
242
243 pinctrl_i2c1: i2c1grp {
244 fsl,pins = <
245 MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
246 MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
247 >;
248 };
249
250 pinctrl_i2c3: i2c3grp {
251 fsl,pins = <
252 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
253 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
254 >;
255 };
256
257 pinctrl_ipu_disp1: ipudisp1grp {
258 fsl,pins = <
259 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5
260 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5
261 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5
262 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5
263 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5
264 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5
265 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5
266 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5
267 MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5
268 MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5
269 MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5
270 MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5
271 MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5
272 MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5
273 MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5
274 MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5
275 MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5
276 MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5
277 MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5
278 MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5
279 MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5
280 MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5
281 MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5
282 MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5
283 MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5
284 MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5
285 MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5
286 MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5
287 MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5
288 MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5
289 MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5
290 MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5
291 >;
292 };
293
294 pinctrl_pwm1: pwm1grp {
295 fsl,pins = <
296 MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
297 >;
298 };
299
300 pinctrl_uart1: uart1grp {
301 fsl,pins = <
302 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
303 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
304 >;
305 };
306
307 pinctrl_uart2: uart2grp {
308 fsl,pins = <
309 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
310 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
311 >;
312 };
313
314 pinctrl_uart3: uart3grp {
315 fsl,pins = <
316 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
317 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
318 MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
319 MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
320 >;
321 };
322 };
323};
324
325&ipu_di1_disp1 {
326 remote-endpoint = <&display1_in>;
327};
328
329&pwm1 {
330 pinctrl-names = "default";
331 pinctrl-0 = <&pinctrl_pwm1>;
332 status = "okay";
333};
334
335&sata {
336 status = "okay";
337};
338
339&ssi2 {
340 status = "okay";
341};
342
343&uart1 {
344 pinctrl-names = "default";
345 pinctrl-0 = <&pinctrl_uart1>;
346 status = "okay";
347};
348
349&uart2 {
350 pinctrl-names = "default";
351 pinctrl-0 = <&pinctrl_uart2>;
352 status = "okay";
353};
354
355&uart3 {
356 pinctrl-names = "default";
357 pinctrl-0 = <&pinctrl_uart3>;
358 status = "okay";
359};
360
361&usbh1 {
362 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_usb>;
364 vbus-supply = <®_usbh1_vbus>;
365 phy_type = "utmi";
366 status = "okay";
367};
368
369&usbotg {
370 pinctrl-names = "default";
371 pinctrl-0 = <&pinctrl_usbotg>;
372 dr_mode = "otg";
373 vbus-supply = <®_usb_otg_vbus>;
374 disable-over-current;
375 status = "okay";
376};
1/*
2 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx53.dtsi"
14
15/ {
16 model = "DENX M53EVK";
17 compatible = "denx,imx53-m53evk", "fsl,imx53";
18
19 memory {
20 reg = <0x70000000 0x20000000>,
21 <0xb0000000 0x20000000>;
22 };
23
24 soc {
25 display1: display@di1 {
26 compatible = "fsl,imx-parallel-display";
27 interface-pix-fmt = "bgr666";
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_ipu_disp1>;
30
31 display-timings {
32 800x480p60 {
33 native-mode;
34 clock-frequency = <31500000>;
35 hactive = <800>;
36 vactive = <480>;
37 hfront-porch = <40>;
38 hback-porch = <88>;
39 hsync-len = <128>;
40 vback-porch = <33>;
41 vfront-porch = <9>;
42 vsync-len = <3>;
43 vsync-active = <1>;
44 };
45 };
46 };
47
48 port {
49 display1_in: endpoint {
50 remote-endpoint = <&ipu_di1_disp1>;
51 };
52 };
53 };
54
55 backlight {
56 compatible = "pwm-backlight";
57 pwms = <&pwm1 0 3000>;
58 brightness-levels = <0 4 8 16 32 64 128 255>;
59 default-brightness-level = <6>;
60 power-supply = <®_backlight>;
61 };
62
63 leds {
64 compatible = "gpio-leds";
65 pinctrl-names = "default";
66 pinctrl-0 = <&led_pin_gpio>;
67
68 user1 {
69 label = "user1";
70 gpios = <&gpio2 8 0>;
71 linux,default-trigger = "heartbeat";
72 };
73
74 user2 {
75 label = "user2";
76 gpios = <&gpio2 9 0>;
77 linux,default-trigger = "heartbeat";
78 };
79 };
80
81 regulators {
82 compatible = "simple-bus";
83 #address-cells = <1>;
84 #size-cells = <0>;
85
86 reg_3p2v: regulator@0 {
87 compatible = "regulator-fixed";
88 reg = <0>;
89 regulator-name = "3P2V";
90 regulator-min-microvolt = <3200000>;
91 regulator-max-microvolt = <3200000>;
92 regulator-always-on;
93 };
94
95
96 reg_backlight: regulator@1 {
97 compatible = "regulator-fixed";
98 reg = <1>;
99 regulator-name = "lcd-supply";
100 regulator-min-microvolt = <3200000>;
101 regulator-max-microvolt = <3200000>;
102 regulator-always-on;
103 };
104
105 reg_usbh1_vbus: regulator@3 {
106 compatible = "regulator-fixed";
107 reg = <3>;
108 regulator-name = "vbus";
109 regulator-min-microvolt = <5000000>;
110 regulator-max-microvolt = <5000000>;
111 gpio = <&gpio1 2 0>;
112 };
113 };
114
115 sound {
116 compatible = "fsl,imx53-m53evk-sgtl5000",
117 "fsl,imx-audio-sgtl5000";
118 model = "imx53-m53evk-sgtl5000";
119 ssi-controller = <&ssi2>;
120 audio-codec = <&sgtl5000>;
121 audio-routing =
122 "MIC_IN", "Mic Jack",
123 "Mic Jack", "Mic Bias",
124 "LINE_IN", "Line In Jack",
125 "Headphone Jack", "HP_OUT",
126 "Ext Spk", "LINE_OUT";
127 mux-int-port = <2>;
128 mux-ext-port = <4>;
129 };
130};
131
132&audmux {
133 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_audmux>;
135 status = "okay";
136};
137
138&can1 {
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_can1>;
141 status = "okay";
142};
143
144&can2 {
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_can2>;
147 status = "okay";
148};
149
150&esdhc1 {
151 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_esdhc1>;
153 cd-gpios = <&gpio1 1 0>;
154 wp-gpios = <&gpio1 9 0>;
155 status = "okay";
156};
157
158&fec {
159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_fec>;
161 phy-mode = "rmii";
162 status = "okay";
163};
164
165&i2c1 {
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_i2c1>;
168 status = "okay";
169
170 sgtl5000: codec@0a {
171 compatible = "fsl,sgtl5000";
172 reg = <0x0a>;
173 VDDA-supply = <®_3p2v>;
174 VDDIO-supply = <®_3p2v>;
175 clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
176 };
177};
178
179&i2c2 {
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_i2c2>;
182 clock-frequency = <400000>;
183 status = "okay";
184
185 stmpe610@41 {
186 compatible = "st,stmpe610";
187 #address-cells = <1>;
188 #size-cells = <0>;
189 reg = <0x41>;
190 id = <0>;
191 blocks = <0x5>;
192 interrupts = <6 0x0>;
193 interrupt-parent = <&gpio7>;
194 irq-trigger = <0x1>;
195
196 stmpe_touchscreen {
197 compatible = "st,stmpe-ts";
198 reg = <0>;
199 st,sample-time = <4>;
200 st,mod-12b = <1>;
201 st,ref-sel = <0>;
202 st,adc-freq = <1>;
203 st,ave-ctrl = <3>;
204 st,touch-det-delay = <3>;
205 st,settling = <4>;
206 st,fraction-z = <7>;
207 st,i-drive = <1>;
208 };
209 };
210
211 eeprom: eeprom@50 {
212 compatible = "atmel,24c128";
213 reg = <0x50>;
214 pagesize = <32>;
215 };
216
217 rtc: rtc@68 {
218 compatible = "stm,m41t62";
219 reg = <0x68>;
220 };
221};
222
223&i2c3 {
224 pinctrl-names = "default";
225 pinctrl-0 = <&pinctrl_i2c3>;
226 status = "okay";
227};
228
229&iomuxc {
230 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_hog>;
232
233 imx53-m53evk {
234 pinctrl_hog: hoggrp {
235 fsl,pins = <
236 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
237 MX53_PAD_EIM_EB3__GPIO2_31 0x80000000
238 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
239 MX53_PAD_GPIO_2__GPIO1_2 0x80000000
240 MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x80000000
241 >;
242 };
243
244 led_pin_gpio: led_gpio@0 {
245 fsl,pins = <
246 MX53_PAD_PATA_DATA8__GPIO2_8 0x80000000
247 MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000
248 >;
249 };
250
251 pinctrl_audmux: audmuxgrp {
252 fsl,pins = <
253 MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000
254 MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000
255 MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000
256 MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000
257 >;
258 };
259
260 pinctrl_can1: can1grp {
261 fsl,pins = <
262 MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000
263 MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000
264 >;
265 };
266
267 pinctrl_can2: can2grp {
268 fsl,pins = <
269 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
270 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
271 >;
272 };
273
274 pinctrl_esdhc1: esdhc1grp {
275 fsl,pins = <
276 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
277 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
278 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
279 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
280 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
281 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
282 >;
283 };
284
285 pinctrl_fec: fecgrp {
286 fsl,pins = <
287 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
288 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
289 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
290 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
291 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
292 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
293 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
294 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
295 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
296 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
297 >;
298 };
299
300 pinctrl_i2c1: i2c1grp {
301 fsl,pins = <
302 MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
303 MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
304 >;
305 };
306
307 pinctrl_i2c2: i2c2grp {
308 fsl,pins = <
309 MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
310 MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
311 >;
312 };
313
314 pinctrl_i2c3: i2c3grp {
315 fsl,pins = <
316 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
317 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
318 >;
319 };
320
321 pinctrl_ipu_disp1: ipudisp1grp {
322 fsl,pins = <
323 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5
324 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5
325 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5
326 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5
327 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5
328 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5
329 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5
330 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5
331 MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5
332 MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5
333 MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5
334 MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5
335 MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5
336 MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5
337 MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5
338 MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5
339 MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5
340 MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5
341 MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5
342 MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5
343 MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5
344 MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5
345 MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5
346 MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5
347 MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5
348 MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5
349 MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5
350 MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5
351 MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5
352 MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5
353 MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5
354 MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5
355 >;
356 };
357
358 pinctrl_nand: nandgrp {
359 fsl,pins = <
360 MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
361 MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
362 MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
363 MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
364 MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
365 MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
366 MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
367 MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
368 MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
369 MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
370 MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
371 MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
372 MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
373 MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
374 MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
375 >;
376 };
377
378 pinctrl_pwm1: pwm1grp {
379 fsl,pins = <
380 MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
381 >;
382 };
383
384 pinctrl_uart1: uart1grp {
385 fsl,pins = <
386 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
387 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
388 >;
389 };
390
391 pinctrl_uart2: uart2grp {
392 fsl,pins = <
393 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
394 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
395 >;
396 };
397
398 pinctrl_uart3: uart3grp {
399 fsl,pins = <
400 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
401 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
402 MX53_PAD_PATA_DA_1__UART3_CTS 0x1e4
403 MX53_PAD_PATA_DA_2__UART3_RTS 0x1e4
404 >;
405 };
406 };
407};
408
409&ipu_di1_disp1 {
410 remote-endpoint = <&display1_in>;
411};
412
413&nfc {
414 pinctrl-names = "default";
415 pinctrl-0 = <&pinctrl_nand>;
416 nand-bus-width = <8>;
417 nand-ecc-mode = "hw";
418 status = "okay";
419};
420
421&pwm1 {
422 pinctrl-names = "default";
423 pinctrl-0 = <&pinctrl_pwm1>;
424 status = "okay";
425};
426
427&sata {
428 status = "okay";
429};
430
431&ssi2 {
432 fsl,mode = "i2s-slave";
433 status = "okay";
434};
435
436&uart1 {
437 pinctrl-names = "default";
438 pinctrl-0 = <&pinctrl_uart1>;
439 status = "okay";
440};
441
442&uart2 {
443 pinctrl-names = "default";
444 pinctrl-0 = <&pinctrl_uart2>;
445 status = "okay";
446};
447
448&uart3 {
449 pinctrl-names = "default";
450 pinctrl-0 = <&pinctrl_uart3>;
451 status = "okay";
452};
453
454&usbh1 {
455 vbus-supply = <®_usbh1_vbus>;
456 phy_type = "utmi";
457 status = "okay";
458};
459
460&usbotg {
461 dr_mode = "peripheral";
462 status = "okay";
463};