1# SPDX-License-Identifier: GPL-2.0
   2config ARM
   3	bool
   4	default y
   5	select ARCH_CLOCKSOURCE_DATA
   6	select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID && !KEXEC
   7	select ARCH_HAS_DEBUG_VIRTUAL if MMU
   8	select ARCH_HAS_DEVMEM_IS_ALLOWED
   9	select ARCH_HAS_ELF_RANDOMIZE
  10	select ARCH_HAS_FORTIFY_SOURCE
  11	select ARCH_HAS_SET_MEMORY
  12	select ARCH_HAS_PHYS_TO_DMA
  13	select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
  14	select ARCH_HAS_STRICT_MODULE_RWX if MMU
  15	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
  16	select ARCH_HAVE_CUSTOM_GPIO_H
  17	select ARCH_HAS_GCOV_PROFILE_ALL
  18	select ARCH_MIGHT_HAVE_PC_PARPORT
  19	select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
  20	select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
  21	select ARCH_SUPPORTS_ATOMIC_RMW
  22	select ARCH_USE_BUILTIN_BSWAP
  23	select ARCH_USE_CMPXCHG_LOCKREF
  24	select ARCH_WANT_IPC_PARSE_VERSION
  25	select BUILDTIME_EXTABLE_SORT if MMU
  26	select CLONE_BACKWARDS
  27	select CPU_PM if (SUSPEND || CPU_IDLE)
  28	select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  29	select DMA_DIRECT_OPS if !MMU
  30	select EDAC_SUPPORT
  31	select EDAC_ATOMIC_SCRUB
  32	select GENERIC_ALLOCATOR
  33	select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
  34	select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  35	select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  36	select GENERIC_CPU_AUTOPROBE
  37	select GENERIC_EARLY_IOREMAP
  38	select GENERIC_IDLE_POLL_SETUP
  39	select GENERIC_IRQ_PROBE
  40	select GENERIC_IRQ_SHOW
  41	select GENERIC_IRQ_SHOW_LEVEL
  42	select GENERIC_PCI_IOMAP
  43	select GENERIC_SCHED_CLOCK
  44	select GENERIC_SMP_IDLE_THREAD
  45	select GENERIC_STRNCPY_FROM_USER
  46	select GENERIC_STRNLEN_USER
  47	select HANDLE_DOMAIN_IRQ
  48	select HARDIRQS_SW_RESEND
  49	select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  50	select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  51	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
  52	select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
  53	select HAVE_ARCH_MMAP_RND_BITS if MMU
  54	select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  55	select HAVE_ARCH_THREAD_STRUCT_WHITELIST
  56	select HAVE_ARCH_TRACEHOOK
  57	select HAVE_ARM_SMCCC if CPU_V7
  58	select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
  59	select HAVE_CC_STACKPROTECTOR
  60	select HAVE_CONTEXT_TRACKING
  61	select HAVE_C_RECORDMCOUNT
  62	select HAVE_DEBUG_KMEMLEAK
  63	select HAVE_DMA_API_DEBUG
 
  64	select HAVE_DMA_CONTIGUOUS if MMU
  65	select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
  66	select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
  67	select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  68	select HAVE_EXIT_THREAD
  69	select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  70	select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  71	select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  72	select HAVE_GCC_PLUGINS
  73	select HAVE_GENERIC_DMA_COHERENT
  74	select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  75	select HAVE_IDE if PCI || ISA || PCMCIA
  76	select HAVE_IRQ_TIME_ACCOUNTING
  77	select HAVE_KERNEL_GZIP
  78	select HAVE_KERNEL_LZ4
  79	select HAVE_KERNEL_LZMA
  80	select HAVE_KERNEL_LZO
  81	select HAVE_KERNEL_XZ
  82	select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
  83	select HAVE_KRETPROBES if (HAVE_KPROBES)
  84	select HAVE_MEMBLOCK
  85	select HAVE_MOD_ARCH_SPECIFIC
  86	select HAVE_NMI
  87	select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  88	select HAVE_OPTPROBES if !THUMB2_KERNEL
  89	select HAVE_PERF_EVENTS
  90	select HAVE_PERF_REGS
  91	select HAVE_PERF_USER_STACK_DUMP
  92	select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  93	select HAVE_REGS_AND_STACK_ACCESS_API
  94	select HAVE_SYSCALL_TRACEPOINTS
  95	select HAVE_UID16
  96	select HAVE_VIRT_CPU_ACCOUNTING_GEN
  97	select IRQ_FORCED_THREADING
 
  98	select MODULES_USE_ELF_REL
  99	select NO_BOOTMEM
 100	select OF_EARLY_FLATTREE if OF
 101	select OF_RESERVED_MEM if OF
 102	select OLD_SIGACTION
 103	select OLD_SIGSUSPEND3
 104	select PERF_USE_VMALLOC
 105	select REFCOUNT_FULL
 106	select RTC_LIB
 107	select SYS_SUPPORTS_APM_EMULATION
 108	# Above selects are sorted alphabetically; please add new ones
 109	# according to that.  Thanks.
 110	help
 111	  The ARM series is a line of low-power-consumption RISC chip designs
 112	  licensed by ARM Ltd and targeted at embedded applications and
 113	  handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
 114	  manufactured, but legacy ARM-based PC hardware remains popular in
 115	  Europe.  There is an ARM Linux project with a web page at
 116	  <http://www.arm.linux.org.uk/>.
 117
 118config ARM_HAS_SG_CHAIN
 119	select ARCH_HAS_SG_CHAIN
 120	bool
 121
 122config NEED_SG_DMA_LENGTH
 123	bool
 124
 125config ARM_DMA_USE_IOMMU
 126	bool
 127	select ARM_HAS_SG_CHAIN
 128	select NEED_SG_DMA_LENGTH
 129
 130if ARM_DMA_USE_IOMMU
 131
 132config ARM_DMA_IOMMU_ALIGNMENT
 133	int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 134	range 4 9
 135	default 8
 136	help
 137	  DMA mapping framework by default aligns all buffers to the smallest
 138	  PAGE_SIZE order which is greater than or equal to the requested buffer
 139	  size. This works well for buffers up to a few hundreds kilobytes, but
 140	  for larger buffers it just a waste of address space. Drivers which has
 141	  relatively small addressing window (like 64Mib) might run out of
 142	  virtual space with just a few allocations.
 143
 144	  With this parameter you can specify the maximum PAGE_SIZE order for
 145	  DMA IOMMU buffers. Larger buffers will be aligned only to this
 146	  specified order. The order is expressed as a power of two multiplied
 147	  by the PAGE_SIZE.
 148
 149endif
 150
 151config MIGHT_HAVE_PCI
 152	bool
 153
 154config SYS_SUPPORTS_APM_EMULATION
 155	bool
 156
 157config HAVE_TCM
 158	bool
 159	select GENERIC_ALLOCATOR
 160
 161config HAVE_PROC_CPU
 162	bool
 163
 164config NO_IOPORT_MAP
 165	bool
 166
 167config EISA
 168	bool
 169	---help---
 170	  The Extended Industry Standard Architecture (EISA) bus was
 171	  developed as an open alternative to the IBM MicroChannel bus.
 172
 173	  The EISA bus provided some of the features of the IBM MicroChannel
 174	  bus while maintaining backward compatibility with cards made for
 175	  the older ISA bus.  The EISA bus saw limited use between 1988 and
 176	  1995 when it was made obsolete by the PCI bus.
 177
 178	  Say Y here if you are building a kernel for an EISA-based machine.
 179
 180	  Otherwise, say N.
 181
 182config SBUS
 183	bool
 184
 185config STACKTRACE_SUPPORT
 186	bool
 187	default y
 188
 
 
 
 
 
 189config LOCKDEP_SUPPORT
 190	bool
 191	default y
 192
 193config TRACE_IRQFLAGS_SUPPORT
 194	bool
 195	default !CPU_V7M
 196
 197config RWSEM_XCHGADD_ALGORITHM
 198	bool
 199	default y
 200
 
 
 
 201config ARCH_HAS_ILOG2_U32
 202	bool
 203
 204config ARCH_HAS_ILOG2_U64
 205	bool
 206
 207config ARCH_HAS_BANDGAP
 208	bool
 
 
 
 
 209
 210config FIX_EARLYCON_MEM
 211	def_bool y if MMU
 212
 213config GENERIC_HWEIGHT
 214	bool
 215	default y
 216
 217config GENERIC_CALIBRATE_DELAY
 218	bool
 219	default y
 220
 221config ARCH_MAY_HAVE_PC_FDC
 222	bool
 223
 224config ZONE_DMA
 225	bool
 226
 227config NEED_DMA_MAP_STATE
 228       def_bool y
 229
 230config ARCH_SUPPORTS_UPROBES
 231	def_bool y
 232
 233config ARCH_HAS_DMA_SET_COHERENT_MASK
 234	bool
 235
 236config GENERIC_ISA_DMA
 237	bool
 238
 239config FIQ
 240	bool
 241
 242config NEED_RET_TO_USER
 243	bool
 244
 245config ARCH_MTD_XIP
 246	bool
 247
 
 
 
 
 
 
 
 
 
 248config ARM_PATCH_PHYS_VIRT
 249	bool "Patch physical to virtual translations at runtime" if EMBEDDED
 250	default y
 251	depends on !XIP_KERNEL && MMU
 
 252	help
 253	  Patch phys-to-virt and virt-to-phys translation functions at
 254	  boot and module load time according to the position of the
 255	  kernel in system memory.
 256
 257	  This can only be used with non-XIP MMU kernels where the base
 258	  of physical memory is at a 16MB boundary.
 259
 260	  Only disable this option if you know that you do not require
 261	  this feature (eg, building a kernel for a single machine) and
 262	  you need to shrink the kernel to the minimal size.
 263
 
 
 
 
 
 
 
 264config NEED_MACH_IO_H
 265	bool
 266	help
 267	  Select this when mach/io.h is required to provide special
 268	  definitions for this platform.  The need for mach/io.h should
 269	  be avoided when possible.
 270
 271config NEED_MACH_MEMORY_H
 272	bool
 273	help
 274	  Select this when mach/memory.h is required to provide special
 275	  definitions for this platform.  The need for mach/memory.h should
 276	  be avoided when possible.
 277
 278config PHYS_OFFSET
 279	hex "Physical address of main memory" if MMU
 280	depends on !ARM_PATCH_PHYS_VIRT
 281	default DRAM_BASE if !MMU
 282	default 0x00000000 if ARCH_EBSA110 || \
 283			ARCH_FOOTBRIDGE || \
 284			ARCH_INTEGRATOR || \
 285			ARCH_IOP13XX || \
 286			ARCH_KS8695 || \
 287			ARCH_REALVIEW
 288	default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 289	default 0x20000000 if ARCH_S5PV210
 290	default 0xc0000000 if ARCH_SA1100
 291	help
 292	  Please provide the physical address corresponding to the
 293	  location of main memory in your system.
 294
 295config GENERIC_BUG
 296	def_bool y
 297	depends on BUG
 298
 299config PGTABLE_LEVELS
 300	int
 301	default 3 if ARM_LPAE
 302	default 2
 303
 304source "init/Kconfig"
 305
 306source "kernel/Kconfig.freezer"
 307
 308menu "System Type"
 309
 310config MMU
 311	bool "MMU-based Paged Memory Management Support"
 312	default y
 313	help
 314	  Select if you want MMU-based virtualised addressing space
 315	  support by paged memory management. If unsure, say 'Y'.
 316
 317config ARCH_MMAP_RND_BITS_MIN
 318	default 8
 319
 320config ARCH_MMAP_RND_BITS_MAX
 321	default 14 if PAGE_OFFSET=0x40000000
 322	default 15 if PAGE_OFFSET=0x80000000
 323	default 16
 324
 325#
 326# The "ARM system type" choice list is ordered alphabetically by option
 327# text.  Please add new entries in the option alphabetic order.
 328#
 329choice
 330	prompt "ARM system type"
 331	default ARM_SINGLE_ARMV7M if !MMU
 332	default ARCH_MULTIPLATFORM if MMU
 333
 334config ARCH_MULTIPLATFORM
 335	bool "Allow multiple platforms to be selected"
 336	depends on MMU
 
 337	select ARM_HAS_SG_CHAIN
 338	select ARM_PATCH_PHYS_VIRT
 339	select AUTO_ZRELADDR
 340	select TIMER_OF
 341	select COMMON_CLK
 342	select GENERIC_CLOCKEVENTS
 343	select MIGHT_HAVE_PCI
 344	select MULTI_IRQ_HANDLER
 345	select PCI_DOMAINS if PCI
 346	select SPARSE_IRQ
 347	select USE_OF
 348
 349config ARM_SINGLE_ARMV7M
 350	bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
 351	depends on !MMU
 352	select ARM_NVIC
 
 353	select AUTO_ZRELADDR
 354	select TIMER_OF
 355	select COMMON_CLK
 356	select CPU_V7M
 357	select GENERIC_CLOCKEVENTS
 358	select NO_IOPORT_MAP
 
 
 
 
 359	select SPARSE_IRQ
 360	select USE_OF
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 361
 362config ARCH_EBSA110
 363	bool "EBSA-110"
 364	select ARCH_USES_GETTIMEOFFSET
 365	select CPU_SA110
 366	select ISA
 367	select NEED_MACH_IO_H
 368	select NEED_MACH_MEMORY_H
 369	select NO_IOPORT_MAP
 370	help
 371	  This is an evaluation board for the StrongARM processor available
 372	  from Digital. It has limited hardware on-board, including an
 373	  Ethernet interface, two PCMCIA sockets, two serial ports and a
 374	  parallel port.
 375
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 376config ARCH_EP93XX
 377	bool "EP93xx-based"
 378	select ARCH_SPARSEMEM_ENABLE
 
 
 379	select ARM_AMBA
 380	imply ARM_PATCH_PHYS_VIRT
 381	select ARM_VIC
 382	select AUTO_ZRELADDR
 383	select CLKDEV_LOOKUP
 384	select CLKSRC_MMIO
 385	select CPU_ARM920T
 386	select GENERIC_CLOCKEVENTS
 387	select GPIOLIB
 388	help
 389	  This enables support for the Cirrus EP93xx series of CPUs.
 390
 391config ARCH_FOOTBRIDGE
 392	bool "FootBridge"
 393	select CPU_SA110
 394	select FOOTBRIDGE
 395	select GENERIC_CLOCKEVENTS
 396	select HAVE_IDE
 397	select NEED_MACH_IO_H if !MMU
 398	select NEED_MACH_MEMORY_H
 399	help
 400	  Support for systems based on the DC21285 companion chip
 401	  ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 402
 403config ARCH_NETX
 404	bool "Hilscher NetX based"
 405	select ARM_VIC
 406	select CLKSRC_MMIO
 407	select CPU_ARM926T
 408	select GENERIC_CLOCKEVENTS
 409	help
 410	  This enables support for systems based on the Hilscher NetX Soc
 411
 412config ARCH_IOP13XX
 413	bool "IOP13xx-based"
 414	depends on MMU
 415	select CPU_XSC3
 416	select NEED_MACH_MEMORY_H
 417	select NEED_RET_TO_USER
 418	select PCI
 419	select PLAT_IOP
 420	select VMSPLIT_1G
 421	select SPARSE_IRQ
 422	help
 423	  Support for Intel's IOP13XX (XScale) family of processors.
 424
 425config ARCH_IOP32X
 426	bool "IOP32x-based"
 427	depends on MMU
 
 428	select CPU_XSCALE
 429	select GPIO_IOP
 430	select GPIOLIB
 431	select NEED_RET_TO_USER
 432	select PCI
 433	select PLAT_IOP
 434	help
 435	  Support for Intel's 80219 and IOP32X (XScale) family of
 436	  processors.
 437
 438config ARCH_IOP33X
 439	bool "IOP33x-based"
 440	depends on MMU
 
 441	select CPU_XSCALE
 442	select GPIO_IOP
 443	select GPIOLIB
 444	select NEED_RET_TO_USER
 445	select PCI
 446	select PLAT_IOP
 447	help
 448	  Support for Intel's IOP33X (XScale) family of processors.
 449
 450config ARCH_IXP4XX
 451	bool "IXP4xx-based"
 452	depends on MMU
 453	select ARCH_HAS_DMA_SET_COHERENT_MASK
 
 454	select ARCH_SUPPORTS_BIG_ENDIAN
 455	select CLKSRC_MMIO
 456	select CPU_XSCALE
 457	select DMABOUNCE if PCI
 458	select GENERIC_CLOCKEVENTS
 459	select GPIOLIB
 460	select MIGHT_HAVE_PCI
 461	select NEED_MACH_IO_H
 462	select USB_EHCI_BIG_ENDIAN_DESC
 463	select USB_EHCI_BIG_ENDIAN_MMIO
 464	help
 465	  Support for Intel's IXP4XX (XScale) family of processors.
 466
 467config ARCH_DOVE
 468	bool "Marvell Dove"
 
 469	select CPU_PJ4
 470	select GENERIC_CLOCKEVENTS
 471	select GPIOLIB
 472	select MIGHT_HAVE_PCI
 473	select MULTI_IRQ_HANDLER
 474	select MVEBU_MBUS
 475	select PINCTRL
 476	select PINCTRL_DOVE
 477	select PLAT_ORION_LEGACY
 478	select SPARSE_IRQ
 479	select PM_GENERIC_DOMAINS if PM
 480	help
 481	  Support for the Marvell Dove SoC 88AP510
 482
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 483config ARCH_KS8695
 484	bool "Micrel/Kendin KS8695"
 
 485	select CLKSRC_MMIO
 486	select CPU_ARM922T
 487	select GENERIC_CLOCKEVENTS
 488	select GPIOLIB
 489	select NEED_MACH_MEMORY_H
 490	help
 491	  Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 492	  System-on-Chip devices.
 493
 494config ARCH_W90X900
 495	bool "Nuvoton W90X900 CPU"
 
 496	select CLKDEV_LOOKUP
 497	select CLKSRC_MMIO
 498	select CPU_ARM926T
 499	select GENERIC_CLOCKEVENTS
 500	select GPIOLIB
 501	help
 502	  Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 503	  At present, the w90x900 has been renamed nuc900, regarding
 504	  the ARM series product line, you can login the following
 505	  link address to know more.
 506
 507	  <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 508		ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 509
 510config ARCH_LPC32XX
 511	bool "NXP LPC32XX"
 
 512	select ARM_AMBA
 513	select CLKDEV_LOOKUP
 514	select CLKSRC_LPC32XX
 515	select COMMON_CLK
 516	select CPU_ARM926T
 517	select GENERIC_CLOCKEVENTS
 518	select GPIOLIB
 519	select MULTI_IRQ_HANDLER
 520	select SPARSE_IRQ
 521	select USE_OF
 522	help
 523	  Support for the NXP LPC32XX family of processors
 524
 525config ARCH_PXA
 526	bool "PXA2xx/PXA3xx-based"
 527	depends on MMU
 
 528	select ARCH_MTD_XIP
 
 529	select ARM_CPU_SUSPEND if PM
 530	select AUTO_ZRELADDR
 531	select COMMON_CLK
 532	select CLKDEV_LOOKUP
 533	select CLKSRC_PXA
 534	select CLKSRC_MMIO
 535	select TIMER_OF
 536	select CPU_XSCALE if !CPU_XSC3
 537	select GENERIC_CLOCKEVENTS
 538	select GPIO_PXA
 539	select GPIOLIB
 540	select HAVE_IDE
 541	select IRQ_DOMAIN
 542	select MULTI_IRQ_HANDLER
 543	select PLAT_PXA
 544	select SPARSE_IRQ
 545	help
 546	  Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 547
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 548config ARCH_RPC
 549	bool "RiscPC"
 550	depends on MMU
 551	select ARCH_ACORN
 552	select ARCH_MAY_HAVE_PC_FDC
 553	select ARCH_SPARSEMEM_ENABLE
 554	select ARCH_USES_GETTIMEOFFSET
 555	select CPU_SA110
 556	select FIQ
 557	select HAVE_IDE
 558	select HAVE_PATA_PLATFORM
 559	select ISA_DMA_API
 560	select NEED_MACH_IO_H
 561	select NEED_MACH_MEMORY_H
 562	select NO_IOPORT_MAP
 
 563	help
 564	  On the Acorn Risc-PC, Linux can support the internal IDE disk and
 565	  CD-ROM interface, serial and parallel port, and the floppy drive.
 566
 567config ARCH_SA1100
 568	bool "SA1100-based"
 
 569	select ARCH_MTD_XIP
 
 570	select ARCH_SPARSEMEM_ENABLE
 571	select CLKDEV_LOOKUP
 572	select CLKSRC_MMIO
 573	select CLKSRC_PXA
 574	select TIMER_OF if OF
 575	select CPU_FREQ
 576	select CPU_SA1100
 577	select GENERIC_CLOCKEVENTS
 578	select GPIOLIB
 579	select HAVE_IDE
 580	select IRQ_DOMAIN
 581	select ISA
 582	select MULTI_IRQ_HANDLER
 583	select NEED_MACH_MEMORY_H
 584	select SPARSE_IRQ
 585	help
 586	  Support for StrongARM 11x0 based boards.
 587
 588config ARCH_S3C24XX
 589	bool "Samsung S3C24XX SoCs"
 
 
 590	select ATAGS
 591	select CLKDEV_LOOKUP
 592	select CLKSRC_SAMSUNG_PWM
 593	select GENERIC_CLOCKEVENTS
 594	select GPIO_SAMSUNG
 595	select GPIOLIB
 596	select HAVE_S3C2410_I2C if I2C
 597	select HAVE_S3C2410_WATCHDOG if WATCHDOG
 598	select HAVE_S3C_RTC if RTC_CLASS
 599	select MULTI_IRQ_HANDLER
 600	select NEED_MACH_IO_H
 601	select SAMSUNG_ATAGS
 602	select USE_OF
 603	help
 604	  Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 605	  and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 606	  (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 607	  Samsung SMDK2410 development board (and derivatives).
 608
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 609config ARCH_DAVINCI
 610	bool "TI DaVinci"
 611	select ARCH_HAS_HOLES_MEMORYMODEL
 
 612	select CLKDEV_LOOKUP
 613	select CPU_ARM926T
 614	select GENERIC_ALLOCATOR
 615	select GENERIC_CLOCKEVENTS
 616	select GENERIC_IRQ_CHIP
 617	select GPIOLIB
 618	select HAVE_IDE
 
 619	select USE_OF
 620	select ZONE_DMA
 621	help
 622	  Support for TI's DaVinci platform.
 623
 624config ARCH_OMAP1
 625	bool "TI OMAP1"
 626	depends on MMU
 
 627	select ARCH_HAS_HOLES_MEMORYMODEL
 628	select ARCH_OMAP
 
 629	select CLKDEV_LOOKUP
 630	select CLKSRC_MMIO
 631	select GENERIC_CLOCKEVENTS
 632	select GENERIC_IRQ_CHIP
 633	select GPIOLIB
 634	select HAVE_IDE
 635	select IRQ_DOMAIN
 636	select MULTI_IRQ_HANDLER
 637	select NEED_MACH_IO_H if PCCARD
 638	select NEED_MACH_MEMORY_H
 639	select SPARSE_IRQ
 640	help
 641	  Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 642
 643endchoice
 644
 645menu "Multiple platform selection"
 646	depends on ARCH_MULTIPLATFORM
 647
 648comment "CPU Core family selection"
 649
 650config ARCH_MULTI_V4
 651	bool "ARMv4 based platforms (FA526)"
 652	depends on !ARCH_MULTI_V6_V7
 653	select ARCH_MULTI_V4_V5
 654	select CPU_FA526
 655
 656config ARCH_MULTI_V4T
 657	bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 658	depends on !ARCH_MULTI_V6_V7
 659	select ARCH_MULTI_V4_V5
 660	select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 661		CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 662		CPU_ARM925T || CPU_ARM940T)
 663
 664config ARCH_MULTI_V5
 665	bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 666	depends on !ARCH_MULTI_V6_V7
 667	select ARCH_MULTI_V4_V5
 668	select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 669		CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 670		CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 671
 672config ARCH_MULTI_V4_V5
 673	bool
 674
 675config ARCH_MULTI_V6
 676	bool "ARMv6 based platforms (ARM11)"
 677	select ARCH_MULTI_V6_V7
 678	select CPU_V6K
 679
 680config ARCH_MULTI_V7
 681	bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 682	default y
 683	select ARCH_MULTI_V6_V7
 684	select CPU_V7
 685	select HAVE_SMP
 686
 687config ARCH_MULTI_V6_V7
 688	bool
 689	select MIGHT_HAVE_CACHE_L2X0
 690
 691config ARCH_MULTI_CPU_AUTO
 692	def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 693	select ARCH_MULTI_V5
 694
 695endmenu
 696
 697config ARCH_VIRT
 698	bool "Dummy Virtual Machine"
 699	depends on ARCH_MULTI_V7
 700	select ARM_AMBA
 701	select ARM_GIC
 702	select ARM_GIC_V2M if PCI
 703	select ARM_GIC_V3
 704	select ARM_GIC_V3_ITS if PCI
 705	select ARM_PSCI
 706	select HAVE_ARM_ARCH_TIMER
 707
 708#
 709# This is sorted alphabetically by mach-* pathname.  However, plat-*
 710# Kconfigs may be included either alphabetically (according to the
 711# plat- suffix) or along side the corresponding mach-* source.
 712#
 713source "arch/arm/mach-actions/Kconfig"
 714
 715source "arch/arm/mach-alpine/Kconfig"
 716
 717source "arch/arm/mach-artpec/Kconfig"
 718
 719source "arch/arm/mach-asm9260/Kconfig"
 720
 721source "arch/arm/mach-aspeed/Kconfig"
 722
 723source "arch/arm/mach-at91/Kconfig"
 724
 725source "arch/arm/mach-axxia/Kconfig"
 726
 727source "arch/arm/mach-bcm/Kconfig"
 728
 729source "arch/arm/mach-berlin/Kconfig"
 730
 731source "arch/arm/mach-clps711x/Kconfig"
 732
 733source "arch/arm/mach-cns3xxx/Kconfig"
 734
 735source "arch/arm/mach-davinci/Kconfig"
 736
 737source "arch/arm/mach-digicolor/Kconfig"
 738
 739source "arch/arm/mach-dove/Kconfig"
 740
 741source "arch/arm/mach-ep93xx/Kconfig"
 742
 743source "arch/arm/mach-exynos/Kconfig"
 744source "arch/arm/plat-samsung/Kconfig"
 745
 746source "arch/arm/mach-footbridge/Kconfig"
 747
 748source "arch/arm/mach-gemini/Kconfig"
 749
 750source "arch/arm/mach-highbank/Kconfig"
 751
 752source "arch/arm/mach-hisi/Kconfig"
 753
 754source "arch/arm/mach-imx/Kconfig"
 755
 756source "arch/arm/mach-integrator/Kconfig"
 757
 758source "arch/arm/mach-iop13xx/Kconfig"
 759
 760source "arch/arm/mach-iop32x/Kconfig"
 761
 762source "arch/arm/mach-iop33x/Kconfig"
 763
 
 
 764source "arch/arm/mach-ixp4xx/Kconfig"
 765
 766source "arch/arm/mach-keystone/Kconfig"
 767
 768source "arch/arm/mach-ks8695/Kconfig"
 769
 770source "arch/arm/mach-mediatek/Kconfig"
 771
 772source "arch/arm/mach-meson/Kconfig"
 773
 774source "arch/arm/mach-mmp/Kconfig"
 775
 776source "arch/arm/mach-moxart/Kconfig"
 777
 778source "arch/arm/mach-mv78xx0/Kconfig"
 779
 780source "arch/arm/mach-mvebu/Kconfig"
 781
 782source "arch/arm/mach-mxs/Kconfig"
 783
 784source "arch/arm/mach-netx/Kconfig"
 785
 786source "arch/arm/mach-nomadik/Kconfig"
 787
 788source "arch/arm/mach-npcm/Kconfig"
 789
 790source "arch/arm/mach-nspire/Kconfig"
 791
 792source "arch/arm/plat-omap/Kconfig"
 793
 794source "arch/arm/mach-omap1/Kconfig"
 795
 796source "arch/arm/mach-omap2/Kconfig"
 797
 798source "arch/arm/mach-orion5x/Kconfig"
 799
 800source "arch/arm/mach-oxnas/Kconfig"
 801
 802source "arch/arm/mach-picoxcell/Kconfig"
 803
 804source "arch/arm/mach-prima2/Kconfig"
 805
 806source "arch/arm/mach-pxa/Kconfig"
 807source "arch/arm/plat-pxa/Kconfig"
 808
 
 
 809source "arch/arm/mach-qcom/Kconfig"
 810
 811source "arch/arm/mach-realview/Kconfig"
 812
 813source "arch/arm/mach-rockchip/Kconfig"
 814
 815source "arch/arm/mach-s3c24xx/Kconfig"
 816
 817source "arch/arm/mach-s3c64xx/Kconfig"
 818
 819source "arch/arm/mach-s5pv210/Kconfig"
 820
 821source "arch/arm/mach-sa1100/Kconfig"
 822
 823source "arch/arm/mach-shmobile/Kconfig"
 824
 825source "arch/arm/mach-socfpga/Kconfig"
 826
 827source "arch/arm/mach-spear/Kconfig"
 828
 829source "arch/arm/mach-sti/Kconfig"
 830
 831source "arch/arm/mach-stm32/Kconfig"
 
 
 
 
 
 
 
 
 
 
 
 
 832
 833source "arch/arm/mach-sunxi/Kconfig"
 834
 835source "arch/arm/mach-tango/Kconfig"
 836
 837source "arch/arm/mach-tegra/Kconfig"
 838
 839source "arch/arm/mach-u300/Kconfig"
 840
 841source "arch/arm/mach-uniphier/Kconfig"
 842
 843source "arch/arm/mach-ux500/Kconfig"
 844
 845source "arch/arm/mach-versatile/Kconfig"
 846
 847source "arch/arm/mach-vexpress/Kconfig"
 848source "arch/arm/plat-versatile/Kconfig"
 849
 850source "arch/arm/mach-vt8500/Kconfig"
 851
 852source "arch/arm/mach-w90x900/Kconfig"
 853
 854source "arch/arm/mach-zx/Kconfig"
 855
 856source "arch/arm/mach-zynq/Kconfig"
 857
 858# ARMv7-M architecture
 859config ARCH_EFM32
 860	bool "Energy Micro efm32"
 861	depends on ARM_SINGLE_ARMV7M
 862	select GPIOLIB
 863	help
 864	  Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 865	  processors.
 866
 867config ARCH_LPC18XX
 868	bool "NXP LPC18xx/LPC43xx"
 869	depends on ARM_SINGLE_ARMV7M
 870	select ARCH_HAS_RESET_CONTROLLER
 871	select ARM_AMBA
 872	select CLKSRC_LPC32XX
 873	select PINCTRL
 874	help
 875	  Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
 876	  high performance microcontrollers.
 877
 878config ARCH_MPS2
 879	bool "ARM MPS2 platform"
 880	depends on ARM_SINGLE_ARMV7M
 881	select ARM_AMBA
 882	select CLKSRC_MPS2
 883	help
 884	  Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
 885	  with a range of available cores like Cortex-M3/M4/M7.
 886
 887	  Please, note that depends which Application Note is used memory map
 888	  for the platform may vary, so adjustment of RAM base might be needed.
 889
 890# Definitions to make life easier
 891config ARCH_ACORN
 892	bool
 893
 894config PLAT_IOP
 895	bool
 896	select GENERIC_CLOCKEVENTS
 897
 898config PLAT_ORION
 899	bool
 900	select CLKSRC_MMIO
 901	select COMMON_CLK
 902	select GENERIC_IRQ_CHIP
 903	select IRQ_DOMAIN
 904
 905config PLAT_ORION_LEGACY
 906	bool
 907	select PLAT_ORION
 908
 909config PLAT_PXA
 910	bool
 911
 912config PLAT_VERSATILE
 913	bool
 914
 
 
 
 
 
 915source "arch/arm/firmware/Kconfig"
 916
 917source arch/arm/mm/Kconfig
 918
 
 
 
 
 
 919config IWMMXT
 920	bool "Enable iWMMXt support"
 921	depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
 922	default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
 923	help
 924	  Enable support for iWMMXt context switching at run time if
 925	  running on a CPU that supports it.
 926
 927config MULTI_IRQ_HANDLER
 928	bool
 929	help
 930	  Allow each machine to specify it's own IRQ handler at run time.
 931
 932if !MMU
 933source "arch/arm/Kconfig-nommu"
 934endif
 935
 936config PJ4B_ERRATA_4742
 937	bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
 938	depends on CPU_PJ4B && MACH_ARMADA_370
 939	default y
 940	help
 941	  When coming out of either a Wait for Interrupt (WFI) or a Wait for
 942	  Event (WFE) IDLE states, a specific timing sensitivity exists between
 943	  the retiring WFI/WFE instructions and the newly issued subsequent
 944	  instructions.  This sensitivity can result in a CPU hang scenario.
 945	  Workaround:
 946	  The software must insert either a Data Synchronization Barrier (DSB)
 947	  or Data Memory Barrier (DMB) command immediately after the WFI/WFE
 948	  instruction
 949
 950config ARM_ERRATA_326103
 951	bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
 952	depends on CPU_V6
 953	help
 954	  Executing a SWP instruction to read-only memory does not set bit 11
 955	  of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
 956	  treat the access as a read, preventing a COW from occurring and
 957	  causing the faulting task to livelock.
 958
 959config ARM_ERRATA_411920
 960	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
 961	depends on CPU_V6 || CPU_V6K
 962	help
 963	  Invalidation of the Instruction Cache operation can
 964	  fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
 965	  It does not affect the MPCore. This option enables the ARM Ltd.
 966	  recommended workaround.
 967
 968config ARM_ERRATA_430973
 969	bool "ARM errata: Stale prediction on replaced interworking branch"
 970	depends on CPU_V7
 971	help
 972	  This option enables the workaround for the 430973 Cortex-A8
 973	  r1p* erratum. If a code sequence containing an ARM/Thumb
 974	  interworking branch is replaced with another code sequence at the
 975	  same virtual address, whether due to self-modifying code or virtual
 976	  to physical address re-mapping, Cortex-A8 does not recover from the
 977	  stale interworking branch prediction. This results in Cortex-A8
 978	  executing the new code sequence in the incorrect ARM or Thumb state.
 979	  The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
 980	  and also flushes the branch target cache at every context switch.
 981	  Note that setting specific bits in the ACTLR register may not be
 982	  available in non-secure mode.
 983
 984config ARM_ERRATA_458693
 985	bool "ARM errata: Processor deadlock when a false hazard is created"
 986	depends on CPU_V7
 987	depends on !ARCH_MULTIPLATFORM
 988	help
 989	  This option enables the workaround for the 458693 Cortex-A8 (r2p0)
 990	  erratum. For very specific sequences of memory operations, it is
 991	  possible for a hazard condition intended for a cache line to instead
 992	  be incorrectly associated with a different cache line. This false
 993	  hazard might then cause a processor deadlock. The workaround enables
 994	  the L1 caching of the NEON accesses and disables the PLD instruction
 995	  in the ACTLR register. Note that setting specific bits in the ACTLR
 996	  register may not be available in non-secure mode.
 997
 998config ARM_ERRATA_460075
 999	bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1000	depends on CPU_V7
1001	depends on !ARCH_MULTIPLATFORM
1002	help
1003	  This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1004	  erratum. Any asynchronous access to the L2 cache may encounter a
1005	  situation in which recent store transactions to the L2 cache are lost
1006	  and overwritten with stale memory contents from external memory. The
1007	  workaround disables the write-allocate mode for the L2 cache via the
1008	  ACTLR register. Note that setting specific bits in the ACTLR register
1009	  may not be available in non-secure mode.
1010
1011config ARM_ERRATA_742230
1012	bool "ARM errata: DMB operation may be faulty"
1013	depends on CPU_V7 && SMP
1014	depends on !ARCH_MULTIPLATFORM
1015	help
1016	  This option enables the workaround for the 742230 Cortex-A9
1017	  (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1018	  between two write operations may not ensure the correct visibility
1019	  ordering of the two writes. This workaround sets a specific bit in
1020	  the diagnostic register of the Cortex-A9 which causes the DMB
1021	  instruction to behave as a DSB, ensuring the correct behaviour of
1022	  the two writes.
1023
1024config ARM_ERRATA_742231
1025	bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1026	depends on CPU_V7 && SMP
1027	depends on !ARCH_MULTIPLATFORM
1028	help
1029	  This option enables the workaround for the 742231 Cortex-A9
1030	  (r2p0..r2p2) erratum. Under certain conditions, specific to the
1031	  Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1032	  accessing some data located in the same cache line, may get corrupted
1033	  data due to bad handling of the address hazard when the line gets
1034	  replaced from one of the CPUs at the same time as another CPU is
1035	  accessing it. This workaround sets specific bits in the diagnostic
1036	  register of the Cortex-A9 which reduces the linefill issuing
1037	  capabilities of the processor.
1038
 
 
 
 
 
 
 
 
 
 
 
 
 
1039config ARM_ERRATA_643719
1040	bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1041	depends on CPU_V7 && SMP
1042	default y
1043	help
1044	  This option enables the workaround for the 643719 Cortex-A9 (prior to
1045	  r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1046	  register returns zero when it should return one. The workaround
1047	  corrects this value, ensuring cache maintenance operations which use
1048	  it behave as intended and avoiding data corruption.
1049
1050config ARM_ERRATA_720789
1051	bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1052	depends on CPU_V7
1053	help
1054	  This option enables the workaround for the 720789 Cortex-A9 (prior to
1055	  r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1056	  broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1057	  As a consequence of this erratum, some TLB entries which should be
1058	  invalidated are not, resulting in an incoherency in the system page
1059	  tables. The workaround changes the TLB flushing routines to invalidate
1060	  entries regardless of the ASID.
1061
 
 
 
 
 
 
 
 
 
 
 
1062config ARM_ERRATA_743622
1063	bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1064	depends on CPU_V7
1065	depends on !ARCH_MULTIPLATFORM
1066	help
1067	  This option enables the workaround for the 743622 Cortex-A9
1068	  (r2p*) erratum. Under very rare conditions, a faulty
1069	  optimisation in the Cortex-A9 Store Buffer may lead to data
1070	  corruption. This workaround sets a specific bit in the diagnostic
1071	  register of the Cortex-A9 which disables the Store Buffer
1072	  optimisation, preventing the defect from occurring. This has no
1073	  visible impact on the overall performance or power consumption of the
1074	  processor.
1075
1076config ARM_ERRATA_751472
1077	bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1078	depends on CPU_V7
1079	depends on !ARCH_MULTIPLATFORM
1080	help
1081	  This option enables the workaround for the 751472 Cortex-A9 (prior
1082	  to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1083	  completion of a following broadcasted operation if the second
1084	  operation is received by a CPU before the ICIALLUIS has completed,
1085	  potentially leading to corrupted entries in the cache or TLB.
1086
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1087config ARM_ERRATA_754322
1088	bool "ARM errata: possible faulty MMU translations following an ASID switch"
1089	depends on CPU_V7
1090	help
1091	  This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1092	  r3p*) erratum. A speculative memory access may cause a page table walk
1093	  which starts prior to an ASID switch but completes afterwards. This
1094	  can populate the micro-TLB with a stale entry which may be hit with
1095	  the new ASID. This workaround places two dsb instructions in the mm
1096	  switching code so that no page table walks can cross the ASID switch.
1097
1098config ARM_ERRATA_754327
1099	bool "ARM errata: no automatic Store Buffer drain"
1100	depends on CPU_V7 && SMP
1101	help
1102	  This option enables the workaround for the 754327 Cortex-A9 (prior to
1103	  r2p0) erratum. The Store Buffer does not have any automatic draining
1104	  mechanism and therefore a livelock may occur if an external agent
1105	  continuously polls a memory location waiting to observe an update.
1106	  This workaround defines cpu_relax() as smp_mb(), preventing correctly
1107	  written polling loops from denying visibility of updates to memory.
1108
1109config ARM_ERRATA_364296
1110	bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1111	depends on CPU_V6
1112	help
1113	  This options enables the workaround for the 364296 ARM1136
1114	  r0p2 erratum (possible cache data corruption with
1115	  hit-under-miss enabled). It sets the undocumented bit 31 in
1116	  the auxiliary control register and the FI bit in the control
1117	  register, thus disabling hit-under-miss without putting the
1118	  processor into full low interrupt latency mode. ARM11MPCore
1119	  is not affected.
1120
1121config ARM_ERRATA_764369
1122	bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1123	depends on CPU_V7 && SMP
1124	help
1125	  This option enables the workaround for erratum 764369
1126	  affecting Cortex-A9 MPCore with two or more processors (all
1127	  current revisions). Under certain timing circumstances, a data
1128	  cache line maintenance operation by MVA targeting an Inner
1129	  Shareable memory region may fail to proceed up to either the
1130	  Point of Coherency or to the Point of Unification of the
1131	  system. This workaround adds a DSB instruction before the
1132	  relevant cache maintenance functions and sets a specific bit
1133	  in the diagnostic control register of the SCU.
1134
 
 
 
 
 
 
 
 
 
 
 
 
1135config ARM_ERRATA_775420
1136       bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1137       depends on CPU_V7
1138       help
1139	 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1140	 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1141	 operation aborts with MMU exception, it might cause the processor
1142	 to deadlock. This workaround puts DSB before executing ISB if
1143	 an abort may occur on cache maintenance.
1144
1145config ARM_ERRATA_798181
1146	bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1147	depends on CPU_V7 && SMP
1148	help
1149	  On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1150	  adequately shooting down all use of the old entries. This
1151	  option enables the Linux kernel workaround for this erratum
1152	  which sends an IPI to the CPUs that are running the same ASID
1153	  as the one being invalidated.
1154
1155config ARM_ERRATA_773022
1156	bool "ARM errata: incorrect instructions may be executed from loop buffer"
1157	depends on CPU_V7
1158	help
1159	  This option enables the workaround for the 773022 Cortex-A15
1160	  (up to r0p4) erratum. In certain rare sequences of code, the
1161	  loop buffer may deliver incorrect instructions. This
1162	  workaround disables the loop buffer to avoid the erratum.
1163
1164config ARM_ERRATA_818325_852422
1165	bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1166	depends on CPU_V7
1167	help
1168	  This option enables the workaround for:
1169	  - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1170	    instruction might deadlock.  Fixed in r0p1.
1171	  - Cortex-A12 852422: Execution of a sequence of instructions might
1172	    lead to either a data corruption or a CPU deadlock.  Not fixed in
1173	    any Cortex-A12 cores yet.
1174	  This workaround for all both errata involves setting bit[12] of the
1175	  Feature Register. This bit disables an optimisation applied to a
1176	  sequence of 2 instructions that use opposing condition codes.
1177
1178config ARM_ERRATA_821420
1179	bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1180	depends on CPU_V7
1181	help
1182	  This option enables the workaround for the 821420 Cortex-A12
1183	  (all revs) erratum. In very rare timing conditions, a sequence
1184	  of VMOV to Core registers instructions, for which the second
1185	  one is in the shadow of a branch or abort, can lead to a
1186	  deadlock when the VMOV instructions are issued out-of-order.
1187
1188config ARM_ERRATA_825619
1189	bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1190	depends on CPU_V7
1191	help
1192	  This option enables the workaround for the 825619 Cortex-A12
1193	  (all revs) erratum. Within rare timing constraints, executing a
1194	  DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1195	  and Device/Strongly-Ordered loads and stores might cause deadlock
1196
1197config ARM_ERRATA_852421
1198	bool "ARM errata: A17: DMB ST might fail to create order between stores"
1199	depends on CPU_V7
1200	help
1201	  This option enables the workaround for the 852421 Cortex-A17
1202	  (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1203	  execution of a DMB ST instruction might fail to properly order
1204	  stores from GroupA and stores from GroupB.
1205
1206config ARM_ERRATA_852423
1207	bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1208	depends on CPU_V7
1209	help
1210	  This option enables the workaround for:
1211	  - Cortex-A17 852423: Execution of a sequence of instructions might
1212	    lead to either a data corruption or a CPU deadlock.  Not fixed in
1213	    any Cortex-A17 cores yet.
1214	  This is identical to Cortex-A12 erratum 852422.  It is a separate
1215	  config option from the A12 erratum due to the way errata are checked
1216	  for and handled.
1217
1218endmenu
1219
1220source "arch/arm/common/Kconfig"
1221
1222menu "Bus support"
1223
 
 
 
1224config ISA
1225	bool
1226	help
1227	  Find out whether you have ISA slots on your motherboard.  ISA is the
1228	  name of a bus system, i.e. the way the CPU talks to the other stuff
1229	  inside your box.  Other bus systems are PCI, EISA, MicroChannel
1230	  (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1231	  newer boards don't support it.  If you have ISA, say Y, otherwise N.
1232
1233# Select ISA DMA controller support
1234config ISA_DMA
1235	bool
1236	select ISA_DMA_API
1237
1238# Select ISA DMA interface
1239config ISA_DMA_API
1240	bool
1241
1242config PCI
1243	bool "PCI support" if MIGHT_HAVE_PCI
1244	help
1245	  Find out whether you have a PCI motherboard. PCI is the name of a
1246	  bus system, i.e. the way the CPU talks to the other stuff inside
1247	  your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1248	  VESA. If you have PCI, say Y, otherwise N.
1249
1250config PCI_DOMAINS
1251	bool
1252	depends on PCI
1253
1254config PCI_DOMAINS_GENERIC
1255	def_bool PCI_DOMAINS
1256
1257config PCI_NANOENGINE
1258	bool "BSE nanoEngine PCI support"
1259	depends on SA1100_NANOENGINE
1260	help
1261	  Enable PCI on the BSE nanoEngine board.
1262
1263config PCI_SYSCALL
1264	def_bool PCI
1265
1266config PCI_HOST_ITE8152
1267	bool
1268	depends on PCI && MACH_ARMCORE
1269	default y
1270	select DMABOUNCE
1271
1272source "drivers/pci/Kconfig"
 
1273
1274source "drivers/pcmcia/Kconfig"
1275
1276endmenu
1277
1278menu "Kernel Features"
1279
1280config HAVE_SMP
1281	bool
1282	help
1283	  This option should be selected by machines which have an SMP-
1284	  capable CPU.
1285
1286	  The only effect of this option is to make the SMP-related
1287	  options available to the user for configuration.
1288
1289config SMP
1290	bool "Symmetric Multi-Processing"
1291	depends on CPU_V6K || CPU_V7
1292	depends on GENERIC_CLOCKEVENTS
1293	depends on HAVE_SMP
1294	depends on MMU || ARM_MPU
1295	select IRQ_WORK
1296	help
1297	  This enables support for systems with more than one CPU. If you have
1298	  a system with only one CPU, say N. If you have a system with more
1299	  than one CPU, say Y.
1300
1301	  If you say N here, the kernel will run on uni- and multiprocessor
1302	  machines, but will use only one CPU of a multiprocessor machine. If
1303	  you say Y here, the kernel will run on many, but not all,
1304	  uniprocessor machines. On a uniprocessor machine, the kernel
1305	  will run faster if you say N here.
1306
1307	  See also <file:Documentation/x86/i386/IO-APIC.txt>,
1308	  <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1309	  <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1310
1311	  If you don't know what to do here, say N.
1312
1313config SMP_ON_UP
1314	bool "Allow booting SMP kernel on uniprocessor systems"
1315	depends on SMP && !XIP_KERNEL && MMU
1316	default y
1317	help
1318	  SMP kernels contain instructions which fail on non-SMP processors.
1319	  Enabling this option allows the kernel to modify itself to make
1320	  these instructions safe.  Disabling it allows about 1K of space
1321	  savings.
1322
1323	  If you don't know what to do here, say Y.
1324
1325config ARM_CPU_TOPOLOGY
1326	bool "Support cpu topology definition"
1327	depends on SMP && CPU_V7
1328	default y
1329	help
1330	  Support ARM cpu topology definition. The MPIDR register defines
1331	  affinity between processors which is then used to describe the cpu
1332	  topology of an ARM System.
1333
1334config SCHED_MC
1335	bool "Multi-core scheduler support"
1336	depends on ARM_CPU_TOPOLOGY
1337	help
1338	  Multi-core scheduler support improves the CPU scheduler's decision
1339	  making when dealing with multi-core CPU chips at a cost of slightly
1340	  increased overhead in some places. If unsure say N here.
1341
1342config SCHED_SMT
1343	bool "SMT scheduler support"
1344	depends on ARM_CPU_TOPOLOGY
1345	help
1346	  Improves the CPU scheduler's decision making when dealing with
1347	  MultiThreading at a cost of slightly increased overhead in some
1348	  places. If unsure say N here.
1349
1350config HAVE_ARM_SCU
1351	bool
1352	help
1353	  This option enables support for the ARM system coherency unit
1354
1355config HAVE_ARM_ARCH_TIMER
1356	bool "Architected timer support"
1357	depends on CPU_V7
1358	select ARM_ARCH_TIMER
1359	select GENERIC_CLOCKEVENTS
1360	help
1361	  This option enables support for the ARM architected timer
1362
1363config HAVE_ARM_TWD
1364	bool
1365	select TIMER_OF if OF
 
1366	help
1367	  This options enables support for the ARM timer and watchdog unit
1368
1369config MCPM
1370	bool "Multi-Cluster Power Management"
1371	depends on CPU_V7 && SMP
1372	help
1373	  This option provides the common power management infrastructure
1374	  for (multi-)cluster based systems, such as big.LITTLE based
1375	  systems.
1376
1377config MCPM_QUAD_CLUSTER
1378	bool
1379	depends on MCPM
1380	help
1381	  To avoid wasting resources unnecessarily, MCPM only supports up
1382	  to 2 clusters by default.
1383	  Platforms with 3 or 4 clusters that use MCPM must select this
1384	  option to allow the additional clusters to be managed.
1385
1386config BIG_LITTLE
1387	bool "big.LITTLE support (Experimental)"
1388	depends on CPU_V7 && SMP
1389	select MCPM
1390	help
1391	  This option enables support selections for the big.LITTLE
1392	  system architecture.
1393
1394config BL_SWITCHER
1395	bool "big.LITTLE switcher support"
1396	depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
 
1397	select CPU_PM
1398	help
1399	  The big.LITTLE "switcher" provides the core functionality to
1400	  transparently handle transition between a cluster of A15's
1401	  and a cluster of A7's in a big.LITTLE system.
1402
1403config BL_SWITCHER_DUMMY_IF
1404	tristate "Simple big.LITTLE switcher user interface"
1405	depends on BL_SWITCHER && DEBUG_KERNEL
1406	help
1407	  This is a simple and dummy char dev interface to control
1408	  the big.LITTLE switcher core code.  It is meant for
1409	  debugging purposes only.
1410
1411choice
1412	prompt "Memory split"
1413	depends on MMU
1414	default VMSPLIT_3G
1415	help
1416	  Select the desired split between kernel and user memory.
1417
1418	  If you are not absolutely sure what you are doing, leave this
1419	  option alone!
1420
1421	config VMSPLIT_3G
1422		bool "3G/1G user/kernel split"
1423	config VMSPLIT_3G_OPT
1424		depends on !ARM_LPAE
1425		bool "3G/1G user/kernel split (for full 1G low memory)"
1426	config VMSPLIT_2G
1427		bool "2G/2G user/kernel split"
1428	config VMSPLIT_1G
1429		bool "1G/3G user/kernel split"
1430endchoice
1431
1432config PAGE_OFFSET
1433	hex
1434	default PHYS_OFFSET if !MMU
1435	default 0x40000000 if VMSPLIT_1G
1436	default 0x80000000 if VMSPLIT_2G
1437	default 0xB0000000 if VMSPLIT_3G_OPT
1438	default 0xC0000000
1439
1440config NR_CPUS
1441	int "Maximum number of CPUs (2-32)"
1442	range 2 32
1443	depends on SMP
1444	default "4"
1445
1446config HOTPLUG_CPU
1447	bool "Support for hot-pluggable CPUs"
1448	depends on SMP
1449	help
1450	  Say Y here to experiment with turning CPUs off and on.  CPUs
1451	  can be controlled through /sys/devices/system/cpu.
1452
1453config ARM_PSCI
1454	bool "Support for the ARM Power State Coordination Interface (PSCI)"
1455	depends on HAVE_ARM_SMCCC
1456	select ARM_PSCI_FW
1457	help
1458	  Say Y here if you want Linux to communicate with system firmware
1459	  implementing the PSCI specification for CPU-centric power
1460	  management operations described in ARM document number ARM DEN
1461	  0022A ("Power State Coordination Interface System Software on
1462	  ARM processors").
1463
1464# The GPIO number here must be sorted by descending number. In case of
1465# a multiplatform kernel, we just want the highest value required by the
1466# selected platforms.
1467config ARCH_NR_GPIO
1468	int
1469	default 2048 if ARCH_SOCFPGA
1470	default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1471		ARCH_ZYNQ
1472	default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1473		SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1474	default 416 if ARCH_SUNXI
1475	default 392 if ARCH_U8500
1476	default 352 if ARCH_VT8500
1477	default 288 if ARCH_ROCKCHIP
1478	default 264 if MACH_H4700
1479	default 0
1480	help
1481	  Maximum number of GPIOs in the system.
1482
1483	  If unsure, leave the default value.
1484
1485source kernel/Kconfig.preempt
1486
1487config HZ_FIXED
1488	int
1489	default 200 if ARCH_EBSA110
1490	default 128 if SOC_AT91RM9200
 
 
1491	default 0
1492
1493choice
1494	depends on HZ_FIXED = 0
1495	prompt "Timer frequency"
1496
1497config HZ_100
1498	bool "100 Hz"
1499
1500config HZ_200
1501	bool "200 Hz"
1502
1503config HZ_250
1504	bool "250 Hz"
1505
1506config HZ_300
1507	bool "300 Hz"
1508
1509config HZ_500
1510	bool "500 Hz"
1511
1512config HZ_1000
1513	bool "1000 Hz"
1514
1515endchoice
1516
1517config HZ
1518	int
1519	default HZ_FIXED if HZ_FIXED != 0
1520	default 100 if HZ_100
1521	default 200 if HZ_200
1522	default 250 if HZ_250
1523	default 300 if HZ_300
1524	default 500 if HZ_500
1525	default 1000
1526
1527config SCHED_HRTICK
1528	def_bool HIGH_RES_TIMERS
1529
1530config THUMB2_KERNEL
1531	bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1532	depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1533	default y if CPU_THUMBONLY
 
 
1534	select ARM_UNWIND
1535	help
1536	  By enabling this option, the kernel will be compiled in
1537	  Thumb-2 mode.
 
1538
1539	  If unsure, say N.
1540
1541config THUMB2_AVOID_R_ARM_THM_JUMP11
1542	bool "Work around buggy Thumb-2 short branch relocations in gas"
1543	depends on THUMB2_KERNEL && MODULES
1544	default y
1545	help
1546	  Various binutils versions can resolve Thumb-2 branches to
1547	  locally-defined, preemptible global symbols as short-range "b.n"
1548	  branch instructions.
1549
1550	  This is a problem, because there's no guarantee the final
1551	  destination of the symbol, or any candidate locations for a
1552	  trampoline, are within range of the branch.  For this reason, the
1553	  kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1554	  relocation in modules at all, and it makes little sense to add
1555	  support.
1556
1557	  The symptom is that the kernel fails with an "unsupported
1558	  relocation" error when loading some modules.
1559
1560	  Until fixed tools are available, passing
1561	  -fno-optimize-sibling-calls to gcc should prevent gcc generating
1562	  code which hits this problem, at the cost of a bit of extra runtime
1563	  stack usage in some cases.
1564
1565	  The problem is described in more detail at:
1566	      https://bugs.launchpad.net/binutils-linaro/+bug/725126
1567
1568	  Only Thumb-2 kernels are affected.
1569
1570	  Unless you are sure your tools don't have this problem, say Y.
1571
1572config ARM_PATCH_IDIV
1573	bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1574	depends on CPU_32v7 && !XIP_KERNEL
1575	default y
1576	help
1577	  The ARM compiler inserts calls to __aeabi_idiv() and
1578	  __aeabi_uidiv() when it needs to perform division on signed
1579	  and unsigned integers. Some v7 CPUs have support for the sdiv
1580	  and udiv instructions that can be used to implement those
1581	  functions.
1582
1583	  Enabling this option allows the kernel to modify itself to
1584	  replace the first two instructions of these library functions
1585	  with the sdiv or udiv plus "bx lr" instructions when the CPU
1586	  it is running on supports them. Typically this will be faster
1587	  and less power intensive than running the original library
1588	  code to do integer division.
1589
1590config AEABI
1591	bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K
1592	default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K
1593	help
1594	  This option allows for the kernel to be compiled using the latest
1595	  ARM ABI (aka EABI).  This is only useful if you are using a user
1596	  space environment that is also compiled with EABI.
1597
1598	  Since there are major incompatibilities between the legacy ABI and
1599	  EABI, especially with regard to structure member alignment, this
1600	  option also changes the kernel syscall calling convention to
1601	  disambiguate both ABIs and allow for backward compatibility support
1602	  (selected with CONFIG_OABI_COMPAT).
1603
1604	  To use this you need GCC version 4.0.0 or later.
1605
1606config OABI_COMPAT
1607	bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1608	depends on AEABI && !THUMB2_KERNEL
1609	help
1610	  This option preserves the old syscall interface along with the
1611	  new (ARM EABI) one. It also provides a compatibility layer to
1612	  intercept syscalls that have structure arguments which layout
1613	  in memory differs between the legacy ABI and the new ARM EABI
1614	  (only for non "thumb" binaries). This option adds a tiny
1615	  overhead to all syscalls and produces a slightly larger kernel.
1616
1617	  The seccomp filter system will not be available when this is
1618	  selected, since there is no way yet to sensibly distinguish
1619	  between calling conventions during filtering.
1620
1621	  If you know you'll be using only pure EABI user space then you
1622	  can say N here. If this option is not selected and you attempt
1623	  to execute a legacy ABI binary then the result will be
1624	  UNPREDICTABLE (in fact it can be predicted that it won't work
1625	  at all). If in doubt say N.
1626
1627config ARCH_HAS_HOLES_MEMORYMODEL
1628	bool
1629
1630config ARCH_SPARSEMEM_ENABLE
1631	bool
1632
1633config ARCH_SPARSEMEM_DEFAULT
1634	def_bool ARCH_SPARSEMEM_ENABLE
1635
1636config ARCH_SELECT_MEMORY_MODEL
1637	def_bool ARCH_SPARSEMEM_ENABLE
1638
1639config HAVE_ARCH_PFN_VALID
1640	def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1641
1642config HAVE_GENERIC_GUP
1643	def_bool y
1644	depends on ARM_LPAE
1645
1646config HIGHMEM
1647	bool "High Memory Support"
1648	depends on MMU
1649	help
1650	  The address space of ARM processors is only 4 Gigabytes large
1651	  and it has to accommodate user address space, kernel address
1652	  space as well as some memory mapped IO. That means that, if you
1653	  have a large amount of physical memory and/or IO, not all of the
1654	  memory can be "permanently mapped" by the kernel. The physical
1655	  memory that is not permanently mapped is called "high memory".
1656
1657	  Depending on the selected kernel/user memory split, minimum
1658	  vmalloc space and actual amount of RAM, you may not need this
1659	  option which should result in a slightly faster kernel.
1660
1661	  If unsure, say n.
1662
1663config HIGHPTE
1664	bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1665	depends on HIGHMEM
1666	default y
1667	help
1668	  The VM uses one page of physical memory for each page table.
1669	  For systems with a lot of processes, this can use a lot of
1670	  precious low memory, eventually leading to low memory being
1671	  consumed by page tables.  Setting this option will allow
1672	  user-space 2nd level page tables to reside in high memory.
1673
1674config CPU_SW_DOMAIN_PAN
1675	bool "Enable use of CPU domains to implement privileged no-access"
1676	depends on MMU && !ARM_LPAE
1677	default y
1678	help
1679	  Increase kernel security by ensuring that normal kernel accesses
1680	  are unable to access userspace addresses.  This can help prevent
1681	  use-after-free bugs becoming an exploitable privilege escalation
1682	  by ensuring that magic values (such as LIST_POISON) will always
1683	  fault when dereferenced.
1684
1685	  CPUs with low-vector mappings use a best-efforts implementation.
1686	  Their lower 1MB needs to remain accessible for the vectors, but
1687	  the remainder of userspace will become appropriately inaccessible.
1688
1689config HW_PERF_EVENTS
1690	def_bool y
1691	depends on ARM_PMU
 
 
 
 
1692
1693config SYS_SUPPORTS_HUGETLBFS
1694       def_bool y
1695       depends on ARM_LPAE
1696
1697config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1698       def_bool y
1699       depends on ARM_LPAE
1700
1701config ARCH_WANT_GENERAL_HUGETLB
1702	def_bool y
1703
1704config ARM_MODULE_PLTS
1705	bool "Use PLTs to allow module memory to spill over into vmalloc area"
1706	depends on MODULES
1707	help
1708	  Allocate PLTs when loading modules so that jumps and calls whose
1709	  targets are too far away for their relative offsets to be encoded
1710	  in the instructions themselves can be bounced via veneers in the
1711	  module's PLT. This allows modules to be allocated in the generic
1712	  vmalloc area after the dedicated module memory area has been
1713	  exhausted. The modules will use slightly more memory, but after
1714	  rounding up to page size, the actual memory footprint is usually
1715	  the same.
1716
1717	  Say y if you are getting out of memory errors while loading modules
1718
1719source "mm/Kconfig"
1720
1721config FORCE_MAX_ZONEORDER
1722	int "Maximum zone order"
 
1723	default "12" if SOC_AM33XX
1724	default "9" if SA1111 || ARCH_EFM32
1725	default "11"
1726	help
1727	  The kernel memory allocator divides physically contiguous memory
1728	  blocks into "zones", where each zone is a power of two number of
1729	  pages.  This option selects the largest power of two that the kernel
1730	  keeps in the memory allocator.  If you need to allocate very large
1731	  blocks of physically contiguous memory, then you may need to
1732	  increase this value.
1733
1734	  This config option is actually maximum order plus one. For example,
1735	  a value of 11 means that the largest free memory block is 2^10 pages.
1736
1737config ALIGNMENT_TRAP
1738	bool
1739	depends on CPU_CP15_MMU
1740	default y if !ARCH_EBSA110
1741	select HAVE_PROC_CPU if PROC_FS
1742	help
1743	  ARM processors cannot fetch/store information which is not
1744	  naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1745	  address divisible by 4. On 32-bit ARM processors, these non-aligned
1746	  fetch/store instructions will be emulated in software if you say
1747	  here, which has a severe performance impact. This is necessary for
1748	  correct operation of some network protocols. With an IP-only
1749	  configuration it is safe to say N, otherwise say Y.
1750
1751config UACCESS_WITH_MEMCPY
1752	bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1753	depends on MMU
1754	default y if CPU_FEROCEON
1755	help
1756	  Implement faster copy_to_user and clear_user methods for CPU
1757	  cores where a 8-word STM instruction give significantly higher
1758	  memory write throughput than a sequence of individual 32bit stores.
1759
1760	  A possible side effect is a slight increase in scheduling latency
1761	  between threads sharing the same address space if they invoke
1762	  such copy operations with large buffers.
1763
1764	  However, if the CPU data cache is using a write-allocate mode,
1765	  this option is unlikely to provide any performance gain.
1766
1767config SECCOMP
1768	bool
1769	prompt "Enable seccomp to safely compute untrusted bytecode"
1770	---help---
1771	  This kernel feature is useful for number crunching applications
1772	  that may need to compute untrusted bytecode during their
1773	  execution. By using pipes or other transports made available to
1774	  the process as file descriptors supporting the read/write
1775	  syscalls, it's possible to isolate those applications in
1776	  their own address space using seccomp. Once seccomp is
1777	  enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1778	  and the task is only allowed to execute a few safe syscalls
1779	  defined by each seccomp mode.
1780
1781config SWIOTLB
1782	def_bool y
1783
1784config IOMMU_HELPER
1785	def_bool SWIOTLB
1786
1787config PARAVIRT
1788	bool "Enable paravirtualization code"
1789	help
1790	  This changes the kernel so it can modify itself when it is run
1791	  under a hypervisor, potentially improving performance significantly
1792	  over full virtualization.
1793
1794config PARAVIRT_TIME_ACCOUNTING
1795	bool "Paravirtual steal time accounting"
1796	select PARAVIRT
1797	default n
1798	help
1799	  Select this option to enable fine granularity task steal time
1800	  accounting. Time spent executing other tasks in parallel with
1801	  the current vCPU is discounted from the vCPU power. To account for
1802	  that, there can be a small performance impact.
1803
1804	  If in doubt, say N here.
1805
1806config XEN_DOM0
1807	def_bool y
1808	depends on XEN
1809
1810config XEN
1811	bool "Xen guest support on ARM"
1812	depends on ARM && AEABI && OF
1813	depends on CPU_V7 && !CPU_V6
1814	depends on !GENERIC_ATOMIC64
1815	depends on MMU
1816	select ARCH_DMA_ADDR_T_64BIT
1817	select ARM_PSCI
1818	select SWIOTLB_XEN
1819	select PARAVIRT
1820	help
1821	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1822
1823endmenu
1824
1825menu "Boot options"
1826
1827config USE_OF
1828	bool "Flattened Device Tree support"
1829	select IRQ_DOMAIN
1830	select OF
 
 
1831	help
1832	  Include support for flattened device tree machine descriptions.
1833
1834config ATAGS
1835	bool "Support for the traditional ATAGS boot data passing" if USE_OF
1836	default y
1837	help
1838	  This is the traditional way of passing data to the kernel at boot
1839	  time. If you are solely relying on the flattened device tree (or
1840	  the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1841	  to remove ATAGS support from your kernel binary.  If unsure,
1842	  leave this to y.
1843
1844config DEPRECATED_PARAM_STRUCT
1845	bool "Provide old way to pass kernel parameters"
1846	depends on ATAGS
1847	help
1848	  This was deprecated in 2001 and announced to live on for 5 years.
1849	  Some old boot loaders still use this way.
1850
1851# Compressed boot loader in ROM.  Yes, we really want to ask about
1852# TEXT and BSS so we preserve their values in the config files.
1853config ZBOOT_ROM_TEXT
1854	hex "Compressed ROM boot loader base address"
1855	default "0"
1856	help
1857	  The physical address at which the ROM-able zImage is to be
1858	  placed in the target.  Platforms which normally make use of
1859	  ROM-able zImage formats normally set this to a suitable
1860	  value in their defconfig file.
1861
1862	  If ZBOOT_ROM is not enabled, this has no effect.
1863
1864config ZBOOT_ROM_BSS
1865	hex "Compressed ROM boot loader BSS address"
1866	default "0"
1867	help
1868	  The base address of an area of read/write memory in the target
1869	  for the ROM-able zImage which must be available while the
1870	  decompressor is running. It must be large enough to hold the
1871	  entire decompressed kernel plus an additional 128 KiB.
1872	  Platforms which normally make use of ROM-able zImage formats
1873	  normally set this to a suitable value in their defconfig file.
1874
1875	  If ZBOOT_ROM is not enabled, this has no effect.
1876
1877config ZBOOT_ROM
1878	bool "Compressed boot loader in ROM/flash"
1879	depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1880	depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1881	help
1882	  Say Y here if you intend to execute your compressed kernel image
1883	  (zImage) directly from ROM or flash.  If unsure, say N.
1884
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1885config ARM_APPENDED_DTB
1886	bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1887	depends on OF
1888	help
1889	  With this option, the boot code will look for a device tree binary
1890	  (DTB) appended to zImage
1891	  (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1892
1893	  This is meant as a backward compatibility convenience for those
1894	  systems with a bootloader that can't be upgraded to accommodate
1895	  the documented boot protocol using a device tree.
1896
1897	  Beware that there is very little in terms of protection against
1898	  this option being confused by leftover garbage in memory that might
1899	  look like a DTB header after a reboot if no actual DTB is appended
1900	  to zImage.  Do not leave this option active in a production kernel
1901	  if you don't intend to always append a DTB.  Proper passing of the
1902	  location into r2 of a bootloader provided DTB is always preferable
1903	  to this option.
1904
1905config ARM_ATAG_DTB_COMPAT
1906	bool "Supplement the appended DTB with traditional ATAG information"
1907	depends on ARM_APPENDED_DTB
1908	help
1909	  Some old bootloaders can't be updated to a DTB capable one, yet
1910	  they provide ATAGs with memory configuration, the ramdisk address,
1911	  the kernel cmdline string, etc.  Such information is dynamically
1912	  provided by the bootloader and can't always be stored in a static
1913	  DTB.  To allow a device tree enabled kernel to be used with such
1914	  bootloaders, this option allows zImage to extract the information
1915	  from the ATAG list and store it at run time into the appended DTB.
1916
1917choice
1918	prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1919	default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1920
1921config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1922	bool "Use bootloader kernel arguments if available"
1923	help
1924	  Uses the command-line options passed by the boot loader instead of
1925	  the device tree bootargs property. If the boot loader doesn't provide
1926	  any, the device tree bootargs property will be used.
1927
1928config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1929	bool "Extend with bootloader kernel arguments"
1930	help
1931	  The command-line arguments provided by the boot loader will be
1932	  appended to the the device tree bootargs property.
1933
1934endchoice
1935
1936config CMDLINE
1937	string "Default kernel command string"
1938	default ""
1939	help
1940	  On some architectures (EBSA110 and CATS), there is currently no way
1941	  for the boot loader to pass arguments to the kernel. For these
1942	  architectures, you should supply some command-line options at build
1943	  time by entering them here. As a minimum, you should specify the
1944	  memory size and the root device (e.g., mem=64M root=/dev/nfs).
1945
1946choice
1947	prompt "Kernel command line type" if CMDLINE != ""
1948	default CMDLINE_FROM_BOOTLOADER
1949	depends on ATAGS
1950
1951config CMDLINE_FROM_BOOTLOADER
1952	bool "Use bootloader kernel arguments if available"
1953	help
1954	  Uses the command-line options passed by the boot loader. If
1955	  the boot loader doesn't provide any, the default kernel command
1956	  string provided in CMDLINE will be used.
1957
1958config CMDLINE_EXTEND
1959	bool "Extend bootloader kernel arguments"
1960	help
1961	  The command-line arguments provided by the boot loader will be
1962	  appended to the default kernel command string.
1963
1964config CMDLINE_FORCE
1965	bool "Always use the default kernel command string"
1966	help
1967	  Always use the default kernel command string, even if the boot
1968	  loader passes other arguments to the kernel.
1969	  This is useful if you cannot or don't want to change the
1970	  command-line options your boot loader passes to the kernel.
1971endchoice
1972
1973config XIP_KERNEL
1974	bool "Kernel Execute-In-Place from ROM"
1975	depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1976	help
1977	  Execute-In-Place allows the kernel to run from non-volatile storage
1978	  directly addressable by the CPU, such as NOR flash. This saves RAM
1979	  space since the text section of the kernel is not loaded from flash
1980	  to RAM.  Read-write sections, such as the data section and stack,
1981	  are still copied to RAM.  The XIP kernel is not compressed since
1982	  it has to run directly from flash, so it will take more space to
1983	  store it.  The flash address used to link the kernel object files,
1984	  and for storing it, is configuration dependent. Therefore, if you
1985	  say Y here, you must know the proper physical address where to
1986	  store the kernel image depending on your own flash memory usage.
1987
1988	  Also note that the make target becomes "make xipImage" rather than
1989	  "make zImage" or "make Image".  The final kernel binary to put in
1990	  ROM memory will be arch/arm/boot/xipImage.
1991
1992	  If unsure, say N.
1993
1994config XIP_PHYS_ADDR
1995	hex "XIP Kernel Physical Location"
1996	depends on XIP_KERNEL
1997	default "0x00080000"
1998	help
1999	  This is the physical address in your flash memory the kernel will
2000	  be linked for and stored to.  This address is dependent on your
2001	  own flash usage.
2002
2003config XIP_DEFLATED_DATA
2004	bool "Store kernel .data section compressed in ROM"
2005	depends on XIP_KERNEL
2006	select ZLIB_INFLATE
2007	help
2008	  Before the kernel is actually executed, its .data section has to be
2009	  copied to RAM from ROM. This option allows for storing that data
2010	  in compressed form and decompressed to RAM rather than merely being
2011	  copied, saving some precious ROM space. A possible drawback is a
2012	  slightly longer boot delay.
2013
2014config KEXEC
2015	bool "Kexec system call (EXPERIMENTAL)"
2016	depends on (!SMP || PM_SLEEP_SMP)
2017	depends on !CPU_V7M
2018	select KEXEC_CORE
2019	help
2020	  kexec is a system call that implements the ability to shutdown your
2021	  current kernel, and to start another kernel.  It is like a reboot
2022	  but it is independent of the system firmware.   And like a reboot
2023	  you can start any kernel with it, not just Linux.
2024
2025	  It is an ongoing process to be certain the hardware in a machine
2026	  is properly shutdown, so do not be surprised if this code does not
2027	  initially work for you.
2028
2029config ATAGS_PROC
2030	bool "Export atags in procfs"
2031	depends on ATAGS && KEXEC
2032	default y
2033	help
2034	  Should the atags used to boot the kernel be exported in an "atags"
2035	  file in procfs. Useful with kexec.
2036
2037config CRASH_DUMP
2038	bool "Build kdump crash kernel (EXPERIMENTAL)"
2039	help
2040	  Generate crash dump after being started by kexec. This should
2041	  be normally only set in special crash dump kernels which are
2042	  loaded in the main kernel with kexec-tools into a specially
2043	  reserved region and then later executed after a crash by
2044	  kdump/kexec. The crash dump kernel must be compiled to a
2045	  memory address not used by the main kernel
2046
2047	  For more details see Documentation/kdump/kdump.txt
2048
2049config AUTO_ZRELADDR
2050	bool "Auto calculation of the decompressed kernel image address"
2051	help
2052	  ZRELADDR is the physical address where the decompressed kernel
2053	  image will be placed. If AUTO_ZRELADDR is selected, the address
2054	  will be determined at run-time by masking the current IP with
2055	  0xf8000000. This assumes the zImage being placed in the first 128MB
2056	  from start of memory.
2057
2058config EFI_STUB
2059	bool
2060
2061config EFI
2062	bool "UEFI runtime support"
2063	depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2064	select UCS2_STRING
2065	select EFI_PARAMS_FROM_FDT
2066	select EFI_STUB
2067	select EFI_ARMSTUB
2068	select EFI_RUNTIME_WRAPPERS
2069	---help---
2070	  This option provides support for runtime services provided
2071	  by UEFI firmware (such as non-volatile variables, realtime
2072	  clock, and platform reset). A UEFI stub is also provided to
2073	  allow the kernel to be booted as an EFI application. This
2074	  is only useful for kernels that may run on systems that have
2075	  UEFI firmware.
2076
2077config DMI
2078	bool "Enable support for SMBIOS (DMI) tables"
2079	depends on EFI
2080	default y
2081	help
2082	  This enables SMBIOS/DMI feature for systems.
2083
2084	  This option is only useful on systems that have UEFI firmware.
2085	  However, even with this option, the resultant kernel should
2086	  continue to boot on existing non-UEFI platforms.
2087
2088	  NOTE: This does *NOT* enable or encourage the use of DMI quirks,
2089	  i.e., the the practice of identifying the platform via DMI to
2090	  decide whether certain workarounds for buggy hardware and/or
2091	  firmware need to be enabled. This would require the DMI subsystem
2092	  to be enabled much earlier than we do on ARM, which is non-trivial.
2093
2094endmenu
2095
2096menu "CPU Power Management"
2097
 
2098source "drivers/cpufreq/Kconfig"
 
2099
2100source "drivers/cpuidle/Kconfig"
2101
2102endmenu
2103
2104menu "Floating point emulation"
2105
2106comment "At least one emulation must be selected"
2107
2108config FPE_NWFPE
2109	bool "NWFPE math emulation"
2110	depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2111	---help---
2112	  Say Y to include the NWFPE floating point emulator in the kernel.
2113	  This is necessary to run most binaries. Linux does not currently
2114	  support floating point hardware so you need to say Y here even if
2115	  your machine has an FPA or floating point co-processor podule.
2116
2117	  You may say N here if you are going to load the Acorn FPEmulator
2118	  early in the bootup.
2119
2120config FPE_NWFPE_XP
2121	bool "Support extended precision"
2122	depends on FPE_NWFPE
2123	help
2124	  Say Y to include 80-bit support in the kernel floating-point
2125	  emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2126	  Note that gcc does not generate 80-bit operations by default,
2127	  so in most cases this option only enlarges the size of the
2128	  floating point emulator without any good reason.
2129
2130	  You almost surely want to say N here.
2131
2132config FPE_FASTFPE
2133	bool "FastFPE math emulation (EXPERIMENTAL)"
2134	depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2135	---help---
2136	  Say Y here to include the FAST floating point emulator in the kernel.
2137	  This is an experimental much faster emulator which now also has full
2138	  precision for the mantissa.  It does not support any exceptions.
2139	  It is very simple, and approximately 3-6 times faster than NWFPE.
2140
2141	  It should be sufficient for most programs.  It may be not suitable
2142	  for scientific calculations, but you have to check this for yourself.
2143	  If you do not feel you need a faster FP emulation you should better
2144	  choose NWFPE.
2145
2146config VFP
2147	bool "VFP-format floating point maths"
2148	depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2149	help
2150	  Say Y to include VFP support code in the kernel. This is needed
2151	  if your hardware includes a VFP unit.
2152
2153	  Please see <file:Documentation/arm/VFP/release-notes.txt> for
2154	  release notes and additional status information.
2155
2156	  Say N if your target does not have VFP hardware.
2157
2158config VFPv3
2159	bool
2160	depends on VFP
2161	default y if CPU_V7
2162
2163config NEON
2164	bool "Advanced SIMD (NEON) Extension support"
2165	depends on VFPv3 && CPU_V7
2166	help
2167	  Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2168	  Extension.
2169
2170config KERNEL_MODE_NEON
2171	bool "Support for NEON in kernel mode"
2172	depends on NEON && AEABI
2173	help
2174	  Say Y to include support for NEON in kernel mode.
2175
2176endmenu
2177
2178menu "Userspace binary formats"
2179
2180source "fs/Kconfig.binfmt"
2181
 
 
 
 
 
 
 
 
 
 
2182endmenu
2183
2184menu "Power management options"
2185
2186source "kernel/power/Kconfig"
2187
2188config ARCH_SUSPEND_POSSIBLE
 
2189	depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2190		CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2191	def_bool y
2192
2193config ARM_CPU_SUSPEND
2194	def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2195	depends on ARCH_SUSPEND_POSSIBLE
2196
2197config ARCH_HIBERNATION_POSSIBLE
2198	bool
2199	depends on MMU
2200	default y if ARCH_SUSPEND_POSSIBLE
2201
2202endmenu
2203
2204source "net/Kconfig"
2205
2206source "drivers/Kconfig"
2207
2208source "drivers/firmware/Kconfig"
2209
2210source "fs/Kconfig"
2211
2212source "arch/arm/Kconfig.debug"
2213
2214source "security/Kconfig"
2215
2216source "crypto/Kconfig"
2217if CRYPTO
2218source "arch/arm/crypto/Kconfig"
2219endif
2220
2221source "lib/Kconfig"
2222
2223source "arch/arm/kvm/Kconfig"