1/*
 2 * Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com)
 3 *
 4 * This program is free software; you can redistribute it and/or modify
 5 * it under the terms of the GNU General Public License version 2 as
 6 * published by the Free Software Foundation.
 7 */
 8
 9/*
10 * Skeleton device tree; the bare minimum needed to boot; just include and
11 * add a compatible value.
12 */
13
14/ {
15	compatible = "snps,arc";
 
16	#address-cells = <1>;
17	#size-cells = <1>;
18	chosen { };
19	aliases { };
20
21	cpus {
22		#address-cells = <1>;
23		#size-cells = <0>;
24
25		cpu@0 {
26			device_type = "cpu";
27			compatible = "snps,arc770d";
28			reg = <0>;
29			clocks = <&core_clk>;
30		};
31	};
32
33	/* TIMER0 with interrupt for clockevent */
34	timer0 {
35		compatible = "snps,arc-timer";
36		interrupts = <3>;
37		interrupt-parent = <&core_intc>;
38		clocks = <&core_clk>;
39	};
40
41	/* TIMER1 for free running clocksource */
42	timer1 {
43		compatible = "snps,arc-timer";
44		clocks = <&core_clk>;
45	};
46
47	memory {
48		device_type = "memory";
49		reg = <0x80000000 0x10000000>;	/* 256M */
50	};
51};

 1/*
 2 * Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com)
 3 *
 4 * This program is free software; you can redistribute it and/or modify
 5 * it under the terms of the GNU General Public License version 2 as
 6 * published by the Free Software Foundation.
 7 */
 8
 9/*
10 * Skeleton device tree; the bare minimum needed to boot; just include and
11 * add a compatible value.
12 */
13
14/ {
15	compatible = "snps,arc";
16	clock-frequency = <80000000>;	/* 80 MHZ */
17	#address-cells = <1>;
18	#size-cells = <1>;
19	chosen { };
20	aliases { };
21
22	cpus {
23		#address-cells = <1>;
24		#size-cells = <0>;
25
26		cpu@0 {
27			device_type = "cpu";
28			compatible = "snps,arc770d";
29			reg = <0>;
 
30		};
31	};
32
 
 
 
 
 
 
 
 
 
 
 
 
 
 
33	memory {
34		device_type = "memory";
35		reg = <0x00000000 0x10000000>;	/* 256M */
36	};
37};