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1/*
2 * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
3 * Author: Elaine <zhangqing@rock-chips.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
17#define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
18
19/* core clocks */
20#define PLL_APLL 1
21#define PLL_DPLL 2
22#define PLL_CPLL 3
23#define PLL_GPLL 4
24#define ARMCLK 5
25#define PLL_GPLL_DIV2 6
26#define PLL_GPLL_DIV3 7
27
28/* sclk gates (special clocks) */
29#define SCLK_SPI0 65
30#define SCLK_NANDC 67
31#define SCLK_SDMMC 68
32#define SCLK_SDIO 69
33#define SCLK_EMMC 71
34#define SCLK_UART0 77
35#define SCLK_UART1 78
36#define SCLK_UART2 79
37#define SCLK_I2S0 80
38#define SCLK_I2S1 81
39#define SCLK_SPDIF 83
40#define SCLK_TIMER0 85
41#define SCLK_TIMER1 86
42#define SCLK_TIMER2 87
43#define SCLK_TIMER3 88
44#define SCLK_TIMER4 89
45#define SCLK_TIMER5 90
46#define SCLK_SARADC 91
47#define SCLK_I2S_OUT 113
48#define SCLK_SDMMC_DRV 114
49#define SCLK_SDIO_DRV 115
50#define SCLK_EMMC_DRV 117
51#define SCLK_SDMMC_SAMPLE 118
52#define SCLK_SDIO_SAMPLE 119
53#define SCLK_EMMC_SAMPLE 121
54#define SCLK_VOP 122
55#define SCLK_MAC_SRC 124
56#define SCLK_MAC 126
57#define SCLK_MAC_REFOUT 127
58#define SCLK_MAC_REF 128
59#define SCLK_MAC_RX 129
60#define SCLK_MAC_TX 130
61#define SCLK_HEVC_CORE 134
62#define SCLK_RGA 135
63#define SCLK_CRYPTO 138
64#define SCLK_TSP 139
65#define SCLK_OTGPHY0 142
66#define SCLK_OTGPHY1 143
67#define SCLK_DDRC 144
68#define SCLK_PVTM_FUNC 145
69#define SCLK_PVTM_CORE 146
70#define SCLK_PVTM_GPU 147
71#define SCLK_MIPI_24M 148
72#define SCLK_PVTM 149
73#define SCLK_CIF_SRC 150
74#define SCLK_CIF_OUT_SRC 151
75#define SCLK_CIF_OUT 152
76#define SCLK_SFC 153
77#define SCLK_USB480M 154
78
79/* dclk gates */
80#define DCLK_VOP 190
81#define DCLK_EBC 191
82
83/* aclk gates */
84#define ACLK_VIO0 192
85#define ACLK_VIO1 193
86#define ACLK_DMAC 194
87#define ACLK_CPU 195
88#define ACLK_VEPU 196
89#define ACLK_VDPU 197
90#define ACLK_CIF 198
91#define ACLK_IEP 199
92#define ACLK_LCDC0 204
93#define ACLK_RGA 205
94#define ACLK_PERI 210
95#define ACLK_VOP 211
96#define ACLK_GMAC 212
97#define ACLK_GPU 213
98
99/* pclk gates */
100#define PCLK_SARADC 318
101#define PCLK_WDT 319
102#define PCLK_GPIO0 320
103#define PCLK_GPIO1 321
104#define PCLK_GPIO2 322
105#define PCLK_GPIO3 323
106#define PCLK_VIO_H2P 324
107#define PCLK_MIPI 325
108#define PCLK_EFUSE 326
109#define PCLK_HDMI 327
110#define PCLK_ACODEC 328
111#define PCLK_GRF 329
112#define PCLK_I2C0 332
113#define PCLK_I2C1 333
114#define PCLK_I2C2 334
115#define PCLK_I2C3 335
116#define PCLK_SPI0 338
117#define PCLK_UART0 341
118#define PCLK_UART1 342
119#define PCLK_UART2 343
120#define PCLK_TSADC 344
121#define PCLK_PWM 350
122#define PCLK_TIMER 353
123#define PCLK_CPU 354
124#define PCLK_PERI 363
125#define PCLK_GMAC 367
126#define PCLK_PMU_PRE 368
127#define PCLK_SIM_CARD 369
128
129/* hclk gates */
130#define HCLK_SPDIF 440
131#define HCLK_GPS 441
132#define HCLK_USBHOST 442
133#define HCLK_I2S_8CH 443
134#define HCLK_I2S_2CH 444
135#define HCLK_VOP 452
136#define HCLK_NANDC 453
137#define HCLK_SDMMC 456
138#define HCLK_SDIO 457
139#define HCLK_EMMC 459
140#define HCLK_CPU 460
141#define HCLK_VEPU 461
142#define HCLK_VDPU 462
143#define HCLK_LCDC0 463
144#define HCLK_EBC 465
145#define HCLK_VIO 466
146#define HCLK_RGA 467
147#define HCLK_IEP 468
148#define HCLK_VIO_H2P 469
149#define HCLK_CIF 470
150#define HCLK_HOST2 473
151#define HCLK_OTG 474
152#define HCLK_TSP 475
153#define HCLK_CRYPTO 476
154#define HCLK_PERI 478
155
156#define CLK_NR_CLKS (HCLK_PERI + 1)
157
158/* soft-reset indices */
159#define SRST_CORE0_PO 0
160#define SRST_CORE1_PO 1
161#define SRST_CORE2_PO 2
162#define SRST_CORE3_PO 3
163#define SRST_CORE0 4
164#define SRST_CORE1 5
165#define SRST_CORE2 6
166#define SRST_CORE3 7
167#define SRST_CORE0_DBG 8
168#define SRST_CORE1_DBG 9
169#define SRST_CORE2_DBG 10
170#define SRST_CORE3_DBG 11
171#define SRST_TOPDBG 12
172#define SRST_ACLK_CORE 13
173#define SRST_STRC_SYS_A 14
174#define SRST_L2C 15
175
176#define SRST_CPUSYS_H 18
177#define SRST_AHB2APBSYS_H 19
178#define SRST_SPDIF 20
179#define SRST_INTMEM 21
180#define SRST_ROM 22
181#define SRST_PERI_NIU 23
182#define SRST_I2S_2CH 24
183#define SRST_I2S_8CH 25
184#define SRST_GPU_PVTM 26
185#define SRST_FUNC_PVTM 27
186#define SRST_CORE_PVTM 29
187#define SRST_EFUSE_P 30
188#define SRST_ACODEC_P 31
189
190#define SRST_GPIO0 32
191#define SRST_GPIO1 33
192#define SRST_GPIO2 34
193#define SRST_GPIO3 35
194#define SRST_MIPIPHY_P 36
195#define SRST_UART0 39
196#define SRST_UART1 40
197#define SRST_UART2 41
198#define SRST_I2C0 43
199#define SRST_I2C1 44
200#define SRST_I2C2 45
201#define SRST_I2C3 46
202#define SRST_SFC 47
203
204#define SRST_PWM 48
205#define SRST_DAP_PO 50
206#define SRST_DAP 51
207#define SRST_DAP_SYS 52
208#define SRST_CRYPTO 53
209#define SRST_GRF 55
210#define SRST_GMAC 56
211#define SRST_PERIPH_SYS_A 57
212#define SRST_PERIPH_SYS_H 58
213#define SRST_PERIPH_SYS_P 59
214#define SRST_SMART_CARD 60
215#define SRST_CPU_PERI 61
216#define SRST_EMEM_PERI 62
217#define SRST_USB_PERI 63
218
219#define SRST_DMA 64
220#define SRST_GPS 67
221#define SRST_NANDC 68
222#define SRST_USBOTG0 69
223#define SRST_OTGC0 71
224#define SRST_USBOTG1 72
225#define SRST_OTGC1 74
226#define SRST_DDRMSCH 79
227
228#define SRST_SDMMC 81
229#define SRST_SDIO 82
230#define SRST_EMMC 83
231#define SRST_SPI 84
232#define SRST_WDT 86
233#define SRST_SARADC 87
234#define SRST_DDRPHY 88
235#define SRST_DDRPHY_P 89
236#define SRST_DDRCTRL 90
237#define SRST_DDRCTRL_P 91
238#define SRST_TSP 92
239#define SRST_TSP_CLKIN 93
240#define SRST_HOST0_ECHI 94
241
242#define SRST_HDMI_P 96
243#define SRST_VIO_ARBI_H 97
244#define SRST_VIO0_A 98
245#define SRST_VIO_BUS_H 99
246#define SRST_VOP_A 100
247#define SRST_VOP_H 101
248#define SRST_VOP_D 102
249#define SRST_UTMI0 103
250#define SRST_UTMI1 104
251#define SRST_USBPOR 105
252#define SRST_IEP_A 106
253#define SRST_IEP_H 107
254#define SRST_RGA_A 108
255#define SRST_RGA_H 109
256#define SRST_CIF0 110
257#define SRST_PMU 111
258
259#define SRST_VCODEC_A 112
260#define SRST_VCODEC_H 113
261#define SRST_VIO1_A 114
262#define SRST_HEVC_CORE 115
263#define SRST_VCODEC_NIU_A 116
264#define SRST_PMU_NIU_P 117
265#define SRST_LCDC0_S 119
266#define SRST_GPU 120
267#define SRST_GPU_NIU_A 122
268#define SRST_EBC_A 123
269#define SRST_EBC_H 124
270
271#define SRST_CORE_DBG 128
272#define SRST_DBG_P 129
273#define SRST_TIMER0 130
274#define SRST_TIMER1 131
275#define SRST_TIMER2 132
276#define SRST_TIMER3 133
277#define SRST_TIMER4 134
278#define SRST_TIMER5 135
279#define SRST_VIO_H2P 136
280#define SRST_VIO_MIPI_DSI 137
281
282#endif