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1/*
2 * Driver for Allwinner sun4i Pulse Width Modulation Controller
3 *
4 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9#include <linux/bitops.h>
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/err.h>
13#include <linux/io.h>
14#include <linux/jiffies.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/of_device.h>
18#include <linux/platform_device.h>
19#include <linux/pwm.h>
20#include <linux/slab.h>
21#include <linux/spinlock.h>
22#include <linux/time.h>
23
24#define PWM_CTRL_REG 0x0
25
26#define PWM_CH_PRD_BASE 0x4
27#define PWM_CH_PRD_OFFSET 0x4
28#define PWM_CH_PRD(ch) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))
29
30#define PWMCH_OFFSET 15
31#define PWM_PRESCAL_MASK GENMASK(3, 0)
32#define PWM_PRESCAL_OFF 0
33#define PWM_EN BIT(4)
34#define PWM_ACT_STATE BIT(5)
35#define PWM_CLK_GATING BIT(6)
36#define PWM_MODE BIT(7)
37#define PWM_PULSE BIT(8)
38#define PWM_BYPASS BIT(9)
39
40#define PWM_RDY_BASE 28
41#define PWM_RDY_OFFSET 1
42#define PWM_RDY(ch) BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
43
44#define PWM_PRD(prd) (((prd) - 1) << 16)
45#define PWM_PRD_MASK GENMASK(15, 0)
46
47#define PWM_DTY_MASK GENMASK(15, 0)
48
49#define PWM_REG_PRD(reg) ((((reg) >> 16) & PWM_PRD_MASK) + 1)
50#define PWM_REG_DTY(reg) ((reg) & PWM_DTY_MASK)
51#define PWM_REG_PRESCAL(reg, chan) (((reg) >> ((chan) * PWMCH_OFFSET)) & PWM_PRESCAL_MASK)
52
53#define BIT_CH(bit, chan) ((bit) << ((chan) * PWMCH_OFFSET))
54
55static const u32 prescaler_table[] = {
56 120,
57 180,
58 240,
59 360,
60 480,
61 0,
62 0,
63 0,
64 12000,
65 24000,
66 36000,
67 48000,
68 72000,
69 0,
70 0,
71 0, /* Actually 1 but tested separately */
72};
73
74struct sun4i_pwm_data {
75 bool has_prescaler_bypass;
76 unsigned int npwm;
77};
78
79struct sun4i_pwm_chip {
80 struct pwm_chip chip;
81 struct clk *clk;
82 void __iomem *base;
83 spinlock_t ctrl_lock;
84 const struct sun4i_pwm_data *data;
85 unsigned long next_period[2];
86 bool needs_delay[2];
87};
88
89static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip)
90{
91 return container_of(chip, struct sun4i_pwm_chip, chip);
92}
93
94static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip,
95 unsigned long offset)
96{
97 return readl(chip->base + offset);
98}
99
100static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
101 u32 val, unsigned long offset)
102{
103 writel(val, chip->base + offset);
104}
105
106static void sun4i_pwm_get_state(struct pwm_chip *chip,
107 struct pwm_device *pwm,
108 struct pwm_state *state)
109{
110 struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
111 u64 clk_rate, tmp;
112 u32 val;
113 unsigned int prescaler;
114
115 clk_rate = clk_get_rate(sun4i_pwm->clk);
116
117 val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
118
119 if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
120 sun4i_pwm->data->has_prescaler_bypass)
121 prescaler = 1;
122 else
123 prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];
124
125 if (prescaler == 0)
126 return;
127
128 if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm))
129 state->polarity = PWM_POLARITY_NORMAL;
130 else
131 state->polarity = PWM_POLARITY_INVERSED;
132
133 if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) ==
134 BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm))
135 state->enabled = true;
136 else
137 state->enabled = false;
138
139 val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm));
140
141 tmp = prescaler * NSEC_PER_SEC * PWM_REG_DTY(val);
142 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
143
144 tmp = prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);
145 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
146}
147
148static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
149 struct pwm_state *state,
150 u32 *dty, u32 *prd, unsigned int *prsclr)
151{
152 u64 clk_rate, div = 0;
153 unsigned int pval, prescaler = 0;
154
155 clk_rate = clk_get_rate(sun4i_pwm->clk);
156
157 if (sun4i_pwm->data->has_prescaler_bypass) {
158 /* First, test without any prescaler when available */
159 prescaler = PWM_PRESCAL_MASK;
160 pval = 1;
161 /*
162 * When not using any prescaler, the clock period in nanoseconds
163 * is not an integer so round it half up instead of
164 * truncating to get less surprising values.
165 */
166 div = clk_rate * state->period + NSEC_PER_SEC / 2;
167 do_div(div, NSEC_PER_SEC);
168 if (div - 1 > PWM_PRD_MASK)
169 prescaler = 0;
170 }
171
172 if (prescaler == 0) {
173 /* Go up from the first divider */
174 for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
175 if (!prescaler_table[prescaler])
176 continue;
177 pval = prescaler_table[prescaler];
178 div = clk_rate;
179 do_div(div, pval);
180 div = div * state->period;
181 do_div(div, NSEC_PER_SEC);
182 if (div - 1 <= PWM_PRD_MASK)
183 break;
184 }
185
186 if (div - 1 > PWM_PRD_MASK)
187 return -EINVAL;
188 }
189
190 *prd = div;
191 div *= state->duty_cycle;
192 do_div(div, state->period);
193 *dty = div;
194 *prsclr = prescaler;
195
196 div = (u64)pval * NSEC_PER_SEC * *prd;
197 state->period = DIV_ROUND_CLOSEST_ULL(div, clk_rate);
198
199 div = (u64)pval * NSEC_PER_SEC * *dty;
200 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(div, clk_rate);
201
202 return 0;
203}
204
205static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
206 struct pwm_state *state)
207{
208 struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
209 struct pwm_state cstate;
210 u32 ctrl;
211 int ret;
212 unsigned int delay_us;
213 unsigned long now;
214
215 pwm_get_state(pwm, &cstate);
216
217 if (!cstate.enabled) {
218 ret = clk_prepare_enable(sun4i_pwm->clk);
219 if (ret) {
220 dev_err(chip->dev, "failed to enable PWM clock\n");
221 return ret;
222 }
223 }
224
225 spin_lock(&sun4i_pwm->ctrl_lock);
226 ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
227
228 if ((cstate.period != state->period) ||
229 (cstate.duty_cycle != state->duty_cycle)) {
230 u32 period, duty, val;
231 unsigned int prescaler;
232
233 ret = sun4i_pwm_calculate(sun4i_pwm, state,
234 &duty, &period, &prescaler);
235 if (ret) {
236 dev_err(chip->dev, "period exceeds the maximum value\n");
237 spin_unlock(&sun4i_pwm->ctrl_lock);
238 if (!cstate.enabled)
239 clk_disable_unprepare(sun4i_pwm->clk);
240 return ret;
241 }
242
243 if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
244 /* Prescaler changed, the clock has to be gated */
245 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
246 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
247
248 ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
249 ctrl |= BIT_CH(prescaler, pwm->hwpwm);
250 }
251
252 val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
253 sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
254 sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
255 usecs_to_jiffies(cstate.period / 1000 + 1);
256 sun4i_pwm->needs_delay[pwm->hwpwm] = true;
257 }
258
259 if (state->polarity != PWM_POLARITY_NORMAL)
260 ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
261 else
262 ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
263
264 ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
265 if (state->enabled) {
266 ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);
267 } else if (!sun4i_pwm->needs_delay[pwm->hwpwm]) {
268 ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
269 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
270 }
271
272 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
273
274 spin_unlock(&sun4i_pwm->ctrl_lock);
275
276 if (state->enabled)
277 return 0;
278
279 if (!sun4i_pwm->needs_delay[pwm->hwpwm]) {
280 clk_disable_unprepare(sun4i_pwm->clk);
281 return 0;
282 }
283
284 /* We need a full period to elapse before disabling the channel. */
285 now = jiffies;
286 if (sun4i_pwm->needs_delay[pwm->hwpwm] &&
287 time_before(now, sun4i_pwm->next_period[pwm->hwpwm])) {
288 delay_us = jiffies_to_usecs(sun4i_pwm->next_period[pwm->hwpwm] -
289 now);
290 if ((delay_us / 500) > MAX_UDELAY_MS)
291 msleep(delay_us / 1000 + 1);
292 else
293 usleep_range(delay_us, delay_us * 2);
294 }
295 sun4i_pwm->needs_delay[pwm->hwpwm] = false;
296
297 spin_lock(&sun4i_pwm->ctrl_lock);
298 ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
299 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
300 ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
301 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
302 spin_unlock(&sun4i_pwm->ctrl_lock);
303
304 clk_disable_unprepare(sun4i_pwm->clk);
305
306 return 0;
307}
308
309static const struct pwm_ops sun4i_pwm_ops = {
310 .apply = sun4i_pwm_apply,
311 .get_state = sun4i_pwm_get_state,
312 .owner = THIS_MODULE,
313};
314
315static const struct sun4i_pwm_data sun4i_pwm_dual_nobypass = {
316 .has_prescaler_bypass = false,
317 .npwm = 2,
318};
319
320static const struct sun4i_pwm_data sun4i_pwm_dual_bypass = {
321 .has_prescaler_bypass = true,
322 .npwm = 2,
323};
324
325static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
326 .has_prescaler_bypass = true,
327 .npwm = 1,
328};
329
330static const struct of_device_id sun4i_pwm_dt_ids[] = {
331 {
332 .compatible = "allwinner,sun4i-a10-pwm",
333 .data = &sun4i_pwm_dual_nobypass,
334 }, {
335 .compatible = "allwinner,sun5i-a10s-pwm",
336 .data = &sun4i_pwm_dual_bypass,
337 }, {
338 .compatible = "allwinner,sun5i-a13-pwm",
339 .data = &sun4i_pwm_single_bypass,
340 }, {
341 .compatible = "allwinner,sun7i-a20-pwm",
342 .data = &sun4i_pwm_dual_bypass,
343 }, {
344 .compatible = "allwinner,sun8i-h3-pwm",
345 .data = &sun4i_pwm_single_bypass,
346 }, {
347 /* sentinel */
348 },
349};
350MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);
351
352static int sun4i_pwm_probe(struct platform_device *pdev)
353{
354 struct sun4i_pwm_chip *pwm;
355 struct resource *res;
356 int ret;
357
358 pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
359 if (!pwm)
360 return -ENOMEM;
361
362 pwm->data = of_device_get_match_data(&pdev->dev);
363 if (!pwm->data)
364 return -ENODEV;
365
366 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
367 pwm->base = devm_ioremap_resource(&pdev->dev, res);
368 if (IS_ERR(pwm->base))
369 return PTR_ERR(pwm->base);
370
371 pwm->clk = devm_clk_get(&pdev->dev, NULL);
372 if (IS_ERR(pwm->clk))
373 return PTR_ERR(pwm->clk);
374
375 pwm->chip.dev = &pdev->dev;
376 pwm->chip.ops = &sun4i_pwm_ops;
377 pwm->chip.base = -1;
378 pwm->chip.npwm = pwm->data->npwm;
379 pwm->chip.of_xlate = of_pwm_xlate_with_flags;
380 pwm->chip.of_pwm_n_cells = 3;
381
382 spin_lock_init(&pwm->ctrl_lock);
383
384 ret = pwmchip_add(&pwm->chip);
385 if (ret < 0) {
386 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
387 return ret;
388 }
389
390 platform_set_drvdata(pdev, pwm);
391
392 return 0;
393}
394
395static int sun4i_pwm_remove(struct platform_device *pdev)
396{
397 struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
398
399 return pwmchip_remove(&pwm->chip);
400}
401
402static struct platform_driver sun4i_pwm_driver = {
403 .driver = {
404 .name = "sun4i-pwm",
405 .of_match_table = sun4i_pwm_dt_ids,
406 },
407 .probe = sun4i_pwm_probe,
408 .remove = sun4i_pwm_remove,
409};
410module_platform_driver(sun4i_pwm_driver);
411
412MODULE_ALIAS("platform:sun4i-pwm");
413MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
414MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
415MODULE_LICENSE("GPL v2");