1/*******************************************************************************
  2  DWMAC DMA Header file.
  3
  4  Copyright (C) 2007-2009  STMicroelectronics Ltd
  5
  6  This program is free software; you can redistribute it and/or modify it
  7  under the terms and conditions of the GNU General Public License,
  8  version 2, as published by the Free Software Foundation.
  9
 10  This program is distributed in the hope it will be useful, but WITHOUT
 11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 12  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 13  more details.
 14
 15  You should have received a copy of the GNU General Public License along with
 16  this program; if not, write to the Free Software Foundation, Inc.,
 17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 18
 19  The full GNU General Public License is included in this distribution in
 20  the file called "COPYING".
 21
 22  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
 23*******************************************************************************/
 24
 25/* DMA CRS Control and Status Register Mapping */
 26#define DMA_BUS_MODE		0x00001000	/* Bus Mode */
 27#define DMA_XMT_POLL_DEMAND	0x00001004	/* Transmit Poll Demand */
 28#define DMA_RCV_POLL_DEMAND	0x00001008	/* Received Poll Demand */
 29#define DMA_RCV_BASE_ADDR	0x0000100c	/* Receive List Base */
 30#define DMA_TX_BASE_ADDR	0x00001010	/* Transmit List Base */
 31#define DMA_STATUS		0x00001014	/* Status Register */
 32#define DMA_CONTROL		0x00001018	/* Ctrl (Operational Mode) */
 33#define DMA_INTR_ENA		0x0000101c	/* Interrupt Enable */
 34#define DMA_MISSED_FRAME_CTR	0x00001020	/* Missed Frame Counter */
 35#define DMA_CUR_TX_BUF_ADDR	0x00001050	/* Current Host Tx Buffer */
 36#define DMA_CUR_RX_BUF_ADDR	0x00001054	/* Current Host Rx Buffer */
 37
 38/* DMA Control register defines */
 39#define DMA_CONTROL_ST		0x00002000	/* Start/Stop Transmission */
 40#define DMA_CONTROL_SR		0x00000002	/* Start/Stop Receive */
 41
 42/* DMA Normal interrupt */
 43#define DMA_INTR_ENA_NIE 0x00010000	/* Normal Summary */
 44#define DMA_INTR_ENA_TIE 0x00000001	/* Transmit Interrupt */
 45#define DMA_INTR_ENA_TUE 0x00000004	/* Transmit Buffer Unavailable */
 46#define DMA_INTR_ENA_RIE 0x00000040	/* Receive Interrupt */
 47#define DMA_INTR_ENA_ERE 0x00004000	/* Early Receive */
 48
 49#define DMA_INTR_NORMAL	(DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \
 50			DMA_INTR_ENA_TIE)
 51
 52/* DMA Abnormal interrupt */
 53#define DMA_INTR_ENA_AIE 0x00008000	/* Abnormal Summary */
 54#define DMA_INTR_ENA_FBE 0x00002000	/* Fatal Bus Error */
 55#define DMA_INTR_ENA_ETE 0x00000400	/* Early Transmit */
 56#define DMA_INTR_ENA_RWE 0x00000200	/* Receive Watchdog */
 57#define DMA_INTR_ENA_RSE 0x00000100	/* Receive Stopped */
 58#define DMA_INTR_ENA_RUE 0x00000080	/* Receive Buffer Unavailable */
 59#define DMA_INTR_ENA_UNE 0x00000020	/* Tx Underflow */
 60#define DMA_INTR_ENA_OVE 0x00000010	/* Receive Overflow */
 61#define DMA_INTR_ENA_TJE 0x00000008	/* Transmit Jabber */
 62#define DMA_INTR_ENA_TSE 0x00000002	/* Transmit Stopped */
 63
 64#define DMA_INTR_ABNORMAL	(DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
 65				DMA_INTR_ENA_UNE)
 66
 67/* DMA default interrupt mask */
 68#define DMA_INTR_DEFAULT_MASK	(DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)
 69
 70/* DMA Status register defines */
 71#define DMA_STATUS_GPI		0x10000000	/* PMT interrupt */
 72#define DMA_STATUS_GMI		0x08000000	/* MMC interrupt */
 73#define DMA_STATUS_GLI		0x04000000	/* GMAC Line interface int */
 74#define DMA_STATUS_GMI		0x08000000
 75#define DMA_STATUS_GLI		0x04000000
 76#define DMA_STATUS_EB_MASK	0x00380000	/* Error Bits Mask */
 77#define DMA_STATUS_EB_TX_ABORT	0x00080000	/* Error Bits - TX Abort */
 78#define DMA_STATUS_EB_RX_ABORT	0x00100000	/* Error Bits - RX Abort */
 79#define DMA_STATUS_TS_MASK	0x00700000	/* Transmit Process State */
 80#define DMA_STATUS_TS_SHIFT	20
 81#define DMA_STATUS_RS_MASK	0x000e0000	/* Receive Process State */
 82#define DMA_STATUS_RS_SHIFT	17
 83#define DMA_STATUS_NIS	0x00010000	/* Normal Interrupt Summary */
 84#define DMA_STATUS_AIS	0x00008000	/* Abnormal Interrupt Summary */
 85#define DMA_STATUS_ERI	0x00004000	/* Early Receive Interrupt */
 86#define DMA_STATUS_FBI	0x00002000	/* Fatal Bus Error Interrupt */
 87#define DMA_STATUS_ETI	0x00000400	/* Early Transmit Interrupt */
 88#define DMA_STATUS_RWT	0x00000200	/* Receive Watchdog Timeout */
 89#define DMA_STATUS_RPS	0x00000100	/* Receive Process Stopped */
 90#define DMA_STATUS_RU	0x00000080	/* Receive Buffer Unavailable */
 91#define DMA_STATUS_RI	0x00000040	/* Receive Interrupt */
 92#define DMA_STATUS_UNF	0x00000020	/* Transmit Underflow */
 93#define DMA_STATUS_OVF	0x00000010	/* Receive Overflow */
 94#define DMA_STATUS_TJT	0x00000008	/* Transmit Jabber Timeout */
 95#define DMA_STATUS_TU	0x00000004	/* Transmit Buffer Unavailable */
 96#define DMA_STATUS_TPS	0x00000002	/* Transmit Process Stopped */
 97#define DMA_STATUS_TI	0x00000001	/* Transmit Interrupt */
 98#define DMA_CONTROL_FTF		0x00100000 /* Flush transmit FIFO */
 99
100extern void dwmac_enable_dma_transmission(void __iomem *ioaddr);
101extern void dwmac_enable_dma_irq(void __iomem *ioaddr);
102extern void dwmac_disable_dma_irq(void __iomem *ioaddr);
103extern void dwmac_dma_start_tx(void __iomem *ioaddr);
104extern void dwmac_dma_stop_tx(void __iomem *ioaddr);
105extern void dwmac_dma_start_rx(void __iomem *ioaddr);
106extern void dwmac_dma_stop_rx(void __iomem *ioaddr);
107extern int dwmac_dma_interrupt(void __iomem *ioaddr,
108				struct stmmac_extra_stats *x);