1/*******************************************************************************
  2  This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
  3  DWC Ether MAC 10/100/1000 Universal version 3.41a  has been used for
  4  developing this code.
  5
  6  This contains the functions to handle the dma.
  7
  8  Copyright (C) 2007-2009  STMicroelectronics Ltd
  9
 10  This program is free software; you can redistribute it and/or modify it
 11  under the terms and conditions of the GNU General Public License,
 12  version 2, as published by the Free Software Foundation.
 13
 14  This program is distributed in the hope it will be useful, but WITHOUT
 15  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 16  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 17  more details.
 18
 19  You should have received a copy of the GNU General Public License along with
 20  this program; if not, write to the Free Software Foundation, Inc.,
 21  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 22
 23  The full GNU General Public License is included in this distribution in
 24  the file called "COPYING".
 25
 26  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
 27*******************************************************************************/
 28
 29#include <asm/io.h>
 30#include "dwmac1000.h"
 31#include "dwmac_dma.h"
 32
 33static int dwmac1000_dma_init(void __iomem *ioaddr, int pbl, u32 dma_tx,
 34			      u32 dma_rx)
 35{
 36	u32 value = readl(ioaddr + DMA_BUS_MODE);
 37	int limit;
 38
 39	/* DMA SW reset */
 40	value |= DMA_BUS_MODE_SFT_RESET;
 41	writel(value, ioaddr + DMA_BUS_MODE);
 42	limit = 15000;
 43	while (limit--) {
 44		if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))
 45			break;
 46	}
 47	if (limit < 0)
 48		return -EBUSY;
 49
 50	value = /* DMA_BUS_MODE_FB | */ DMA_BUS_MODE_4PBL |
 51	    ((pbl << DMA_BUS_MODE_PBL_SHIFT) |
 52	     (pbl << DMA_BUS_MODE_RPBL_SHIFT));
 53
 54#ifdef CONFIG_STMMAC_DA
 55	value |= DMA_BUS_MODE_DA;	/* Rx has priority over tx */
 56#endif
 57	writel(value, ioaddr + DMA_BUS_MODE);
 58
 59	/* Mask interrupts by writing to CSR7 */
 60	writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
 61
 62	/* The base address of the RX/TX descriptor lists must be written into
 63	 * DMA CSR3 and CSR4, respectively. */
 64	writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR);
 65	writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR);
 66
 67	return 0;
 68}
 69
 70static void dwmac1000_dma_operation_mode(void __iomem *ioaddr, int txmode,
 71				    int rxmode)
 72{
 73	u32 csr6 = readl(ioaddr + DMA_CONTROL);
 74
 75	if (txmode == SF_DMA_MODE) {
 76		CHIP_DBG(KERN_DEBUG "GMAC: enable TX store and forward mode\n");
 77		/* Transmit COE type 2 cannot be done in cut-through mode. */
 78		csr6 |= DMA_CONTROL_TSF;
 79		/* Operating on second frame increase the performance
 80		 * especially when transmit store-and-forward is used.*/
 81		csr6 |= DMA_CONTROL_OSF;
 82	} else {
 83		CHIP_DBG(KERN_DEBUG "GMAC: disabling TX store and forward mode"
 84			      " (threshold = %d)\n", txmode);
 85		csr6 &= ~DMA_CONTROL_TSF;
 86		csr6 &= DMA_CONTROL_TC_TX_MASK;
 87		/* Set the transmit threshold */
 88		if (txmode <= 32)
 89			csr6 |= DMA_CONTROL_TTC_32;
 90		else if (txmode <= 64)
 91			csr6 |= DMA_CONTROL_TTC_64;
 92		else if (txmode <= 128)
 93			csr6 |= DMA_CONTROL_TTC_128;
 94		else if (txmode <= 192)
 95			csr6 |= DMA_CONTROL_TTC_192;
 96		else
 97			csr6 |= DMA_CONTROL_TTC_256;
 98	}
 99
100	if (rxmode == SF_DMA_MODE) {
101		CHIP_DBG(KERN_DEBUG "GMAC: enable RX store and forward mode\n");
102		csr6 |= DMA_CONTROL_RSF;
103	} else {
104		CHIP_DBG(KERN_DEBUG "GMAC: disabling RX store and forward mode"
105			      " (threshold = %d)\n", rxmode);
106		csr6 &= ~DMA_CONTROL_RSF;
107		csr6 &= DMA_CONTROL_TC_RX_MASK;
108		if (rxmode <= 32)
109			csr6 |= DMA_CONTROL_RTC_32;
110		else if (rxmode <= 64)
111			csr6 |= DMA_CONTROL_RTC_64;
112		else if (rxmode <= 96)
113			csr6 |= DMA_CONTROL_RTC_96;
114		else
115			csr6 |= DMA_CONTROL_RTC_128;
116	}
117
118	writel(csr6, ioaddr + DMA_CONTROL);
119}
120
121/* Not yet implemented --- no RMON module */
122static void dwmac1000_dma_diagnostic_fr(void *data,
123		  struct stmmac_extra_stats *x, void __iomem *ioaddr)
124{
125	return;
126}
127
128static void dwmac1000_dump_dma_regs(void __iomem *ioaddr)
129{
130	int i;
131	pr_info(" DMA registers\n");
132	for (i = 0; i < 22; i++) {
133		if ((i < 9) || (i > 17)) {
134			int offset = i * 4;
135			pr_err("\t Reg No. %d (offset 0x%x): 0x%08x\n", i,
136			       (DMA_BUS_MODE + offset),
137			       readl(ioaddr + DMA_BUS_MODE + offset));
138		}
139	}
140}
141
142const struct stmmac_dma_ops dwmac1000_dma_ops = {
143	.init = dwmac1000_dma_init,
144	.dump_regs = dwmac1000_dump_dma_regs,
145	.dma_mode = dwmac1000_dma_operation_mode,
146	.dma_diagnostic_fr = dwmac1000_dma_diagnostic_fr,
147	.enable_dma_transmission = dwmac_enable_dma_transmission,
148	.enable_dma_irq = dwmac_enable_dma_irq,
149	.disable_dma_irq = dwmac_disable_dma_irq,
150	.start_tx = dwmac_dma_start_tx,
151	.stop_tx = dwmac_dma_stop_tx,
152	.start_rx = dwmac_dma_start_rx,
153	.stop_rx = dwmac_dma_stop_rx,
154	.dma_interrupt = dwmac_dma_interrupt,
155};