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1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include "ixgbe.h"
29#include "ixgbe_type.h"
30#include "ixgbe_dcb.h"
31#include "ixgbe_dcb_82599.h"
32
33/**
34 * ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter
35 * @hw: pointer to hardware structure
36 * @refill: refill credits index by traffic class
37 * @max: max credits index by traffic class
38 * @bwg_id: bandwidth grouping indexed by traffic class
39 * @prio_type: priority type indexed by traffic class
40 *
41 * Configure Rx Packet Arbiter and credits for each traffic class.
42 */
43s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw,
44 u16 *refill,
45 u16 *max,
46 u8 *bwg_id,
47 u8 *prio_type,
48 u8 *prio_tc)
49{
50 u32 reg = 0;
51 u32 credit_refill = 0;
52 u32 credit_max = 0;
53 u8 i = 0;
54
55 /*
56 * Disable the arbiter before changing parameters
57 * (always enable recycle mode; WSP)
58 */
59 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
60 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
61
62 /* Map all traffic classes to their UP, 1 to 1 */
63 reg = 0;
64 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
65 reg |= (prio_tc[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT));
66 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
67
68 /* Configure traffic class credits and priority */
69 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
70 credit_refill = refill[i];
71 credit_max = max[i];
72 reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT);
73
74 reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT;
75
76 if (prio_type[i] == prio_link)
77 reg |= IXGBE_RTRPT4C_LSP;
78
79 IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg);
80 }
81
82 /*
83 * Configure Rx packet plane (recycle mode; WSP) and
84 * enable arbiter
85 */
86 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
87 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
88
89 return 0;
90}
91
92/**
93 * ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter
94 * @hw: pointer to hardware structure
95 * @refill: refill credits index by traffic class
96 * @max: max credits index by traffic class
97 * @bwg_id: bandwidth grouping indexed by traffic class
98 * @prio_type: priority type indexed by traffic class
99 *
100 * Configure Tx Descriptor Arbiter and credits for each traffic class.
101 */
102s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw,
103 u16 *refill,
104 u16 *max,
105 u8 *bwg_id,
106 u8 *prio_type)
107{
108 u32 reg, max_credits;
109 u8 i;
110
111 /* Clear the per-Tx queue credits; we use per-TC instead */
112 for (i = 0; i < 128; i++) {
113 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
114 IXGBE_WRITE_REG(hw, IXGBE_RTTDT1C, 0);
115 }
116
117 /* Configure traffic class credits and priority */
118 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
119 max_credits = max[i];
120 reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT;
121 reg |= refill[i];
122 reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT;
123
124 if (prio_type[i] == prio_group)
125 reg |= IXGBE_RTTDT2C_GSP;
126
127 if (prio_type[i] == prio_link)
128 reg |= IXGBE_RTTDT2C_LSP;
129
130 IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg);
131 }
132
133 /*
134 * Configure Tx descriptor plane (recycle mode; WSP) and
135 * enable arbiter
136 */
137 reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM;
138 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
139
140 return 0;
141}
142
143/**
144 * ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter
145 * @hw: pointer to hardware structure
146 * @refill: refill credits index by traffic class
147 * @max: max credits index by traffic class
148 * @bwg_id: bandwidth grouping indexed by traffic class
149 * @prio_type: priority type indexed by traffic class
150 *
151 * Configure Tx Packet Arbiter and credits for each traffic class.
152 */
153s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw,
154 u16 *refill,
155 u16 *max,
156 u8 *bwg_id,
157 u8 *prio_type,
158 u8 *prio_tc)
159{
160 u32 reg;
161 u8 i;
162
163 /*
164 * Disable the arbiter before changing parameters
165 * (always enable recycle mode; SP; arb delay)
166 */
167 reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
168 (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT) |
169 IXGBE_RTTPCS_ARBDIS;
170 IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
171
172 /* Map all traffic classes to their UP, 1 to 1 */
173 reg = 0;
174 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
175 reg |= (prio_tc[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT));
176 IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg);
177
178 /* Configure traffic class credits and priority */
179 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
180 reg = refill[i];
181 reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT;
182 reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT;
183
184 if (prio_type[i] == prio_group)
185 reg |= IXGBE_RTTPT2C_GSP;
186
187 if (prio_type[i] == prio_link)
188 reg |= IXGBE_RTTPT2C_LSP;
189
190 IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg);
191 }
192
193 /*
194 * Configure Tx packet plane (recycle mode; SP; arb delay) and
195 * enable arbiter
196 */
197 reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
198 (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT);
199 IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
200
201 return 0;
202}
203
204/**
205 * ixgbe_dcb_config_pfc_82599 - Configure priority flow control
206 * @hw: pointer to hardware structure
207 * @pfc_en: enabled pfc bitmask
208 *
209 * Configure Priority Flow Control (PFC) for each traffic class.
210 */
211s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en)
212{
213 u32 i, reg, rx_pba_size;
214
215 /* Configure PFC Tx thresholds per TC */
216 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
217 int enabled = pfc_en & (1 << i);
218 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
219 rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
220
221 reg = (rx_pba_size - hw->fc.low_water) << 10;
222
223 if (enabled)
224 reg |= IXGBE_FCRTL_XONE;
225 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), reg);
226
227 reg = (rx_pba_size - hw->fc.high_water) << 10;
228 if (enabled)
229 reg |= IXGBE_FCRTH_FCEN;
230 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
231 }
232
233 if (pfc_en) {
234 /* Configure pause time (2 TCs per register) */
235 reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
236 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
237 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
238
239 /* Configure flow control refresh threshold value */
240 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
241
242
243 reg = IXGBE_FCCFG_TFCE_PRIORITY;
244 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, reg);
245 /*
246 * Enable Receive PFC
247 * 82599 will always honor XOFF frames we receive when
248 * we are in PFC mode however X540 only honors enabled
249 * traffic classes.
250 */
251 reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
252 reg &= ~IXGBE_MFLCN_RFCE;
253 reg |= IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_DPF;
254
255 if (hw->mac.type == ixgbe_mac_X540)
256 reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;
257
258 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
259
260 } else {
261 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
262 hw->mac.ops.fc_enable(hw, i);
263 }
264
265 return 0;
266}
267
268/**
269 * ixgbe_dcb_config_tc_stats_82599 - Config traffic class statistics
270 * @hw: pointer to hardware structure
271 *
272 * Configure queue statistics registers, all queues belonging to same traffic
273 * class uses a single set of queue statistics counters.
274 */
275static s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw)
276{
277 u32 reg = 0;
278 u8 i = 0;
279
280 /*
281 * Receive Queues stats setting
282 * 32 RQSMR registers, each configuring 4 queues.
283 * Set all 16 queues of each TC to the same stat
284 * with TC 'n' going to stat 'n'.
285 */
286 for (i = 0; i < 32; i++) {
287 reg = 0x01010101 * (i / 4);
288 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
289 }
290 /*
291 * Transmit Queues stats setting
292 * 32 TQSM registers, each controlling 4 queues.
293 * Set all queues of each TC to the same stat
294 * with TC 'n' going to stat 'n'.
295 * Tx queues are allocated non-uniformly to TCs:
296 * 32, 32, 16, 16, 8, 8, 8, 8.
297 */
298 for (i = 0; i < 32; i++) {
299 if (i < 8)
300 reg = 0x00000000;
301 else if (i < 16)
302 reg = 0x01010101;
303 else if (i < 20)
304 reg = 0x02020202;
305 else if (i < 24)
306 reg = 0x03030303;
307 else if (i < 26)
308 reg = 0x04040404;
309 else if (i < 28)
310 reg = 0x05050505;
311 else if (i < 30)
312 reg = 0x06060606;
313 else
314 reg = 0x07070707;
315 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);
316 }
317
318 return 0;
319}
320
321/**
322 * ixgbe_dcb_hw_config_82599 - Configure and enable DCB
323 * @hw: pointer to hardware structure
324 * @refill: refill credits index by traffic class
325 * @max: max credits index by traffic class
326 * @bwg_id: bandwidth grouping indexed by traffic class
327 * @prio_type: priority type indexed by traffic class
328 * @pfc_en: enabled pfc bitmask
329 *
330 * Configure dcb settings and enable dcb mode.
331 */
332s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill,
333 u16 *max, u8 *bwg_id, u8 *prio_type, u8 *prio_tc)
334{
335 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
336 prio_type, prio_tc);
337 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
338 bwg_id, prio_type);
339 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max,
340 bwg_id, prio_type, prio_tc);
341 ixgbe_dcb_config_pfc_82599(hw, pfc_en);
342 ixgbe_dcb_config_tc_stats_82599(hw);
343
344 return 0;
345}
346