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1/*
2 * Tehuti Networks(R) Network Driver
3 * ethtool interface implementation
4 * Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12/*
13 * RX HW/SW interaction overview
14 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
15 * There are 2 types of RX communication channels between driver and NIC.
16 * 1) RX Free Fifo - RXF - holds descriptors of empty buffers to accept incoming
17 * traffic. This Fifo is filled by SW and is readen by HW. Each descriptor holds
18 * info about buffer's location, size and ID. An ID field is used to identify a
19 * buffer when it's returned with data via RXD Fifo (see below)
20 * 2) RX Data Fifo - RXD - holds descriptors of full buffers. This Fifo is
21 * filled by HW and is readen by SW. Each descriptor holds status and ID.
22 * HW pops descriptor from RXF Fifo, stores ID, fills buffer with incoming data,
23 * via dma moves it into host memory, builds new RXD descriptor with same ID,
24 * pushes it into RXD Fifo and raises interrupt to indicate new RX data.
25 *
26 * Current NIC configuration (registers + firmware) makes NIC use 2 RXF Fifos.
27 * One holds 1.5K packets and another - 26K packets. Depending on incoming
28 * packet size, HW desides on a RXF Fifo to pop buffer from. When packet is
29 * filled with data, HW builds new RXD descriptor for it and push it into single
30 * RXD Fifo.
31 *
32 * RX SW Data Structures
33 * ~~~~~~~~~~~~~~~~~~~~~
34 * skb db - used to keep track of all skbs owned by SW and their dma addresses.
35 * For RX case, ownership lasts from allocating new empty skb for RXF until
36 * accepting full skb from RXD and passing it to OS. Each RXF Fifo has its own
37 * skb db. Implemented as array with bitmask.
38 * fifo - keeps info about fifo's size and location, relevant HW registers,
39 * usage and skb db. Each RXD and RXF Fifo has its own fifo structure.
40 * Implemented as simple struct.
41 *
42 * RX SW Execution Flow
43 * ~~~~~~~~~~~~~~~~~~~~
44 * Upon initialization (ifconfig up) driver creates RX fifos and initializes
45 * relevant registers. At the end of init phase, driver enables interrupts.
46 * NIC sees that there is no RXF buffers and raises
47 * RD_INTR interrupt, isr fills skbs and Rx begins.
48 * Driver has two receive operation modes:
49 * NAPI - interrupt-driven mixed with polling
50 * interrupt-driven only
51 *
52 * Interrupt-driven only flow is following. When buffer is ready, HW raises
53 * interrupt and isr is called. isr collects all available packets
54 * (bdx_rx_receive), refills skbs (bdx_rx_alloc_skbs) and exit.
55
56 * Rx buffer allocation note
57 * ~~~~~~~~~~~~~~~~~~~~~~~~~
58 * Driver cares to feed such amount of RxF descriptors that respective amount of
59 * RxD descriptors can not fill entire RxD fifo. The main reason is lack of
60 * overflow check in Bordeaux for RxD fifo free/used size.
61 * FIXME: this is NOT fully implemented, more work should be done
62 *
63 */
64
65#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
66
67#include "tehuti.h"
68
69static const struct pci_device_id bdx_pci_tbl[] = {
70 { PCI_VDEVICE(TEHUTI, 0x3009), },
71 { PCI_VDEVICE(TEHUTI, 0x3010), },
72 { PCI_VDEVICE(TEHUTI, 0x3014), },
73 { 0 }
74};
75
76MODULE_DEVICE_TABLE(pci, bdx_pci_tbl);
77
78/* Definitions needed by ISR or NAPI functions */
79static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f);
80static void bdx_tx_cleanup(struct bdx_priv *priv);
81static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget);
82
83/* Definitions needed by FW loading */
84static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size);
85
86/* Definitions needed by hw_start */
87static int bdx_tx_init(struct bdx_priv *priv);
88static int bdx_rx_init(struct bdx_priv *priv);
89
90/* Definitions needed by bdx_close */
91static void bdx_rx_free(struct bdx_priv *priv);
92static void bdx_tx_free(struct bdx_priv *priv);
93
94/* Definitions needed by bdx_probe */
95static void bdx_set_ethtool_ops(struct net_device *netdev);
96
97/*************************************************************************
98 * Print Info *
99 *************************************************************************/
100
101static void print_hw_id(struct pci_dev *pdev)
102{
103 struct pci_nic *nic = pci_get_drvdata(pdev);
104 u16 pci_link_status = 0;
105 u16 pci_ctrl = 0;
106
107 pci_read_config_word(pdev, PCI_LINK_STATUS_REG, &pci_link_status);
108 pci_read_config_word(pdev, PCI_DEV_CTRL_REG, &pci_ctrl);
109
110 pr_info("%s%s\n", BDX_NIC_NAME,
111 nic->port_num == 1 ? "" : ", 2-Port");
112 pr_info("srom 0x%x fpga %d build %u lane# %d max_pl 0x%x mrrs 0x%x\n",
113 readl(nic->regs + SROM_VER), readl(nic->regs + FPGA_VER) & 0xFFF,
114 readl(nic->regs + FPGA_SEED),
115 GET_LINK_STATUS_LANES(pci_link_status),
116 GET_DEV_CTRL_MAXPL(pci_ctrl), GET_DEV_CTRL_MRRS(pci_ctrl));
117}
118
119static void print_fw_id(struct pci_nic *nic)
120{
121 pr_info("fw 0x%x\n", readl(nic->regs + FW_VER));
122}
123
124static void print_eth_id(struct net_device *ndev)
125{
126 netdev_info(ndev, "%s, Port %c\n",
127 BDX_NIC_NAME, (ndev->if_port == 0) ? 'A' : 'B');
128
129}
130
131/*************************************************************************
132 * Code *
133 *************************************************************************/
134
135#define bdx_enable_interrupts(priv) \
136 do { WRITE_REG(priv, regIMR, IR_RUN); } while (0)
137#define bdx_disable_interrupts(priv) \
138 do { WRITE_REG(priv, regIMR, 0); } while (0)
139
140/**
141 * bdx_fifo_init - create TX/RX descriptor fifo for host-NIC communication.
142 * @priv: NIC private structure
143 * @f: fifo to initialize
144 * @fsz_type: fifo size type: 0-4KB, 1-8KB, 2-16KB, 3-32KB
145 * @reg_XXX: offsets of registers relative to base address
146 *
147 * 1K extra space is allocated at the end of the fifo to simplify
148 * processing of descriptors that wraps around fifo's end
149 *
150 * Returns 0 on success, negative value on failure
151 *
152 */
153static int
154bdx_fifo_init(struct bdx_priv *priv, struct fifo *f, int fsz_type,
155 u16 reg_CFG0, u16 reg_CFG1, u16 reg_RPTR, u16 reg_WPTR)
156{
157 u16 memsz = FIFO_SIZE * (1 << fsz_type);
158
159 memset(f, 0, sizeof(struct fifo));
160 /* pci_alloc_consistent gives us 4k-aligned memory */
161 f->va = pci_alloc_consistent(priv->pdev,
162 memsz + FIFO_EXTRA_SPACE, &f->da);
163 if (!f->va) {
164 pr_err("pci_alloc_consistent failed\n");
165 RET(-ENOMEM);
166 }
167 f->reg_CFG0 = reg_CFG0;
168 f->reg_CFG1 = reg_CFG1;
169 f->reg_RPTR = reg_RPTR;
170 f->reg_WPTR = reg_WPTR;
171 f->rptr = 0;
172 f->wptr = 0;
173 f->memsz = memsz;
174 f->size_mask = memsz - 1;
175 WRITE_REG(priv, reg_CFG0, (u32) ((f->da & TX_RX_CFG0_BASE) | fsz_type));
176 WRITE_REG(priv, reg_CFG1, H32_64(f->da));
177
178 RET(0);
179}
180
181/**
182 * bdx_fifo_free - free all resources used by fifo
183 * @priv: NIC private structure
184 * @f: fifo to release
185 */
186static void bdx_fifo_free(struct bdx_priv *priv, struct fifo *f)
187{
188 ENTER;
189 if (f->va) {
190 pci_free_consistent(priv->pdev,
191 f->memsz + FIFO_EXTRA_SPACE, f->va, f->da);
192 f->va = NULL;
193 }
194 RET();
195}
196
197/**
198 * bdx_link_changed - notifies OS about hw link state.
199 * @priv: hw adapter structure
200 */
201static void bdx_link_changed(struct bdx_priv *priv)
202{
203 u32 link = READ_REG(priv, regMAC_LNK_STAT) & MAC_LINK_STAT;
204
205 if (!link) {
206 if (netif_carrier_ok(priv->ndev)) {
207 netif_stop_queue(priv->ndev);
208 netif_carrier_off(priv->ndev);
209 netdev_err(priv->ndev, "Link Down\n");
210 }
211 } else {
212 if (!netif_carrier_ok(priv->ndev)) {
213 netif_wake_queue(priv->ndev);
214 netif_carrier_on(priv->ndev);
215 netdev_err(priv->ndev, "Link Up\n");
216 }
217 }
218}
219
220static void bdx_isr_extra(struct bdx_priv *priv, u32 isr)
221{
222 if (isr & IR_RX_FREE_0) {
223 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
224 DBG("RX_FREE_0\n");
225 }
226
227 if (isr & IR_LNKCHG0)
228 bdx_link_changed(priv);
229
230 if (isr & IR_PCIE_LINK)
231 netdev_err(priv->ndev, "PCI-E Link Fault\n");
232
233 if (isr & IR_PCIE_TOUT)
234 netdev_err(priv->ndev, "PCI-E Time Out\n");
235
236}
237
238/**
239 * bdx_isr_napi - Interrupt Service Routine for Bordeaux NIC
240 * @irq: interrupt number
241 * @dev: network device
242 *
243 * Return IRQ_NONE if it was not our interrupt, IRQ_HANDLED - otherwise
244 *
245 * It reads ISR register to know interrupt reasons, and proceed them one by one.
246 * Reasons of interest are:
247 * RX_DESC - new packet has arrived and RXD fifo holds its descriptor
248 * RX_FREE - number of free Rx buffers in RXF fifo gets low
249 * TX_FREE - packet was transmited and RXF fifo holds its descriptor
250 */
251
252static irqreturn_t bdx_isr_napi(int irq, void *dev)
253{
254 struct net_device *ndev = dev;
255 struct bdx_priv *priv = netdev_priv(ndev);
256 u32 isr;
257
258 ENTER;
259 isr = (READ_REG(priv, regISR) & IR_RUN);
260 if (unlikely(!isr)) {
261 bdx_enable_interrupts(priv);
262 return IRQ_NONE; /* Not our interrupt */
263 }
264
265 if (isr & IR_EXTRA)
266 bdx_isr_extra(priv, isr);
267
268 if (isr & (IR_RX_DESC_0 | IR_TX_FREE_0)) {
269 if (likely(napi_schedule_prep(&priv->napi))) {
270 __napi_schedule(&priv->napi);
271 RET(IRQ_HANDLED);
272 } else {
273 /* NOTE: we get here if intr has slipped into window
274 * between these lines in bdx_poll:
275 * bdx_enable_interrupts(priv);
276 * return 0;
277 * currently intrs are disabled (since we read ISR),
278 * and we have failed to register next poll.
279 * so we read the regs to trigger chip
280 * and allow further interupts. */
281 READ_REG(priv, regTXF_WPTR_0);
282 READ_REG(priv, regRXD_WPTR_0);
283 }
284 }
285
286 bdx_enable_interrupts(priv);
287 RET(IRQ_HANDLED);
288}
289
290static int bdx_poll(struct napi_struct *napi, int budget)
291{
292 struct bdx_priv *priv = container_of(napi, struct bdx_priv, napi);
293 int work_done;
294
295 ENTER;
296 bdx_tx_cleanup(priv);
297 work_done = bdx_rx_receive(priv, &priv->rxd_fifo0, budget);
298 if ((work_done < budget) ||
299 (priv->napi_stop++ >= 30)) {
300 DBG("rx poll is done. backing to isr-driven\n");
301
302 /* from time to time we exit to let NAPI layer release
303 * device lock and allow waiting tasks (eg rmmod) to advance) */
304 priv->napi_stop = 0;
305
306 napi_complete_done(napi, work_done);
307 bdx_enable_interrupts(priv);
308 }
309 return work_done;
310}
311
312/**
313 * bdx_fw_load - loads firmware to NIC
314 * @priv: NIC private structure
315 *
316 * Firmware is loaded via TXD fifo, so it must be initialized first.
317 * Firware must be loaded once per NIC not per PCI device provided by NIC (NIC
318 * can have few of them). So all drivers use semaphore register to choose one
319 * that will actually load FW to NIC.
320 */
321
322static int bdx_fw_load(struct bdx_priv *priv)
323{
324 const struct firmware *fw = NULL;
325 int master, i;
326 int rc;
327
328 ENTER;
329 master = READ_REG(priv, regINIT_SEMAPHORE);
330 if (!READ_REG(priv, regINIT_STATUS) && master) {
331 rc = request_firmware(&fw, "tehuti/bdx.bin", &priv->pdev->dev);
332 if (rc)
333 goto out;
334 bdx_tx_push_desc_safe(priv, (char *)fw->data, fw->size);
335 mdelay(100);
336 }
337 for (i = 0; i < 200; i++) {
338 if (READ_REG(priv, regINIT_STATUS)) {
339 rc = 0;
340 goto out;
341 }
342 mdelay(2);
343 }
344 rc = -EIO;
345out:
346 if (master)
347 WRITE_REG(priv, regINIT_SEMAPHORE, 1);
348
349 release_firmware(fw);
350
351 if (rc) {
352 netdev_err(priv->ndev, "firmware loading failed\n");
353 if (rc == -EIO)
354 DBG("VPC = 0x%x VIC = 0x%x INIT_STATUS = 0x%x i=%d\n",
355 READ_REG(priv, regVPC),
356 READ_REG(priv, regVIC),
357 READ_REG(priv, regINIT_STATUS), i);
358 RET(rc);
359 } else {
360 DBG("%s: firmware loading success\n", priv->ndev->name);
361 RET(0);
362 }
363}
364
365static void bdx_restore_mac(struct net_device *ndev, struct bdx_priv *priv)
366{
367 u32 val;
368
369 ENTER;
370 DBG("mac0=%x mac1=%x mac2=%x\n",
371 READ_REG(priv, regUNC_MAC0_A),
372 READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
373
374 val = (ndev->dev_addr[0] << 8) | (ndev->dev_addr[1]);
375 WRITE_REG(priv, regUNC_MAC2_A, val);
376 val = (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]);
377 WRITE_REG(priv, regUNC_MAC1_A, val);
378 val = (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]);
379 WRITE_REG(priv, regUNC_MAC0_A, val);
380
381 DBG("mac0=%x mac1=%x mac2=%x\n",
382 READ_REG(priv, regUNC_MAC0_A),
383 READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
384 RET();
385}
386
387/**
388 * bdx_hw_start - inits registers and starts HW's Rx and Tx engines
389 * @priv: NIC private structure
390 */
391static int bdx_hw_start(struct bdx_priv *priv)
392{
393 int rc = -EIO;
394 struct net_device *ndev = priv->ndev;
395
396 ENTER;
397 bdx_link_changed(priv);
398
399 /* 10G overall max length (vlan, eth&ip header, ip payload, crc) */
400 WRITE_REG(priv, regFRM_LENGTH, 0X3FE0);
401 WRITE_REG(priv, regPAUSE_QUANT, 0x96);
402 WRITE_REG(priv, regRX_FIFO_SECTION, 0x800010);
403 WRITE_REG(priv, regTX_FIFO_SECTION, 0xE00010);
404 WRITE_REG(priv, regRX_FULLNESS, 0);
405 WRITE_REG(priv, regTX_FULLNESS, 0);
406 WRITE_REG(priv, regCTRLST,
407 regCTRLST_BASE | regCTRLST_RX_ENA | regCTRLST_TX_ENA);
408
409 WRITE_REG(priv, regVGLB, 0);
410 WRITE_REG(priv, regMAX_FRAME_A,
411 priv->rxf_fifo0.m.pktsz & MAX_FRAME_AB_VAL);
412
413 DBG("RDINTCM=%08x\n", priv->rdintcm); /*NOTE: test script uses this */
414 WRITE_REG(priv, regRDINTCM0, priv->rdintcm);
415 WRITE_REG(priv, regRDINTCM2, 0); /*cpu_to_le32(rcm.val)); */
416
417 DBG("TDINTCM=%08x\n", priv->tdintcm); /*NOTE: test script uses this */
418 WRITE_REG(priv, regTDINTCM0, priv->tdintcm); /* old val = 0x300064 */
419
420 /* Enable timer interrupt once in 2 secs. */
421 /*WRITE_REG(priv, regGTMR0, ((GTMR_SEC * 2) & GTMR_DATA)); */
422 bdx_restore_mac(priv->ndev, priv);
423
424 WRITE_REG(priv, regGMAC_RXF_A, GMAC_RX_FILTER_OSEN |
425 GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB);
426
427#define BDX_IRQ_TYPE ((priv->nic->irq_type == IRQ_MSI) ? 0 : IRQF_SHARED)
428
429 rc = request_irq(priv->pdev->irq, bdx_isr_napi, BDX_IRQ_TYPE,
430 ndev->name, ndev);
431 if (rc)
432 goto err_irq;
433 bdx_enable_interrupts(priv);
434
435 RET(0);
436
437err_irq:
438 RET(rc);
439}
440
441static void bdx_hw_stop(struct bdx_priv *priv)
442{
443 ENTER;
444 bdx_disable_interrupts(priv);
445 free_irq(priv->pdev->irq, priv->ndev);
446
447 netif_carrier_off(priv->ndev);
448 netif_stop_queue(priv->ndev);
449
450 RET();
451}
452
453static int bdx_hw_reset_direct(void __iomem *regs)
454{
455 u32 val, i;
456 ENTER;
457
458 /* reset sequences: read, write 1, read, write 0 */
459 val = readl(regs + regCLKPLL);
460 writel((val | CLKPLL_SFTRST) + 0x8, regs + regCLKPLL);
461 udelay(50);
462 val = readl(regs + regCLKPLL);
463 writel(val & ~CLKPLL_SFTRST, regs + regCLKPLL);
464
465 /* check that the PLLs are locked and reset ended */
466 for (i = 0; i < 70; i++, mdelay(10))
467 if ((readl(regs + regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) {
468 /* do any PCI-E read transaction */
469 readl(regs + regRXD_CFG0_0);
470 return 0;
471 }
472 pr_err("HW reset failed\n");
473 return 1; /* failure */
474}
475
476static int bdx_hw_reset(struct bdx_priv *priv)
477{
478 u32 val, i;
479 ENTER;
480
481 if (priv->port == 0) {
482 /* reset sequences: read, write 1, read, write 0 */
483 val = READ_REG(priv, regCLKPLL);
484 WRITE_REG(priv, regCLKPLL, (val | CLKPLL_SFTRST) + 0x8);
485 udelay(50);
486 val = READ_REG(priv, regCLKPLL);
487 WRITE_REG(priv, regCLKPLL, val & ~CLKPLL_SFTRST);
488 }
489 /* check that the PLLs are locked and reset ended */
490 for (i = 0; i < 70; i++, mdelay(10))
491 if ((READ_REG(priv, regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) {
492 /* do any PCI-E read transaction */
493 READ_REG(priv, regRXD_CFG0_0);
494 return 0;
495 }
496 pr_err("HW reset failed\n");
497 return 1; /* failure */
498}
499
500static int bdx_sw_reset(struct bdx_priv *priv)
501{
502 int i;
503
504 ENTER;
505 /* 1. load MAC (obsolete) */
506 /* 2. disable Rx (and Tx) */
507 WRITE_REG(priv, regGMAC_RXF_A, 0);
508 mdelay(100);
509 /* 3. disable port */
510 WRITE_REG(priv, regDIS_PORT, 1);
511 /* 4. disable queue */
512 WRITE_REG(priv, regDIS_QU, 1);
513 /* 5. wait until hw is disabled */
514 for (i = 0; i < 50; i++) {
515 if (READ_REG(priv, regRST_PORT) & 1)
516 break;
517 mdelay(10);
518 }
519 if (i == 50)
520 netdev_err(priv->ndev, "SW reset timeout. continuing anyway\n");
521
522 /* 6. disable intrs */
523 WRITE_REG(priv, regRDINTCM0, 0);
524 WRITE_REG(priv, regTDINTCM0, 0);
525 WRITE_REG(priv, regIMR, 0);
526 READ_REG(priv, regISR);
527
528 /* 7. reset queue */
529 WRITE_REG(priv, regRST_QU, 1);
530 /* 8. reset port */
531 WRITE_REG(priv, regRST_PORT, 1);
532 /* 9. zero all read and write pointers */
533 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
534 DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
535 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
536 WRITE_REG(priv, i, 0);
537 /* 10. unseet port disable */
538 WRITE_REG(priv, regDIS_PORT, 0);
539 /* 11. unset queue disable */
540 WRITE_REG(priv, regDIS_QU, 0);
541 /* 12. unset queue reset */
542 WRITE_REG(priv, regRST_QU, 0);
543 /* 13. unset port reset */
544 WRITE_REG(priv, regRST_PORT, 0);
545 /* 14. enable Rx */
546 /* skiped. will be done later */
547 /* 15. save MAC (obsolete) */
548 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
549 DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
550
551 RET(0);
552}
553
554/* bdx_reset - performs right type of reset depending on hw type */
555static int bdx_reset(struct bdx_priv *priv)
556{
557 ENTER;
558 RET((priv->pdev->device == 0x3009)
559 ? bdx_hw_reset(priv)
560 : bdx_sw_reset(priv));
561}
562
563/**
564 * bdx_close - Disables a network interface
565 * @netdev: network interface device structure
566 *
567 * Returns 0, this is not allowed to fail
568 *
569 * The close entry point is called when an interface is de-activated
570 * by the OS. The hardware is still under the drivers control, but
571 * needs to be disabled. A global MAC reset is issued to stop the
572 * hardware, and all transmit and receive resources are freed.
573 **/
574static int bdx_close(struct net_device *ndev)
575{
576 struct bdx_priv *priv = NULL;
577
578 ENTER;
579 priv = netdev_priv(ndev);
580
581 napi_disable(&priv->napi);
582
583 bdx_reset(priv);
584 bdx_hw_stop(priv);
585 bdx_rx_free(priv);
586 bdx_tx_free(priv);
587 RET(0);
588}
589
590/**
591 * bdx_open - Called when a network interface is made active
592 * @netdev: network interface device structure
593 *
594 * Returns 0 on success, negative value on failure
595 *
596 * The open entry point is called when a network interface is made
597 * active by the system (IFF_UP). At this point all resources needed
598 * for transmit and receive operations are allocated, the interrupt
599 * handler is registered with the OS, the watchdog timer is started,
600 * and the stack is notified that the interface is ready.
601 **/
602static int bdx_open(struct net_device *ndev)
603{
604 struct bdx_priv *priv;
605 int rc;
606
607 ENTER;
608 priv = netdev_priv(ndev);
609 bdx_reset(priv);
610 if (netif_running(ndev))
611 netif_stop_queue(priv->ndev);
612
613 if ((rc = bdx_tx_init(priv)) ||
614 (rc = bdx_rx_init(priv)) ||
615 (rc = bdx_fw_load(priv)))
616 goto err;
617
618 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
619
620 rc = bdx_hw_start(priv);
621 if (rc)
622 goto err;
623
624 napi_enable(&priv->napi);
625
626 print_fw_id(priv->nic);
627
628 RET(0);
629
630err:
631 bdx_close(ndev);
632 RET(rc);
633}
634
635static int bdx_range_check(struct bdx_priv *priv, u32 offset)
636{
637 return (offset > (u32) (BDX_REGS_SIZE / priv->nic->port_num)) ?
638 -EINVAL : 0;
639}
640
641static int bdx_ioctl_priv(struct net_device *ndev, struct ifreq *ifr, int cmd)
642{
643 struct bdx_priv *priv = netdev_priv(ndev);
644 u32 data[3];
645 int error;
646
647 ENTER;
648
649 DBG("jiffies=%ld cmd=%d\n", jiffies, cmd);
650 if (cmd != SIOCDEVPRIVATE) {
651 error = copy_from_user(data, ifr->ifr_data, sizeof(data));
652 if (error) {
653 pr_err("can't copy from user\n");
654 RET(-EFAULT);
655 }
656 DBG("%d 0x%x 0x%x\n", data[0], data[1], data[2]);
657 } else {
658 return -EOPNOTSUPP;
659 }
660
661 if (!capable(CAP_SYS_RAWIO))
662 return -EPERM;
663
664 switch (data[0]) {
665
666 case BDX_OP_READ:
667 error = bdx_range_check(priv, data[1]);
668 if (error < 0)
669 return error;
670 data[2] = READ_REG(priv, data[1]);
671 DBG("read_reg(0x%x)=0x%x (dec %d)\n", data[1], data[2],
672 data[2]);
673 error = copy_to_user(ifr->ifr_data, data, sizeof(data));
674 if (error)
675 RET(-EFAULT);
676 break;
677
678 case BDX_OP_WRITE:
679 error = bdx_range_check(priv, data[1]);
680 if (error < 0)
681 return error;
682 WRITE_REG(priv, data[1], data[2]);
683 DBG("write_reg(0x%x, 0x%x)\n", data[1], data[2]);
684 break;
685
686 default:
687 RET(-EOPNOTSUPP);
688 }
689 return 0;
690}
691
692static int bdx_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd)
693{
694 ENTER;
695 if (cmd >= SIOCDEVPRIVATE && cmd <= (SIOCDEVPRIVATE + 15))
696 RET(bdx_ioctl_priv(ndev, ifr, cmd));
697 else
698 RET(-EOPNOTSUPP);
699}
700
701/**
702 * __bdx_vlan_rx_vid - private helper for adding/killing VLAN vid
703 * @ndev: network device
704 * @vid: VLAN vid
705 * @op: add or kill operation
706 *
707 * Passes VLAN filter table to hardware
708 */
709static void __bdx_vlan_rx_vid(struct net_device *ndev, uint16_t vid, int enable)
710{
711 struct bdx_priv *priv = netdev_priv(ndev);
712 u32 reg, bit, val;
713
714 ENTER;
715 DBG2("vid=%d value=%d\n", (int)vid, enable);
716 if (unlikely(vid >= 4096)) {
717 pr_err("invalid VID: %u (> 4096)\n", vid);
718 RET();
719 }
720 reg = regVLAN_0 + (vid / 32) * 4;
721 bit = 1 << vid % 32;
722 val = READ_REG(priv, reg);
723 DBG2("reg=%x, val=%x, bit=%d\n", reg, val, bit);
724 if (enable)
725 val |= bit;
726 else
727 val &= ~bit;
728 DBG2("new val %x\n", val);
729 WRITE_REG(priv, reg, val);
730 RET();
731}
732
733/**
734 * bdx_vlan_rx_add_vid - kernel hook for adding VLAN vid to hw filtering table
735 * @ndev: network device
736 * @vid: VLAN vid to add
737 */
738static int bdx_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)
739{
740 __bdx_vlan_rx_vid(ndev, vid, 1);
741 return 0;
742}
743
744/**
745 * bdx_vlan_rx_kill_vid - kernel hook for killing VLAN vid in hw filtering table
746 * @ndev: network device
747 * @vid: VLAN vid to kill
748 */
749static int bdx_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid)
750{
751 __bdx_vlan_rx_vid(ndev, vid, 0);
752 return 0;
753}
754
755/**
756 * bdx_change_mtu - Change the Maximum Transfer Unit
757 * @netdev: network interface device structure
758 * @new_mtu: new value for maximum frame size
759 *
760 * Returns 0 on success, negative on failure
761 */
762static int bdx_change_mtu(struct net_device *ndev, int new_mtu)
763{
764 ENTER;
765
766 ndev->mtu = new_mtu;
767 if (netif_running(ndev)) {
768 bdx_close(ndev);
769 bdx_open(ndev);
770 }
771 RET(0);
772}
773
774static void bdx_setmulti(struct net_device *ndev)
775{
776 struct bdx_priv *priv = netdev_priv(ndev);
777
778 u32 rxf_val =
779 GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB | GMAC_RX_FILTER_OSEN;
780 int i;
781
782 ENTER;
783 /* IMF - imperfect (hash) rx multicat filter */
784 /* PMF - perfect rx multicat filter */
785
786 /* FIXME: RXE(OFF) */
787 if (ndev->flags & IFF_PROMISC) {
788 rxf_val |= GMAC_RX_FILTER_PRM;
789 } else if (ndev->flags & IFF_ALLMULTI) {
790 /* set IMF to accept all multicast frmaes */
791 for (i = 0; i < MAC_MCST_HASH_NUM; i++)
792 WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, ~0);
793 } else if (!netdev_mc_empty(ndev)) {
794 u8 hash;
795 struct netdev_hw_addr *ha;
796 u32 reg, val;
797
798 /* set IMF to deny all multicast frames */
799 for (i = 0; i < MAC_MCST_HASH_NUM; i++)
800 WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, 0);
801 /* set PMF to deny all multicast frames */
802 for (i = 0; i < MAC_MCST_NUM; i++) {
803 WRITE_REG(priv, regRX_MAC_MCST0 + i * 8, 0);
804 WRITE_REG(priv, regRX_MAC_MCST1 + i * 8, 0);
805 }
806
807 /* use PMF to accept first MAC_MCST_NUM (15) addresses */
808 /* TBD: sort addresses and write them in ascending order
809 * into RX_MAC_MCST regs. we skip this phase now and accept ALL
810 * multicast frames throu IMF */
811 /* accept the rest of addresses throu IMF */
812 netdev_for_each_mc_addr(ha, ndev) {
813 hash = 0;
814 for (i = 0; i < ETH_ALEN; i++)
815 hash ^= ha->addr[i];
816 reg = regRX_MCST_HASH0 + ((hash >> 5) << 2);
817 val = READ_REG(priv, reg);
818 val |= (1 << (hash % 32));
819 WRITE_REG(priv, reg, val);
820 }
821
822 } else {
823 DBG("only own mac %d\n", netdev_mc_count(ndev));
824 rxf_val |= GMAC_RX_FILTER_AB;
825 }
826 WRITE_REG(priv, regGMAC_RXF_A, rxf_val);
827 /* enable RX */
828 /* FIXME: RXE(ON) */
829 RET();
830}
831
832static int bdx_set_mac(struct net_device *ndev, void *p)
833{
834 struct bdx_priv *priv = netdev_priv(ndev);
835 struct sockaddr *addr = p;
836
837 ENTER;
838 /*
839 if (netif_running(dev))
840 return -EBUSY
841 */
842 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
843 bdx_restore_mac(ndev, priv);
844 RET(0);
845}
846
847static int bdx_read_mac(struct bdx_priv *priv)
848{
849 u16 macAddress[3], i;
850 ENTER;
851
852 macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
853 macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
854 macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
855 macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
856 macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
857 macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
858 for (i = 0; i < 3; i++) {
859 priv->ndev->dev_addr[i * 2 + 1] = macAddress[i];
860 priv->ndev->dev_addr[i * 2] = macAddress[i] >> 8;
861 }
862 RET(0);
863}
864
865static u64 bdx_read_l2stat(struct bdx_priv *priv, int reg)
866{
867 u64 val;
868
869 val = READ_REG(priv, reg);
870 val |= ((u64) READ_REG(priv, reg + 8)) << 32;
871 return val;
872}
873
874/*Do the statistics-update work*/
875static void bdx_update_stats(struct bdx_priv *priv)
876{
877 struct bdx_stats *stats = &priv->hw_stats;
878 u64 *stats_vector = (u64 *) stats;
879 int i;
880 int addr;
881
882 /*Fill HW structure */
883 addr = 0x7200;
884 /*First 12 statistics - 0x7200 - 0x72B0 */
885 for (i = 0; i < 12; i++) {
886 stats_vector[i] = bdx_read_l2stat(priv, addr);
887 addr += 0x10;
888 }
889 BDX_ASSERT(addr != 0x72C0);
890 /* 0x72C0-0x72E0 RSRV */
891 addr = 0x72F0;
892 for (; i < 16; i++) {
893 stats_vector[i] = bdx_read_l2stat(priv, addr);
894 addr += 0x10;
895 }
896 BDX_ASSERT(addr != 0x7330);
897 /* 0x7330-0x7360 RSRV */
898 addr = 0x7370;
899 for (; i < 19; i++) {
900 stats_vector[i] = bdx_read_l2stat(priv, addr);
901 addr += 0x10;
902 }
903 BDX_ASSERT(addr != 0x73A0);
904 /* 0x73A0-0x73B0 RSRV */
905 addr = 0x73C0;
906 for (; i < 23; i++) {
907 stats_vector[i] = bdx_read_l2stat(priv, addr);
908 addr += 0x10;
909 }
910 BDX_ASSERT(addr != 0x7400);
911 BDX_ASSERT((sizeof(struct bdx_stats) / sizeof(u64)) != i);
912}
913
914static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len,
915 u16 rxd_vlan);
916static void print_rxfd(struct rxf_desc *rxfd);
917
918/*************************************************************************
919 * Rx DB *
920 *************************************************************************/
921
922static void bdx_rxdb_destroy(struct rxdb *db)
923{
924 vfree(db);
925}
926
927static struct rxdb *bdx_rxdb_create(int nelem)
928{
929 struct rxdb *db;
930 int i;
931
932 db = vmalloc(sizeof(struct rxdb)
933 + (nelem * sizeof(int))
934 + (nelem * sizeof(struct rx_map)));
935 if (likely(db != NULL)) {
936 db->stack = (int *)(db + 1);
937 db->elems = (void *)(db->stack + nelem);
938 db->nelem = nelem;
939 db->top = nelem;
940 for (i = 0; i < nelem; i++)
941 db->stack[i] = nelem - i - 1; /* to make first allocs
942 close to db struct*/
943 }
944
945 return db;
946}
947
948static inline int bdx_rxdb_alloc_elem(struct rxdb *db)
949{
950 BDX_ASSERT(db->top <= 0);
951 return db->stack[--(db->top)];
952}
953
954static inline void *bdx_rxdb_addr_elem(struct rxdb *db, int n)
955{
956 BDX_ASSERT((n < 0) || (n >= db->nelem));
957 return db->elems + n;
958}
959
960static inline int bdx_rxdb_available(struct rxdb *db)
961{
962 return db->top;
963}
964
965static inline void bdx_rxdb_free_elem(struct rxdb *db, int n)
966{
967 BDX_ASSERT((n >= db->nelem) || (n < 0));
968 db->stack[(db->top)++] = n;
969}
970
971/*************************************************************************
972 * Rx Init *
973 *************************************************************************/
974
975/**
976 * bdx_rx_init - initialize RX all related HW and SW resources
977 * @priv: NIC private structure
978 *
979 * Returns 0 on success, negative value on failure
980 *
981 * It creates rxf and rxd fifos, update relevant HW registers, preallocate
982 * skb for rx. It assumes that Rx is desabled in HW
983 * funcs are grouped for better cache usage
984 *
985 * RxD fifo is smaller than RxF fifo by design. Upon high load, RxD will be
986 * filled and packets will be dropped by nic without getting into host or
987 * cousing interrupt. Anyway, in that condition, host has no chance to process
988 * all packets, but dropping in nic is cheaper, since it takes 0 cpu cycles
989 */
990
991/* TBD: ensure proper packet size */
992
993static int bdx_rx_init(struct bdx_priv *priv)
994{
995 ENTER;
996
997 if (bdx_fifo_init(priv, &priv->rxd_fifo0.m, priv->rxd_size,
998 regRXD_CFG0_0, regRXD_CFG1_0,
999 regRXD_RPTR_0, regRXD_WPTR_0))
1000 goto err_mem;
1001 if (bdx_fifo_init(priv, &priv->rxf_fifo0.m, priv->rxf_size,
1002 regRXF_CFG0_0, regRXF_CFG1_0,
1003 regRXF_RPTR_0, regRXF_WPTR_0))
1004 goto err_mem;
1005 priv->rxdb = bdx_rxdb_create(priv->rxf_fifo0.m.memsz /
1006 sizeof(struct rxf_desc));
1007 if (!priv->rxdb)
1008 goto err_mem;
1009
1010 priv->rxf_fifo0.m.pktsz = priv->ndev->mtu + VLAN_ETH_HLEN;
1011 return 0;
1012
1013err_mem:
1014 netdev_err(priv->ndev, "Rx init failed\n");
1015 return -ENOMEM;
1016}
1017
1018/**
1019 * bdx_rx_free_skbs - frees and unmaps all skbs allocated for the fifo
1020 * @priv: NIC private structure
1021 * @f: RXF fifo
1022 */
1023static void bdx_rx_free_skbs(struct bdx_priv *priv, struct rxf_fifo *f)
1024{
1025 struct rx_map *dm;
1026 struct rxdb *db = priv->rxdb;
1027 u16 i;
1028
1029 ENTER;
1030 DBG("total=%d free=%d busy=%d\n", db->nelem, bdx_rxdb_available(db),
1031 db->nelem - bdx_rxdb_available(db));
1032 while (bdx_rxdb_available(db) > 0) {
1033 i = bdx_rxdb_alloc_elem(db);
1034 dm = bdx_rxdb_addr_elem(db, i);
1035 dm->dma = 0;
1036 }
1037 for (i = 0; i < db->nelem; i++) {
1038 dm = bdx_rxdb_addr_elem(db, i);
1039 if (dm->dma) {
1040 pci_unmap_single(priv->pdev,
1041 dm->dma, f->m.pktsz,
1042 PCI_DMA_FROMDEVICE);
1043 dev_kfree_skb(dm->skb);
1044 }
1045 }
1046}
1047
1048/**
1049 * bdx_rx_free - release all Rx resources
1050 * @priv: NIC private structure
1051 *
1052 * It assumes that Rx is desabled in HW
1053 */
1054static void bdx_rx_free(struct bdx_priv *priv)
1055{
1056 ENTER;
1057 if (priv->rxdb) {
1058 bdx_rx_free_skbs(priv, &priv->rxf_fifo0);
1059 bdx_rxdb_destroy(priv->rxdb);
1060 priv->rxdb = NULL;
1061 }
1062 bdx_fifo_free(priv, &priv->rxf_fifo0.m);
1063 bdx_fifo_free(priv, &priv->rxd_fifo0.m);
1064
1065 RET();
1066}
1067
1068/*************************************************************************
1069 * Rx Engine *
1070 *************************************************************************/
1071
1072/**
1073 * bdx_rx_alloc_skbs - fill rxf fifo with new skbs
1074 * @priv: nic's private structure
1075 * @f: RXF fifo that needs skbs
1076 *
1077 * It allocates skbs, build rxf descs and push it (rxf descr) into rxf fifo.
1078 * skb's virtual and physical addresses are stored in skb db.
1079 * To calculate free space, func uses cached values of RPTR and WPTR
1080 * When needed, it also updates RPTR and WPTR.
1081 */
1082
1083/* TBD: do not update WPTR if no desc were written */
1084
1085static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f)
1086{
1087 struct sk_buff *skb;
1088 struct rxf_desc *rxfd;
1089 struct rx_map *dm;
1090 int dno, delta, idx;
1091 struct rxdb *db = priv->rxdb;
1092
1093 ENTER;
1094 dno = bdx_rxdb_available(db) - 1;
1095 while (dno > 0) {
1096 skb = netdev_alloc_skb(priv->ndev, f->m.pktsz + NET_IP_ALIGN);
1097 if (!skb)
1098 break;
1099
1100 skb_reserve(skb, NET_IP_ALIGN);
1101
1102 idx = bdx_rxdb_alloc_elem(db);
1103 dm = bdx_rxdb_addr_elem(db, idx);
1104 dm->dma = pci_map_single(priv->pdev,
1105 skb->data, f->m.pktsz,
1106 PCI_DMA_FROMDEVICE);
1107 dm->skb = skb;
1108 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1109 rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */
1110 rxfd->va_lo = idx;
1111 rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma));
1112 rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma));
1113 rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz);
1114 print_rxfd(rxfd);
1115
1116 f->m.wptr += sizeof(struct rxf_desc);
1117 delta = f->m.wptr - f->m.memsz;
1118 if (unlikely(delta >= 0)) {
1119 f->m.wptr = delta;
1120 if (delta > 0) {
1121 memcpy(f->m.va, f->m.va + f->m.memsz, delta);
1122 DBG("wrapped descriptor\n");
1123 }
1124 }
1125 dno--;
1126 }
1127 /*TBD: to do - delayed rxf wptr like in txd */
1128 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1129 RET();
1130}
1131
1132static inline void
1133NETIF_RX_MUX(struct bdx_priv *priv, u32 rxd_val1, u16 rxd_vlan,
1134 struct sk_buff *skb)
1135{
1136 ENTER;
1137 DBG("rxdd->flags.bits.vtag=%d\n", GET_RXD_VTAG(rxd_val1));
1138 if (GET_RXD_VTAG(rxd_val1)) {
1139 DBG("%s: vlan rcv vlan '%x' vtag '%x'\n",
1140 priv->ndev->name,
1141 GET_RXD_VLAN_ID(rxd_vlan),
1142 GET_RXD_VTAG(rxd_val1));
1143 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), GET_RXD_VLAN_TCI(rxd_vlan));
1144 }
1145 netif_receive_skb(skb);
1146}
1147
1148static void bdx_recycle_skb(struct bdx_priv *priv, struct rxd_desc *rxdd)
1149{
1150 struct rxf_desc *rxfd;
1151 struct rx_map *dm;
1152 struct rxf_fifo *f;
1153 struct rxdb *db;
1154 struct sk_buff *skb;
1155 int delta;
1156
1157 ENTER;
1158 DBG("priv=%p rxdd=%p\n", priv, rxdd);
1159 f = &priv->rxf_fifo0;
1160 db = priv->rxdb;
1161 DBG("db=%p f=%p\n", db, f);
1162 dm = bdx_rxdb_addr_elem(db, rxdd->va_lo);
1163 DBG("dm=%p\n", dm);
1164 skb = dm->skb;
1165 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1166 rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */
1167 rxfd->va_lo = rxdd->va_lo;
1168 rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma));
1169 rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma));
1170 rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz);
1171 print_rxfd(rxfd);
1172
1173 f->m.wptr += sizeof(struct rxf_desc);
1174 delta = f->m.wptr - f->m.memsz;
1175 if (unlikely(delta >= 0)) {
1176 f->m.wptr = delta;
1177 if (delta > 0) {
1178 memcpy(f->m.va, f->m.va + f->m.memsz, delta);
1179 DBG("wrapped descriptor\n");
1180 }
1181 }
1182 RET();
1183}
1184
1185/**
1186 * bdx_rx_receive - receives full packets from RXD fifo and pass them to OS
1187 * NOTE: a special treatment is given to non-continuous descriptors
1188 * that start near the end, wraps around and continue at the beginning. a second
1189 * part is copied right after the first, and then descriptor is interpreted as
1190 * normal. fifo has an extra space to allow such operations
1191 * @priv: nic's private structure
1192 * @f: RXF fifo that needs skbs
1193 * @budget: maximum number of packets to receive
1194 */
1195
1196/* TBD: replace memcpy func call by explicite inline asm */
1197
1198static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget)
1199{
1200 struct net_device *ndev = priv->ndev;
1201 struct sk_buff *skb, *skb2;
1202 struct rxd_desc *rxdd;
1203 struct rx_map *dm;
1204 struct rxf_fifo *rxf_fifo;
1205 int tmp_len, size;
1206 int done = 0;
1207 int max_done = BDX_MAX_RX_DONE;
1208 struct rxdb *db = NULL;
1209 /* Unmarshalled descriptor - copy of descriptor in host order */
1210 u32 rxd_val1;
1211 u16 len;
1212 u16 rxd_vlan;
1213
1214 ENTER;
1215 max_done = budget;
1216
1217 f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_WR_PTR;
1218
1219 size = f->m.wptr - f->m.rptr;
1220 if (size < 0)
1221 size = f->m.memsz + size; /* size is negative :-) */
1222
1223 while (size > 0) {
1224
1225 rxdd = (struct rxd_desc *)(f->m.va + f->m.rptr);
1226 rxd_val1 = CPU_CHIP_SWAP32(rxdd->rxd_val1);
1227
1228 len = CPU_CHIP_SWAP16(rxdd->len);
1229
1230 rxd_vlan = CPU_CHIP_SWAP16(rxdd->rxd_vlan);
1231
1232 print_rxdd(rxdd, rxd_val1, len, rxd_vlan);
1233
1234 tmp_len = GET_RXD_BC(rxd_val1) << 3;
1235 BDX_ASSERT(tmp_len <= 0);
1236 size -= tmp_len;
1237 if (size < 0) /* test for partially arrived descriptor */
1238 break;
1239
1240 f->m.rptr += tmp_len;
1241
1242 tmp_len = f->m.rptr - f->m.memsz;
1243 if (unlikely(tmp_len >= 0)) {
1244 f->m.rptr = tmp_len;
1245 if (tmp_len > 0) {
1246 DBG("wrapped desc rptr=%d tmp_len=%d\n",
1247 f->m.rptr, tmp_len);
1248 memcpy(f->m.va + f->m.memsz, f->m.va, tmp_len);
1249 }
1250 }
1251
1252 if (unlikely(GET_RXD_ERR(rxd_val1))) {
1253 DBG("rxd_err = 0x%x\n", GET_RXD_ERR(rxd_val1));
1254 ndev->stats.rx_errors++;
1255 bdx_recycle_skb(priv, rxdd);
1256 continue;
1257 }
1258
1259 rxf_fifo = &priv->rxf_fifo0;
1260 db = priv->rxdb;
1261 dm = bdx_rxdb_addr_elem(db, rxdd->va_lo);
1262 skb = dm->skb;
1263
1264 if (len < BDX_COPYBREAK &&
1265 (skb2 = netdev_alloc_skb(priv->ndev, len + NET_IP_ALIGN))) {
1266 skb_reserve(skb2, NET_IP_ALIGN);
1267 /*skb_put(skb2, len); */
1268 pci_dma_sync_single_for_cpu(priv->pdev,
1269 dm->dma, rxf_fifo->m.pktsz,
1270 PCI_DMA_FROMDEVICE);
1271 memcpy(skb2->data, skb->data, len);
1272 bdx_recycle_skb(priv, rxdd);
1273 skb = skb2;
1274 } else {
1275 pci_unmap_single(priv->pdev,
1276 dm->dma, rxf_fifo->m.pktsz,
1277 PCI_DMA_FROMDEVICE);
1278 bdx_rxdb_free_elem(db, rxdd->va_lo);
1279 }
1280
1281 ndev->stats.rx_bytes += len;
1282
1283 skb_put(skb, len);
1284 skb->protocol = eth_type_trans(skb, ndev);
1285
1286 /* Non-IP packets aren't checksum-offloaded */
1287 if (GET_RXD_PKT_ID(rxd_val1) == 0)
1288 skb_checksum_none_assert(skb);
1289 else
1290 skb->ip_summed = CHECKSUM_UNNECESSARY;
1291
1292 NETIF_RX_MUX(priv, rxd_val1, rxd_vlan, skb);
1293
1294 if (++done >= max_done)
1295 break;
1296 }
1297
1298 ndev->stats.rx_packets += done;
1299
1300 /* FIXME: do smth to minimize pci accesses */
1301 WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
1302
1303 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
1304
1305 RET(done);
1306}
1307
1308/*************************************************************************
1309 * Debug / Temprorary Code *
1310 *************************************************************************/
1311static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len,
1312 u16 rxd_vlan)
1313{
1314 DBG("ERROR: rxdd bc %d rxfq %d to %d type %d err %d rxp %d pkt_id %d vtag %d len %d vlan_id %d cfi %d prio %d va_lo %d va_hi %d\n",
1315 GET_RXD_BC(rxd_val1), GET_RXD_RXFQ(rxd_val1), GET_RXD_TO(rxd_val1),
1316 GET_RXD_TYPE(rxd_val1), GET_RXD_ERR(rxd_val1),
1317 GET_RXD_RXP(rxd_val1), GET_RXD_PKT_ID(rxd_val1),
1318 GET_RXD_VTAG(rxd_val1), len, GET_RXD_VLAN_ID(rxd_vlan),
1319 GET_RXD_CFI(rxd_vlan), GET_RXD_PRIO(rxd_vlan), rxdd->va_lo,
1320 rxdd->va_hi);
1321}
1322
1323static void print_rxfd(struct rxf_desc *rxfd)
1324{
1325 DBG("=== RxF desc CHIP ORDER/ENDIANNESS =============\n"
1326 "info 0x%x va_lo %u pa_lo 0x%x pa_hi 0x%x len 0x%x\n",
1327 rxfd->info, rxfd->va_lo, rxfd->pa_lo, rxfd->pa_hi, rxfd->len);
1328}
1329
1330/*
1331 * TX HW/SW interaction overview
1332 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1333 * There are 2 types of TX communication channels between driver and NIC.
1334 * 1) TX Free Fifo - TXF - holds ack descriptors for sent packets
1335 * 2) TX Data Fifo - TXD - holds descriptors of full buffers.
1336 *
1337 * Currently NIC supports TSO, checksuming and gather DMA
1338 * UFO and IP fragmentation is on the way
1339 *
1340 * RX SW Data Structures
1341 * ~~~~~~~~~~~~~~~~~~~~~
1342 * txdb - used to keep track of all skbs owned by SW and their dma addresses.
1343 * For TX case, ownership lasts from geting packet via hard_xmit and until HW
1344 * acknowledges sent by TXF descriptors.
1345 * Implemented as cyclic buffer.
1346 * fifo - keeps info about fifo's size and location, relevant HW registers,
1347 * usage and skb db. Each RXD and RXF Fifo has its own fifo structure.
1348 * Implemented as simple struct.
1349 *
1350 * TX SW Execution Flow
1351 * ~~~~~~~~~~~~~~~~~~~~
1352 * OS calls driver's hard_xmit method with packet to sent.
1353 * Driver creates DMA mappings, builds TXD descriptors and kicks HW
1354 * by updating TXD WPTR.
1355 * When packet is sent, HW write us TXF descriptor and SW frees original skb.
1356 * To prevent TXD fifo overflow without reading HW registers every time,
1357 * SW deploys "tx level" technique.
1358 * Upon strart up, tx level is initialized to TXD fifo length.
1359 * For every sent packet, SW gets its TXD descriptor sizei
1360 * (from precalculated array) and substructs it from tx level.
1361 * The size is also stored in txdb. When TXF ack arrives, SW fetch size of
1362 * original TXD descriptor from txdb and adds it to tx level.
1363 * When Tx level drops under some predefined treshhold, the driver
1364 * stops the TX queue. When TX level rises above that level,
1365 * the tx queue is enabled again.
1366 *
1367 * This technique avoids eccessive reading of RPTR and WPTR registers.
1368 * As our benchmarks shows, it adds 1.5 Gbit/sec to NIS's throuput.
1369 */
1370
1371/*************************************************************************
1372 * Tx DB *
1373 *************************************************************************/
1374static inline int bdx_tx_db_size(struct txdb *db)
1375{
1376 int taken = db->wptr - db->rptr;
1377 if (taken < 0)
1378 taken = db->size + 1 + taken; /* (size + 1) equals memsz */
1379
1380 return db->size - taken;
1381}
1382
1383/**
1384 * __bdx_tx_db_ptr_next - helper function, increment read/write pointer + wrap
1385 * @db: tx data base
1386 * @pptr: read or write pointer
1387 */
1388static inline void __bdx_tx_db_ptr_next(struct txdb *db, struct tx_map **pptr)
1389{
1390 BDX_ASSERT(db == NULL || pptr == NULL); /* sanity */
1391
1392 BDX_ASSERT(*pptr != db->rptr && /* expect either read */
1393 *pptr != db->wptr); /* or write pointer */
1394
1395 BDX_ASSERT(*pptr < db->start || /* pointer has to be */
1396 *pptr >= db->end); /* in range */
1397
1398 ++*pptr;
1399 if (unlikely(*pptr == db->end))
1400 *pptr = db->start;
1401}
1402
1403/**
1404 * bdx_tx_db_inc_rptr - increment read pointer
1405 * @db: tx data base
1406 */
1407static inline void bdx_tx_db_inc_rptr(struct txdb *db)
1408{
1409 BDX_ASSERT(db->rptr == db->wptr); /* can't read from empty db */
1410 __bdx_tx_db_ptr_next(db, &db->rptr);
1411}
1412
1413/**
1414 * bdx_tx_db_inc_wptr - increment write pointer
1415 * @db: tx data base
1416 */
1417static inline void bdx_tx_db_inc_wptr(struct txdb *db)
1418{
1419 __bdx_tx_db_ptr_next(db, &db->wptr);
1420 BDX_ASSERT(db->rptr == db->wptr); /* we can not get empty db as
1421 a result of write */
1422}
1423
1424/**
1425 * bdx_tx_db_init - creates and initializes tx db
1426 * @d: tx data base
1427 * @sz_type: size of tx fifo
1428 *
1429 * Returns 0 on success, error code otherwise
1430 */
1431static int bdx_tx_db_init(struct txdb *d, int sz_type)
1432{
1433 int memsz = FIFO_SIZE * (1 << (sz_type + 1));
1434
1435 d->start = vmalloc(memsz);
1436 if (!d->start)
1437 return -ENOMEM;
1438
1439 /*
1440 * In order to differentiate between db is empty and db is full
1441 * states at least one element should always be empty in order to
1442 * avoid rptr == wptr which means db is empty
1443 */
1444 d->size = memsz / sizeof(struct tx_map) - 1;
1445 d->end = d->start + d->size + 1; /* just after last element */
1446
1447 /* all dbs are created equally empty */
1448 d->rptr = d->start;
1449 d->wptr = d->start;
1450
1451 return 0;
1452}
1453
1454/**
1455 * bdx_tx_db_close - closes tx db and frees all memory
1456 * @d: tx data base
1457 */
1458static void bdx_tx_db_close(struct txdb *d)
1459{
1460 BDX_ASSERT(d == NULL);
1461
1462 vfree(d->start);
1463 d->start = NULL;
1464}
1465
1466/*************************************************************************
1467 * Tx Engine *
1468 *************************************************************************/
1469
1470/* sizes of tx desc (including padding if needed) as function
1471 * of skb's frag number */
1472static struct {
1473 u16 bytes;
1474 u16 qwords; /* qword = 64 bit */
1475} txd_sizes[MAX_SKB_FRAGS + 1];
1476
1477/**
1478 * bdx_tx_map_skb - creates and stores dma mappings for skb's data blocks
1479 * @priv: NIC private structure
1480 * @skb: socket buffer to map
1481 * @txdd: TX descriptor to use
1482 *
1483 * It makes dma mappings for skb's data blocks and writes them to PBL of
1484 * new tx descriptor. It also stores them in the tx db, so they could be
1485 * unmaped after data was sent. It is reponsibility of a caller to make
1486 * sure that there is enough space in the tx db. Last element holds pointer
1487 * to skb itself and marked with zero length
1488 */
1489static inline void
1490bdx_tx_map_skb(struct bdx_priv *priv, struct sk_buff *skb,
1491 struct txd_desc *txdd)
1492{
1493 struct txdb *db = &priv->txdb;
1494 struct pbl *pbl = &txdd->pbl[0];
1495 int nr_frags = skb_shinfo(skb)->nr_frags;
1496 int i;
1497
1498 db->wptr->len = skb_headlen(skb);
1499 db->wptr->addr.dma = pci_map_single(priv->pdev, skb->data,
1500 db->wptr->len, PCI_DMA_TODEVICE);
1501 pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
1502 pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
1503 pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
1504 DBG("=== pbl len: 0x%x ================\n", pbl->len);
1505 DBG("=== pbl pa_lo: 0x%x ================\n", pbl->pa_lo);
1506 DBG("=== pbl pa_hi: 0x%x ================\n", pbl->pa_hi);
1507 bdx_tx_db_inc_wptr(db);
1508
1509 for (i = 0; i < nr_frags; i++) {
1510 const struct skb_frag_struct *frag;
1511
1512 frag = &skb_shinfo(skb)->frags[i];
1513 db->wptr->len = skb_frag_size(frag);
1514 db->wptr->addr.dma = skb_frag_dma_map(&priv->pdev->dev, frag,
1515 0, skb_frag_size(frag),
1516 DMA_TO_DEVICE);
1517
1518 pbl++;
1519 pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
1520 pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
1521 pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
1522 bdx_tx_db_inc_wptr(db);
1523 }
1524
1525 /* add skb clean up info. */
1526 db->wptr->len = -txd_sizes[nr_frags].bytes;
1527 db->wptr->addr.skb = skb;
1528 bdx_tx_db_inc_wptr(db);
1529}
1530
1531/* init_txd_sizes - precalculate sizes of descriptors for skbs up to 16 frags
1532 * number of frags is used as index to fetch correct descriptors size,
1533 * instead of calculating it each time */
1534static void __init init_txd_sizes(void)
1535{
1536 int i, lwords;
1537
1538 /* 7 - is number of lwords in txd with one phys buffer
1539 * 3 - is number of lwords used for every additional phys buffer */
1540 for (i = 0; i < MAX_SKB_FRAGS + 1; i++) {
1541 lwords = 7 + (i * 3);
1542 if (lwords & 1)
1543 lwords++; /* pad it with 1 lword */
1544 txd_sizes[i].qwords = lwords >> 1;
1545 txd_sizes[i].bytes = lwords << 2;
1546 }
1547}
1548
1549/* bdx_tx_init - initialize all Tx related stuff.
1550 * Namely, TXD and TXF fifos, database etc */
1551static int bdx_tx_init(struct bdx_priv *priv)
1552{
1553 if (bdx_fifo_init(priv, &priv->txd_fifo0.m, priv->txd_size,
1554 regTXD_CFG0_0,
1555 regTXD_CFG1_0, regTXD_RPTR_0, regTXD_WPTR_0))
1556 goto err_mem;
1557 if (bdx_fifo_init(priv, &priv->txf_fifo0.m, priv->txf_size,
1558 regTXF_CFG0_0,
1559 regTXF_CFG1_0, regTXF_RPTR_0, regTXF_WPTR_0))
1560 goto err_mem;
1561
1562 /* The TX db has to keep mappings for all packets sent (on TxD)
1563 * and not yet reclaimed (on TxF) */
1564 if (bdx_tx_db_init(&priv->txdb, max(priv->txd_size, priv->txf_size)))
1565 goto err_mem;
1566
1567 priv->tx_level = BDX_MAX_TX_LEVEL;
1568#ifdef BDX_DELAY_WPTR
1569 priv->tx_update_mark = priv->tx_level - 1024;
1570#endif
1571 return 0;
1572
1573err_mem:
1574 netdev_err(priv->ndev, "Tx init failed\n");
1575 return -ENOMEM;
1576}
1577
1578/**
1579 * bdx_tx_space - calculates available space in TX fifo
1580 * @priv: NIC private structure
1581 *
1582 * Returns available space in TX fifo in bytes
1583 */
1584static inline int bdx_tx_space(struct bdx_priv *priv)
1585{
1586 struct txd_fifo *f = &priv->txd_fifo0;
1587 int fsize;
1588
1589 f->m.rptr = READ_REG(priv, f->m.reg_RPTR) & TXF_WPTR_WR_PTR;
1590 fsize = f->m.rptr - f->m.wptr;
1591 if (fsize <= 0)
1592 fsize = f->m.memsz + fsize;
1593 return fsize;
1594}
1595
1596/**
1597 * bdx_tx_transmit - send packet to NIC
1598 * @skb: packet to send
1599 * @ndev: network device assigned to NIC
1600 * Return codes:
1601 * o NETDEV_TX_OK everything ok.
1602 * o NETDEV_TX_BUSY Cannot transmit packet, try later
1603 * Usually a bug, means queue start/stop flow control is broken in
1604 * the driver. Note: the driver must NOT put the skb in its DMA ring.
1605 */
1606static netdev_tx_t bdx_tx_transmit(struct sk_buff *skb,
1607 struct net_device *ndev)
1608{
1609 struct bdx_priv *priv = netdev_priv(ndev);
1610 struct txd_fifo *f = &priv->txd_fifo0;
1611 int txd_checksum = 7; /* full checksum */
1612 int txd_lgsnd = 0;
1613 int txd_vlan_id = 0;
1614 int txd_vtag = 0;
1615 int txd_mss = 0;
1616
1617 int nr_frags = skb_shinfo(skb)->nr_frags;
1618 struct txd_desc *txdd;
1619 int len;
1620 unsigned long flags;
1621
1622 ENTER;
1623 local_irq_save(flags);
1624 spin_lock(&priv->tx_lock);
1625
1626 /* build tx descriptor */
1627 BDX_ASSERT(f->m.wptr >= f->m.memsz); /* started with valid wptr */
1628 txdd = (struct txd_desc *)(f->m.va + f->m.wptr);
1629 if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL))
1630 txd_checksum = 0;
1631
1632 if (skb_shinfo(skb)->gso_size) {
1633 txd_mss = skb_shinfo(skb)->gso_size;
1634 txd_lgsnd = 1;
1635 DBG("skb %p skb len %d gso size = %d\n", skb, skb->len,
1636 txd_mss);
1637 }
1638
1639 if (skb_vlan_tag_present(skb)) {
1640 /*Cut VLAN ID to 12 bits */
1641 txd_vlan_id = skb_vlan_tag_get(skb) & BITS_MASK(12);
1642 txd_vtag = 1;
1643 }
1644
1645 txdd->length = CPU_CHIP_SWAP16(skb->len);
1646 txdd->mss = CPU_CHIP_SWAP16(txd_mss);
1647 txdd->txd_val1 =
1648 CPU_CHIP_SWAP32(TXD_W1_VAL
1649 (txd_sizes[nr_frags].qwords, txd_checksum, txd_vtag,
1650 txd_lgsnd, txd_vlan_id));
1651 DBG("=== TxD desc =====================\n");
1652 DBG("=== w1: 0x%x ================\n", txdd->txd_val1);
1653 DBG("=== w2: mss 0x%x len 0x%x\n", txdd->mss, txdd->length);
1654
1655 bdx_tx_map_skb(priv, skb, txdd);
1656
1657 /* increment TXD write pointer. In case of
1658 fifo wrapping copy reminder of the descriptor
1659 to the beginning */
1660 f->m.wptr += txd_sizes[nr_frags].bytes;
1661 len = f->m.wptr - f->m.memsz;
1662 if (unlikely(len >= 0)) {
1663 f->m.wptr = len;
1664 if (len > 0) {
1665 BDX_ASSERT(len > f->m.memsz);
1666 memcpy(f->m.va, f->m.va + f->m.memsz, len);
1667 }
1668 }
1669 BDX_ASSERT(f->m.wptr >= f->m.memsz); /* finished with valid wptr */
1670
1671 priv->tx_level -= txd_sizes[nr_frags].bytes;
1672 BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);
1673#ifdef BDX_DELAY_WPTR
1674 if (priv->tx_level > priv->tx_update_mark) {
1675 /* Force memory writes to complete before letting h/w
1676 know there are new descriptors to fetch.
1677 (might be needed on platforms like IA64)
1678 wmb(); */
1679 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1680 } else {
1681 if (priv->tx_noupd++ > BDX_NO_UPD_PACKETS) {
1682 priv->tx_noupd = 0;
1683 WRITE_REG(priv, f->m.reg_WPTR,
1684 f->m.wptr & TXF_WPTR_WR_PTR);
1685 }
1686 }
1687#else
1688 /* Force memory writes to complete before letting h/w
1689 know there are new descriptors to fetch.
1690 (might be needed on platforms like IA64)
1691 wmb(); */
1692 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1693
1694#endif
1695#ifdef BDX_LLTX
1696 netif_trans_update(ndev); /* NETIF_F_LLTX driver :( */
1697#endif
1698 ndev->stats.tx_packets++;
1699 ndev->stats.tx_bytes += skb->len;
1700
1701 if (priv->tx_level < BDX_MIN_TX_LEVEL) {
1702 DBG("%s: %s: TX Q STOP level %d\n",
1703 BDX_DRV_NAME, ndev->name, priv->tx_level);
1704 netif_stop_queue(ndev);
1705 }
1706
1707 spin_unlock_irqrestore(&priv->tx_lock, flags);
1708 return NETDEV_TX_OK;
1709}
1710
1711/**
1712 * bdx_tx_cleanup - clean TXF fifo, run in the context of IRQ.
1713 * @priv: bdx adapter
1714 *
1715 * It scans TXF fifo for descriptors, frees DMA mappings and reports to OS
1716 * that those packets were sent
1717 */
1718static void bdx_tx_cleanup(struct bdx_priv *priv)
1719{
1720 struct txf_fifo *f = &priv->txf_fifo0;
1721 struct txdb *db = &priv->txdb;
1722 int tx_level = 0;
1723
1724 ENTER;
1725 f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_MASK;
1726 BDX_ASSERT(f->m.rptr >= f->m.memsz); /* started with valid rptr */
1727
1728 while (f->m.wptr != f->m.rptr) {
1729 f->m.rptr += BDX_TXF_DESC_SZ;
1730 f->m.rptr &= f->m.size_mask;
1731
1732 /* unmap all the fragments */
1733 /* first has to come tx_maps containing dma */
1734 BDX_ASSERT(db->rptr->len == 0);
1735 do {
1736 BDX_ASSERT(db->rptr->addr.dma == 0);
1737 pci_unmap_page(priv->pdev, db->rptr->addr.dma,
1738 db->rptr->len, PCI_DMA_TODEVICE);
1739 bdx_tx_db_inc_rptr(db);
1740 } while (db->rptr->len > 0);
1741 tx_level -= db->rptr->len; /* '-' koz len is negative */
1742
1743 /* now should come skb pointer - free it */
1744 dev_kfree_skb_irq(db->rptr->addr.skb);
1745 bdx_tx_db_inc_rptr(db);
1746 }
1747
1748 /* let h/w know which TXF descriptors were cleaned */
1749 BDX_ASSERT((f->m.wptr & TXF_WPTR_WR_PTR) >= f->m.memsz);
1750 WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
1751
1752 /* We reclaimed resources, so in case the Q is stopped by xmit callback,
1753 * we resume the transmission and use tx_lock to synchronize with xmit.*/
1754 spin_lock(&priv->tx_lock);
1755 priv->tx_level += tx_level;
1756 BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);
1757#ifdef BDX_DELAY_WPTR
1758 if (priv->tx_noupd) {
1759 priv->tx_noupd = 0;
1760 WRITE_REG(priv, priv->txd_fifo0.m.reg_WPTR,
1761 priv->txd_fifo0.m.wptr & TXF_WPTR_WR_PTR);
1762 }
1763#endif
1764
1765 if (unlikely(netif_queue_stopped(priv->ndev) &&
1766 netif_carrier_ok(priv->ndev) &&
1767 (priv->tx_level >= BDX_MIN_TX_LEVEL))) {
1768 DBG("%s: %s: TX Q WAKE level %d\n",
1769 BDX_DRV_NAME, priv->ndev->name, priv->tx_level);
1770 netif_wake_queue(priv->ndev);
1771 }
1772 spin_unlock(&priv->tx_lock);
1773}
1774
1775/**
1776 * bdx_tx_free_skbs - frees all skbs from TXD fifo.
1777 * It gets called when OS stops this dev, eg upon "ifconfig down" or rmmod
1778 */
1779static void bdx_tx_free_skbs(struct bdx_priv *priv)
1780{
1781 struct txdb *db = &priv->txdb;
1782
1783 ENTER;
1784 while (db->rptr != db->wptr) {
1785 if (likely(db->rptr->len))
1786 pci_unmap_page(priv->pdev, db->rptr->addr.dma,
1787 db->rptr->len, PCI_DMA_TODEVICE);
1788 else
1789 dev_kfree_skb(db->rptr->addr.skb);
1790 bdx_tx_db_inc_rptr(db);
1791 }
1792 RET();
1793}
1794
1795/* bdx_tx_free - frees all Tx resources */
1796static void bdx_tx_free(struct bdx_priv *priv)
1797{
1798 ENTER;
1799 bdx_tx_free_skbs(priv);
1800 bdx_fifo_free(priv, &priv->txd_fifo0.m);
1801 bdx_fifo_free(priv, &priv->txf_fifo0.m);
1802 bdx_tx_db_close(&priv->txdb);
1803}
1804
1805/**
1806 * bdx_tx_push_desc - push descriptor to TxD fifo
1807 * @priv: NIC private structure
1808 * @data: desc's data
1809 * @size: desc's size
1810 *
1811 * Pushes desc to TxD fifo and overlaps it if needed.
1812 * NOTE: this func does not check for available space. this is responsibility
1813 * of the caller. Neither does it check that data size is smaller than
1814 * fifo size.
1815 */
1816static void bdx_tx_push_desc(struct bdx_priv *priv, void *data, int size)
1817{
1818 struct txd_fifo *f = &priv->txd_fifo0;
1819 int i = f->m.memsz - f->m.wptr;
1820
1821 if (size == 0)
1822 return;
1823
1824 if (i > size) {
1825 memcpy(f->m.va + f->m.wptr, data, size);
1826 f->m.wptr += size;
1827 } else {
1828 memcpy(f->m.va + f->m.wptr, data, i);
1829 f->m.wptr = size - i;
1830 memcpy(f->m.va, data + i, f->m.wptr);
1831 }
1832 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1833}
1834
1835/**
1836 * bdx_tx_push_desc_safe - push descriptor to TxD fifo in a safe way
1837 * @priv: NIC private structure
1838 * @data: desc's data
1839 * @size: desc's size
1840 *
1841 * NOTE: this func does check for available space and, if necessary, waits for
1842 * NIC to read existing data before writing new one.
1843 */
1844static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size)
1845{
1846 int timer = 0;
1847 ENTER;
1848
1849 while (size > 0) {
1850 /* we substruct 8 because when fifo is full rptr == wptr
1851 which also means that fifo is empty, we can understand
1852 the difference, but could hw do the same ??? :) */
1853 int avail = bdx_tx_space(priv) - 8;
1854 if (avail <= 0) {
1855 if (timer++ > 300) { /* prevent endless loop */
1856 DBG("timeout while writing desc to TxD fifo\n");
1857 break;
1858 }
1859 udelay(50); /* give hw a chance to clean fifo */
1860 continue;
1861 }
1862 avail = min(avail, size);
1863 DBG("about to push %d bytes starting %p size %d\n", avail,
1864 data, size);
1865 bdx_tx_push_desc(priv, data, avail);
1866 size -= avail;
1867 data += avail;
1868 }
1869 RET();
1870}
1871
1872static const struct net_device_ops bdx_netdev_ops = {
1873 .ndo_open = bdx_open,
1874 .ndo_stop = bdx_close,
1875 .ndo_start_xmit = bdx_tx_transmit,
1876 .ndo_validate_addr = eth_validate_addr,
1877 .ndo_do_ioctl = bdx_ioctl,
1878 .ndo_set_rx_mode = bdx_setmulti,
1879 .ndo_change_mtu = bdx_change_mtu,
1880 .ndo_set_mac_address = bdx_set_mac,
1881 .ndo_vlan_rx_add_vid = bdx_vlan_rx_add_vid,
1882 .ndo_vlan_rx_kill_vid = bdx_vlan_rx_kill_vid,
1883};
1884
1885/**
1886 * bdx_probe - Device Initialization Routine
1887 * @pdev: PCI device information struct
1888 * @ent: entry in bdx_pci_tbl
1889 *
1890 * Returns 0 on success, negative on failure
1891 *
1892 * bdx_probe initializes an adapter identified by a pci_dev structure.
1893 * The OS initialization, configuring of the adapter private structure,
1894 * and a hardware reset occur.
1895 *
1896 * functions and their order used as explained in
1897 * /usr/src/linux/Documentation/DMA-{API,mapping}.txt
1898 *
1899 */
1900
1901/* TBD: netif_msg should be checked and implemented. I disable it for now */
1902static int
1903bdx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1904{
1905 struct net_device *ndev;
1906 struct bdx_priv *priv;
1907 int err, pci_using_dac, port;
1908 unsigned long pciaddr;
1909 u32 regionSize;
1910 struct pci_nic *nic;
1911
1912 ENTER;
1913
1914 nic = vmalloc(sizeof(*nic));
1915 if (!nic)
1916 RET(-ENOMEM);
1917
1918 /************** pci *****************/
1919 err = pci_enable_device(pdev);
1920 if (err) /* it triggers interrupt, dunno why. */
1921 goto err_pci; /* it's not a problem though */
1922
1923 if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) &&
1924 !(err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))) {
1925 pci_using_dac = 1;
1926 } else {
1927 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) ||
1928 (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) {
1929 pr_err("No usable DMA configuration, aborting\n");
1930 goto err_dma;
1931 }
1932 pci_using_dac = 0;
1933 }
1934
1935 err = pci_request_regions(pdev, BDX_DRV_NAME);
1936 if (err)
1937 goto err_dma;
1938
1939 pci_set_master(pdev);
1940
1941 pciaddr = pci_resource_start(pdev, 0);
1942 if (!pciaddr) {
1943 err = -EIO;
1944 pr_err("no MMIO resource\n");
1945 goto err_out_res;
1946 }
1947 regionSize = pci_resource_len(pdev, 0);
1948 if (regionSize < BDX_REGS_SIZE) {
1949 err = -EIO;
1950 pr_err("MMIO resource (%x) too small\n", regionSize);
1951 goto err_out_res;
1952 }
1953
1954 nic->regs = ioremap(pciaddr, regionSize);
1955 if (!nic->regs) {
1956 err = -EIO;
1957 pr_err("ioremap failed\n");
1958 goto err_out_res;
1959 }
1960
1961 if (pdev->irq < 2) {
1962 err = -EIO;
1963 pr_err("invalid irq (%d)\n", pdev->irq);
1964 goto err_out_iomap;
1965 }
1966 pci_set_drvdata(pdev, nic);
1967
1968 if (pdev->device == 0x3014)
1969 nic->port_num = 2;
1970 else
1971 nic->port_num = 1;
1972
1973 print_hw_id(pdev);
1974
1975 bdx_hw_reset_direct(nic->regs);
1976
1977 nic->irq_type = IRQ_INTX;
1978#ifdef BDX_MSI
1979 if ((readl(nic->regs + FPGA_VER) & 0xFFF) >= 378) {
1980 err = pci_enable_msi(pdev);
1981 if (err)
1982 pr_err("Can't enable msi. error is %d\n", err);
1983 else
1984 nic->irq_type = IRQ_MSI;
1985 } else
1986 DBG("HW does not support MSI\n");
1987#endif
1988
1989 /************** netdev **************/
1990 for (port = 0; port < nic->port_num; port++) {
1991 ndev = alloc_etherdev(sizeof(struct bdx_priv));
1992 if (!ndev) {
1993 err = -ENOMEM;
1994 goto err_out_iomap;
1995 }
1996
1997 ndev->netdev_ops = &bdx_netdev_ops;
1998 ndev->tx_queue_len = BDX_NDEV_TXQ_LEN;
1999
2000 bdx_set_ethtool_ops(ndev); /* ethtool interface */
2001
2002 /* these fields are used for info purposes only
2003 * so we can have them same for all ports of the board */
2004 ndev->if_port = port;
2005 ndev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO
2006 | NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
2007 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_RXCSUM
2008 ;
2009 ndev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
2010 NETIF_F_TSO | NETIF_F_HW_VLAN_CTAG_TX;
2011
2012 if (pci_using_dac)
2013 ndev->features |= NETIF_F_HIGHDMA;
2014
2015 /************** priv ****************/
2016 priv = nic->priv[port] = netdev_priv(ndev);
2017
2018 priv->pBdxRegs = nic->regs + port * 0x8000;
2019 priv->port = port;
2020 priv->pdev = pdev;
2021 priv->ndev = ndev;
2022 priv->nic = nic;
2023 priv->msg_enable = BDX_DEF_MSG_ENABLE;
2024
2025 netif_napi_add(ndev, &priv->napi, bdx_poll, 64);
2026
2027 if ((readl(nic->regs + FPGA_VER) & 0xFFF) == 308) {
2028 DBG("HW statistics not supported\n");
2029 priv->stats_flag = 0;
2030 } else {
2031 priv->stats_flag = 1;
2032 }
2033
2034 /* Initialize fifo sizes. */
2035 priv->txd_size = 2;
2036 priv->txf_size = 2;
2037 priv->rxd_size = 2;
2038 priv->rxf_size = 3;
2039
2040 /* Initialize the initial coalescing registers. */
2041 priv->rdintcm = INT_REG_VAL(0x20, 1, 4, 12);
2042 priv->tdintcm = INT_REG_VAL(0x20, 1, 0, 12);
2043
2044 /* ndev->xmit_lock spinlock is not used.
2045 * Private priv->tx_lock is used for synchronization
2046 * between transmit and TX irq cleanup. In addition
2047 * set multicast list callback has to use priv->tx_lock.
2048 */
2049#ifdef BDX_LLTX
2050 ndev->features |= NETIF_F_LLTX;
2051#endif
2052 /* MTU range: 60 - 16384 */
2053 ndev->min_mtu = ETH_ZLEN;
2054 ndev->max_mtu = BDX_MAX_MTU;
2055
2056 spin_lock_init(&priv->tx_lock);
2057
2058 /*bdx_hw_reset(priv); */
2059 if (bdx_read_mac(priv)) {
2060 pr_err("load MAC address failed\n");
2061 goto err_out_iomap;
2062 }
2063 SET_NETDEV_DEV(ndev, &pdev->dev);
2064 err = register_netdev(ndev);
2065 if (err) {
2066 pr_err("register_netdev failed\n");
2067 goto err_out_free;
2068 }
2069 netif_carrier_off(ndev);
2070 netif_stop_queue(ndev);
2071
2072 print_eth_id(ndev);
2073 }
2074 RET(0);
2075
2076err_out_free:
2077 free_netdev(ndev);
2078err_out_iomap:
2079 iounmap(nic->regs);
2080err_out_res:
2081 pci_release_regions(pdev);
2082err_dma:
2083 pci_disable_device(pdev);
2084err_pci:
2085 vfree(nic);
2086
2087 RET(err);
2088}
2089
2090/****************** Ethtool interface *********************/
2091/* get strings for statistics counters */
2092static const char
2093 bdx_stat_names[][ETH_GSTRING_LEN] = {
2094 "InUCast", /* 0x7200 */
2095 "InMCast", /* 0x7210 */
2096 "InBCast", /* 0x7220 */
2097 "InPkts", /* 0x7230 */
2098 "InErrors", /* 0x7240 */
2099 "InDropped", /* 0x7250 */
2100 "FrameTooLong", /* 0x7260 */
2101 "FrameSequenceErrors", /* 0x7270 */
2102 "InVLAN", /* 0x7280 */
2103 "InDroppedDFE", /* 0x7290 */
2104 "InDroppedIntFull", /* 0x72A0 */
2105 "InFrameAlignErrors", /* 0x72B0 */
2106
2107 /* 0x72C0-0x72E0 RSRV */
2108
2109 "OutUCast", /* 0x72F0 */
2110 "OutMCast", /* 0x7300 */
2111 "OutBCast", /* 0x7310 */
2112 "OutPkts", /* 0x7320 */
2113
2114 /* 0x7330-0x7360 RSRV */
2115
2116 "OutVLAN", /* 0x7370 */
2117 "InUCastOctects", /* 0x7380 */
2118 "OutUCastOctects", /* 0x7390 */
2119
2120 /* 0x73A0-0x73B0 RSRV */
2121
2122 "InBCastOctects", /* 0x73C0 */
2123 "OutBCastOctects", /* 0x73D0 */
2124 "InOctects", /* 0x73E0 */
2125 "OutOctects", /* 0x73F0 */
2126};
2127
2128/*
2129 * bdx_get_link_ksettings - get device-specific settings
2130 * @netdev
2131 * @ecmd
2132 */
2133static int bdx_get_link_ksettings(struct net_device *netdev,
2134 struct ethtool_link_ksettings *ecmd)
2135{
2136 ethtool_link_ksettings_zero_link_mode(ecmd, supported);
2137 ethtool_link_ksettings_add_link_mode(ecmd, supported,
2138 10000baseT_Full);
2139 ethtool_link_ksettings_add_link_mode(ecmd, supported, FIBRE);
2140 ethtool_link_ksettings_zero_link_mode(ecmd, advertising);
2141 ethtool_link_ksettings_add_link_mode(ecmd, advertising,
2142 10000baseT_Full);
2143 ethtool_link_ksettings_add_link_mode(ecmd, advertising, FIBRE);
2144
2145 ecmd->base.speed = SPEED_10000;
2146 ecmd->base.duplex = DUPLEX_FULL;
2147 ecmd->base.port = PORT_FIBRE;
2148 ecmd->base.autoneg = AUTONEG_DISABLE;
2149
2150 return 0;
2151}
2152
2153/*
2154 * bdx_get_drvinfo - report driver information
2155 * @netdev
2156 * @drvinfo
2157 */
2158static void
2159bdx_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo)
2160{
2161 struct bdx_priv *priv = netdev_priv(netdev);
2162
2163 strlcpy(drvinfo->driver, BDX_DRV_NAME, sizeof(drvinfo->driver));
2164 strlcpy(drvinfo->version, BDX_DRV_VERSION, sizeof(drvinfo->version));
2165 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
2166 strlcpy(drvinfo->bus_info, pci_name(priv->pdev),
2167 sizeof(drvinfo->bus_info));
2168}
2169
2170/*
2171 * bdx_get_coalesce - get interrupt coalescing parameters
2172 * @netdev
2173 * @ecoal
2174 */
2175static int
2176bdx_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal)
2177{
2178 u32 rdintcm;
2179 u32 tdintcm;
2180 struct bdx_priv *priv = netdev_priv(netdev);
2181
2182 rdintcm = priv->rdintcm;
2183 tdintcm = priv->tdintcm;
2184
2185 /* PCK_TH measures in multiples of FIFO bytes
2186 We translate to packets */
2187 ecoal->rx_coalesce_usecs = GET_INT_COAL(rdintcm) * INT_COAL_MULT;
2188 ecoal->rx_max_coalesced_frames =
2189 ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc));
2190
2191 ecoal->tx_coalesce_usecs = GET_INT_COAL(tdintcm) * INT_COAL_MULT;
2192 ecoal->tx_max_coalesced_frames =
2193 ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ);
2194
2195 /* adaptive parameters ignored */
2196 return 0;
2197}
2198
2199/*
2200 * bdx_set_coalesce - set interrupt coalescing parameters
2201 * @netdev
2202 * @ecoal
2203 */
2204static int
2205bdx_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal)
2206{
2207 u32 rdintcm;
2208 u32 tdintcm;
2209 struct bdx_priv *priv = netdev_priv(netdev);
2210 int rx_coal;
2211 int tx_coal;
2212 int rx_max_coal;
2213 int tx_max_coal;
2214
2215 /* Check for valid input */
2216 rx_coal = ecoal->rx_coalesce_usecs / INT_COAL_MULT;
2217 tx_coal = ecoal->tx_coalesce_usecs / INT_COAL_MULT;
2218 rx_max_coal = ecoal->rx_max_coalesced_frames;
2219 tx_max_coal = ecoal->tx_max_coalesced_frames;
2220
2221 /* Translate from packets to multiples of FIFO bytes */
2222 rx_max_coal =
2223 (((rx_max_coal * sizeof(struct rxf_desc)) + PCK_TH_MULT - 1)
2224 / PCK_TH_MULT);
2225 tx_max_coal =
2226 (((tx_max_coal * BDX_TXF_DESC_SZ) + PCK_TH_MULT - 1)
2227 / PCK_TH_MULT);
2228
2229 if ((rx_coal > 0x7FFF) || (tx_coal > 0x7FFF) ||
2230 (rx_max_coal > 0xF) || (tx_max_coal > 0xF))
2231 return -EINVAL;
2232
2233 rdintcm = INT_REG_VAL(rx_coal, GET_INT_COAL_RC(priv->rdintcm),
2234 GET_RXF_TH(priv->rdintcm), rx_max_coal);
2235 tdintcm = INT_REG_VAL(tx_coal, GET_INT_COAL_RC(priv->tdintcm), 0,
2236 tx_max_coal);
2237
2238 priv->rdintcm = rdintcm;
2239 priv->tdintcm = tdintcm;
2240
2241 WRITE_REG(priv, regRDINTCM0, rdintcm);
2242 WRITE_REG(priv, regTDINTCM0, tdintcm);
2243
2244 return 0;
2245}
2246
2247/* Convert RX fifo size to number of pending packets */
2248static inline int bdx_rx_fifo_size_to_packets(int rx_size)
2249{
2250 return (FIFO_SIZE * (1 << rx_size)) / sizeof(struct rxf_desc);
2251}
2252
2253/* Convert TX fifo size to number of pending packets */
2254static inline int bdx_tx_fifo_size_to_packets(int tx_size)
2255{
2256 return (FIFO_SIZE * (1 << tx_size)) / BDX_TXF_DESC_SZ;
2257}
2258
2259/*
2260 * bdx_get_ringparam - report ring sizes
2261 * @netdev
2262 * @ring
2263 */
2264static void
2265bdx_get_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
2266{
2267 struct bdx_priv *priv = netdev_priv(netdev);
2268
2269 /*max_pending - the maximum-sized FIFO we allow */
2270 ring->rx_max_pending = bdx_rx_fifo_size_to_packets(3);
2271 ring->tx_max_pending = bdx_tx_fifo_size_to_packets(3);
2272 ring->rx_pending = bdx_rx_fifo_size_to_packets(priv->rxf_size);
2273 ring->tx_pending = bdx_tx_fifo_size_to_packets(priv->txd_size);
2274}
2275
2276/*
2277 * bdx_set_ringparam - set ring sizes
2278 * @netdev
2279 * @ring
2280 */
2281static int
2282bdx_set_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
2283{
2284 struct bdx_priv *priv = netdev_priv(netdev);
2285 int rx_size = 0;
2286 int tx_size = 0;
2287
2288 for (; rx_size < 4; rx_size++) {
2289 if (bdx_rx_fifo_size_to_packets(rx_size) >= ring->rx_pending)
2290 break;
2291 }
2292 if (rx_size == 4)
2293 rx_size = 3;
2294
2295 for (; tx_size < 4; tx_size++) {
2296 if (bdx_tx_fifo_size_to_packets(tx_size) >= ring->tx_pending)
2297 break;
2298 }
2299 if (tx_size == 4)
2300 tx_size = 3;
2301
2302 /*Is there anything to do? */
2303 if ((rx_size == priv->rxf_size) &&
2304 (tx_size == priv->txd_size))
2305 return 0;
2306
2307 priv->rxf_size = rx_size;
2308 if (rx_size > 1)
2309 priv->rxd_size = rx_size - 1;
2310 else
2311 priv->rxd_size = rx_size;
2312
2313 priv->txf_size = priv->txd_size = tx_size;
2314
2315 if (netif_running(netdev)) {
2316 bdx_close(netdev);
2317 bdx_open(netdev);
2318 }
2319 return 0;
2320}
2321
2322/*
2323 * bdx_get_strings - return a set of strings that describe the requested objects
2324 * @netdev
2325 * @data
2326 */
2327static void bdx_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2328{
2329 switch (stringset) {
2330 case ETH_SS_STATS:
2331 memcpy(data, *bdx_stat_names, sizeof(bdx_stat_names));
2332 break;
2333 }
2334}
2335
2336/*
2337 * bdx_get_sset_count - return number of statistics or tests
2338 * @netdev
2339 */
2340static int bdx_get_sset_count(struct net_device *netdev, int stringset)
2341{
2342 struct bdx_priv *priv = netdev_priv(netdev);
2343
2344 switch (stringset) {
2345 case ETH_SS_STATS:
2346 BDX_ASSERT(ARRAY_SIZE(bdx_stat_names)
2347 != sizeof(struct bdx_stats) / sizeof(u64));
2348 return (priv->stats_flag) ? ARRAY_SIZE(bdx_stat_names) : 0;
2349 }
2350
2351 return -EINVAL;
2352}
2353
2354/*
2355 * bdx_get_ethtool_stats - return device's hardware L2 statistics
2356 * @netdev
2357 * @stats
2358 * @data
2359 */
2360static void bdx_get_ethtool_stats(struct net_device *netdev,
2361 struct ethtool_stats *stats, u64 *data)
2362{
2363 struct bdx_priv *priv = netdev_priv(netdev);
2364
2365 if (priv->stats_flag) {
2366
2367 /* Update stats from HW */
2368 bdx_update_stats(priv);
2369
2370 /* Copy data to user buffer */
2371 memcpy(data, &priv->hw_stats, sizeof(priv->hw_stats));
2372 }
2373}
2374
2375/*
2376 * bdx_set_ethtool_ops - ethtool interface implementation
2377 * @netdev
2378 */
2379static void bdx_set_ethtool_ops(struct net_device *netdev)
2380{
2381 static const struct ethtool_ops bdx_ethtool_ops = {
2382 .get_drvinfo = bdx_get_drvinfo,
2383 .get_link = ethtool_op_get_link,
2384 .get_coalesce = bdx_get_coalesce,
2385 .set_coalesce = bdx_set_coalesce,
2386 .get_ringparam = bdx_get_ringparam,
2387 .set_ringparam = bdx_set_ringparam,
2388 .get_strings = bdx_get_strings,
2389 .get_sset_count = bdx_get_sset_count,
2390 .get_ethtool_stats = bdx_get_ethtool_stats,
2391 .get_link_ksettings = bdx_get_link_ksettings,
2392 };
2393
2394 netdev->ethtool_ops = &bdx_ethtool_ops;
2395}
2396
2397/**
2398 * bdx_remove - Device Removal Routine
2399 * @pdev: PCI device information struct
2400 *
2401 * bdx_remove is called by the PCI subsystem to alert the driver
2402 * that it should release a PCI device. The could be caused by a
2403 * Hot-Plug event, or because the driver is going to be removed from
2404 * memory.
2405 **/
2406static void bdx_remove(struct pci_dev *pdev)
2407{
2408 struct pci_nic *nic = pci_get_drvdata(pdev);
2409 struct net_device *ndev;
2410 int port;
2411
2412 for (port = 0; port < nic->port_num; port++) {
2413 ndev = nic->priv[port]->ndev;
2414 unregister_netdev(ndev);
2415 free_netdev(ndev);
2416 }
2417
2418 /*bdx_hw_reset_direct(nic->regs); */
2419#ifdef BDX_MSI
2420 if (nic->irq_type == IRQ_MSI)
2421 pci_disable_msi(pdev);
2422#endif
2423
2424 iounmap(nic->regs);
2425 pci_release_regions(pdev);
2426 pci_disable_device(pdev);
2427 vfree(nic);
2428
2429 RET();
2430}
2431
2432static struct pci_driver bdx_pci_driver = {
2433 .name = BDX_DRV_NAME,
2434 .id_table = bdx_pci_tbl,
2435 .probe = bdx_probe,
2436 .remove = bdx_remove,
2437};
2438
2439/*
2440 * print_driver_id - print parameters of the driver build
2441 */
2442static void __init print_driver_id(void)
2443{
2444 pr_info("%s, %s\n", BDX_DRV_DESC, BDX_DRV_VERSION);
2445 pr_info("Options: hw_csum %s\n", BDX_MSI_STRING);
2446}
2447
2448static int __init bdx_module_init(void)
2449{
2450 ENTER;
2451 init_txd_sizes();
2452 print_driver_id();
2453 RET(pci_register_driver(&bdx_pci_driver));
2454}
2455
2456module_init(bdx_module_init);
2457
2458static void __exit bdx_module_exit(void)
2459{
2460 ENTER;
2461 pci_unregister_driver(&bdx_pci_driver);
2462 RET();
2463}
2464
2465module_exit(bdx_module_exit);
2466
2467MODULE_LICENSE("GPL");
2468MODULE_AUTHOR(DRIVER_AUTHOR);
2469MODULE_DESCRIPTION(BDX_DRV_DESC);
2470MODULE_FIRMWARE("tehuti/bdx.bin");