1/*
   2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
   3 * Ethernet adapters. Based on earlier sk98lin, e100 and
   4 * FreeBSD if_sk drivers.
   5 *
   6 * This driver intentionally does not support all the features
   7 * of the original driver such as link fail-over and link management because
   8 * those should be done at higher levels.
   9 *
  10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
  11 *
  12 * This program is free software; you can redistribute it and/or modify
  13 * it under the terms of the GNU General Public License as published by
  14 * the Free Software Foundation; either version 2 of the License.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24 */
  25
  26#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  27
  28#include <linux/in.h>
  29#include <linux/kernel.h>
  30#include <linux/module.h>
  31#include <linux/moduleparam.h>
  32#include <linux/netdevice.h>
  33#include <linux/etherdevice.h>
  34#include <linux/ethtool.h>
  35#include <linux/pci.h>
  36#include <linux/if_vlan.h>
  37#include <linux/ip.h>
  38#include <linux/delay.h>
  39#include <linux/crc32.h>
  40#include <linux/dma-mapping.h>
  41#include <linux/debugfs.h>
  42#include <linux/sched.h>
  43#include <linux/seq_file.h>
  44#include <linux/mii.h>
  45#include <linux/slab.h>
  46#include <linux/dmi.h>
  47#include <linux/prefetch.h>
  48#include <asm/irq.h>
  49
  50#include "skge.h"
  51
  52#define DRV_NAME		"skge"
  53#define DRV_VERSION		"1.14"
  54
  55#define DEFAULT_TX_RING_SIZE	128
  56#define DEFAULT_RX_RING_SIZE	512
  57#define MAX_TX_RING_SIZE	1024
  58#define TX_LOW_WATER		(MAX_SKB_FRAGS + 1)
  59#define MAX_RX_RING_SIZE	4096
  60#define RX_COPY_THRESHOLD	128
  61#define RX_BUF_SIZE		1536
  62#define PHY_RETRIES	        1000
  63#define ETH_JUMBO_MTU		9000
  64#define TX_WATCHDOG		(5 * HZ)
  65#define NAPI_WEIGHT		64
  66#define BLINK_MS		250
  67#define LINK_HZ			HZ
  68
  69#define SKGE_EEPROM_MAGIC	0x9933aabb
  70
  71
  72MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
  73MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
  74MODULE_LICENSE("GPL");
  75MODULE_VERSION(DRV_VERSION);
  76
  77static const u32 default_msg = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
  78				NETIF_MSG_LINK | NETIF_MSG_IFUP |
  79				NETIF_MSG_IFDOWN);
  80
  81static int debug = -1;	/* defaults above */
  82module_param(debug, int, 0);
  83MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  84
  85static const struct pci_device_id skge_id_table[] = {
  86	{ PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x1700) },	  /* 3Com 3C940 */
  87	{ PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x80EB) },	  /* 3Com 3C940B */
  88#ifdef CONFIG_SKGE_GENESIS
  89	{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4300) }, /* SK-9xx */
  90#endif
  91	{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4320) }, /* SK-98xx V2.0 */
  92	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },	  /* D-Link DGE-530T (rev.B) */
  93	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4c00) },	  /* D-Link DGE-530T */
  94	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302) },	  /* D-Link DGE-530T Rev C1 */
  95	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },	  /* Marvell Yukon 88E8001/8003/8010 */
  96	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) },	  /* Belkin */
  97	{ PCI_DEVICE(PCI_VENDOR_ID_CNET, 0x434E) }, 	  /* CNet PowerG-2000 */
  98	{ PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, 0x1064) },	  /* Linksys EG1064 v2 */
  99	{ PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 }, /* Linksys EG1032 v2 */
 100	{ 0 }
 101};
 102MODULE_DEVICE_TABLE(pci, skge_id_table);
 103
 104static int skge_up(struct net_device *dev);
 105static int skge_down(struct net_device *dev);
 106static void skge_phy_reset(struct skge_port *skge);
 107static void skge_tx_clean(struct net_device *dev);
 108static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
 109static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
 110static void genesis_get_stats(struct skge_port *skge, u64 *data);
 111static void yukon_get_stats(struct skge_port *skge, u64 *data);
 112static void yukon_init(struct skge_hw *hw, int port);
 113static void genesis_mac_init(struct skge_hw *hw, int port);
 114static void genesis_link_up(struct skge_port *skge);
 115static void skge_set_multicast(struct net_device *dev);
 116static irqreturn_t skge_intr(int irq, void *dev_id);
 117
 118/* Avoid conditionals by using array */
 119static const int txqaddr[] = { Q_XA1, Q_XA2 };
 120static const int rxqaddr[] = { Q_R1, Q_R2 };
 121static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
 122static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
 123static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
 124static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
 125
 126static inline bool is_genesis(const struct skge_hw *hw)
 127{
 128#ifdef CONFIG_SKGE_GENESIS
 129	return hw->chip_id == CHIP_ID_GENESIS;
 130#else
 131	return false;
 132#endif
 133}
 134
 135static int skge_get_regs_len(struct net_device *dev)
 136{
 137	return 0x4000;
 138}
 139
 140/*
 141 * Returns copy of whole control register region
 142 * Note: skip RAM address register because accessing it will
 143 * 	 cause bus hangs!
 144 */
 145static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
 146			  void *p)
 147{
 148	const struct skge_port *skge = netdev_priv(dev);
 149	const void __iomem *io = skge->hw->regs;
 150
 151	regs->version = 1;
 152	memset(p, 0, regs->len);
 153	memcpy_fromio(p, io, B3_RAM_ADDR);
 154
 155	memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
 156		      regs->len - B3_RI_WTO_R1);
 157}
 158
 159/* Wake on Lan only supported on Yukon chips with rev 1 or above */
 160static u32 wol_supported(const struct skge_hw *hw)
 161{
 162	if (is_genesis(hw))
 163		return 0;
 164
 165	if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
 166		return 0;
 167
 168	return WAKE_MAGIC | WAKE_PHY;
 169}
 170
 171static void skge_wol_init(struct skge_port *skge)
 172{
 173	struct skge_hw *hw = skge->hw;
 174	int port = skge->port;
 175	u16 ctrl;
 176
 177	skge_write16(hw, B0_CTST, CS_RST_CLR);
 178	skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
 179
 180	/* Turn on Vaux */
 181	skge_write8(hw, B0_POWER_CTRL,
 182		    PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
 183
 184	/* WA code for COMA mode -- clear PHY reset */
 185	if (hw->chip_id == CHIP_ID_YUKON_LITE &&
 186	    hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
 187		u32 reg = skge_read32(hw, B2_GP_IO);
 188		reg |= GP_DIR_9;
 189		reg &= ~GP_IO_9;
 190		skge_write32(hw, B2_GP_IO, reg);
 191	}
 192
 193	skge_write32(hw, SK_REG(port, GPHY_CTRL),
 194		     GPC_DIS_SLEEP |
 195		     GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
 196		     GPC_ANEG_1 | GPC_RST_SET);
 197
 198	skge_write32(hw, SK_REG(port, GPHY_CTRL),
 199		     GPC_DIS_SLEEP |
 200		     GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
 201		     GPC_ANEG_1 | GPC_RST_CLR);
 202
 203	skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
 204
 205	/* Force to 10/100 skge_reset will re-enable on resume	 */
 206	gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
 207		     (PHY_AN_100FULL | PHY_AN_100HALF |
 208		      PHY_AN_10FULL | PHY_AN_10HALF | PHY_AN_CSMA));
 209	/* no 1000 HD/FD */
 210	gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
 211	gm_phy_write(hw, port, PHY_MARV_CTRL,
 212		     PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
 213		     PHY_CT_RE_CFG | PHY_CT_DUP_MD);
 214
 215
 216	/* Set GMAC to no flow control and auto update for speed/duplex */
 217	gma_write16(hw, port, GM_GP_CTRL,
 218		    GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
 219		    GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
 220
 221	/* Set WOL address */
 222	memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
 223		    skge->netdev->dev_addr, ETH_ALEN);
 224
 225	/* Turn on appropriate WOL control bits */
 226	skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
 227	ctrl = 0;
 228	if (skge->wol & WAKE_PHY)
 229		ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
 230	else
 231		ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
 232
 233	if (skge->wol & WAKE_MAGIC)
 234		ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
 235	else
 236		ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
 237
 238	ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
 239	skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
 240
 241	/* block receiver */
 242	skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
 243}
 244
 245static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 246{
 247	struct skge_port *skge = netdev_priv(dev);
 248
 249	wol->supported = wol_supported(skge->hw);
 250	wol->wolopts = skge->wol;
 251}
 252
 253static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 254{
 255	struct skge_port *skge = netdev_priv(dev);
 256	struct skge_hw *hw = skge->hw;
 257
 258	if ((wol->wolopts & ~wol_supported(hw)) ||
 259	    !device_can_wakeup(&hw->pdev->dev))
 260		return -EOPNOTSUPP;
 261
 262	skge->wol = wol->wolopts;
 263
 264	device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
 265
 266	return 0;
 267}
 268
 269/* Determine supported/advertised modes based on hardware.
 270 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
 271 */
 272static u32 skge_supported_modes(const struct skge_hw *hw)
 273{
 274	u32 supported;
 275
 276	if (hw->copper) {
 277		supported = (SUPPORTED_10baseT_Half |
 278			     SUPPORTED_10baseT_Full |
 279			     SUPPORTED_100baseT_Half |
 280			     SUPPORTED_100baseT_Full |
 281			     SUPPORTED_1000baseT_Half |
 282			     SUPPORTED_1000baseT_Full |
 283			     SUPPORTED_Autoneg |
 284			     SUPPORTED_TP);
 285
 286		if (is_genesis(hw))
 287			supported &= ~(SUPPORTED_10baseT_Half |
 288				       SUPPORTED_10baseT_Full |
 289				       SUPPORTED_100baseT_Half |
 290				       SUPPORTED_100baseT_Full);
 291
 292		else if (hw->chip_id == CHIP_ID_YUKON)
 293			supported &= ~SUPPORTED_1000baseT_Half;
 294	} else
 295		supported = (SUPPORTED_1000baseT_Full |
 296			     SUPPORTED_1000baseT_Half |
 297			     SUPPORTED_FIBRE |
 298			     SUPPORTED_Autoneg);
 299
 300	return supported;
 301}
 302
 303static int skge_get_link_ksettings(struct net_device *dev,
 304				   struct ethtool_link_ksettings *cmd)
 305{
 306	struct skge_port *skge = netdev_priv(dev);
 307	struct skge_hw *hw = skge->hw;
 308	u32 supported, advertising;
 309
 310	supported = skge_supported_modes(hw);
 311
 312	if (hw->copper) {
 313		cmd->base.port = PORT_TP;
 314		cmd->base.phy_address = hw->phy_addr;
 315	} else
 316		cmd->base.port = PORT_FIBRE;
 317
 318	advertising = skge->advertising;
 319	cmd->base.autoneg = skge->autoneg;
 320	cmd->base.speed = skge->speed;
 321	cmd->base.duplex = skge->duplex;
 322
 323	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
 324						supported);
 325	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
 326						advertising);
 327
 328	return 0;
 329}
 330
 331static int skge_set_link_ksettings(struct net_device *dev,
 332				   const struct ethtool_link_ksettings *cmd)
 333{
 334	struct skge_port *skge = netdev_priv(dev);
 335	const struct skge_hw *hw = skge->hw;
 336	u32 supported = skge_supported_modes(hw);
 337	int err = 0;
 338	u32 advertising;
 339
 340	ethtool_convert_link_mode_to_legacy_u32(&advertising,
 341						cmd->link_modes.advertising);
 342
 343	if (cmd->base.autoneg == AUTONEG_ENABLE) {
 344		advertising = supported;
 345		skge->duplex = -1;
 346		skge->speed = -1;
 347	} else {
 348		u32 setting;
 349		u32 speed = cmd->base.speed;
 350
 351		switch (speed) {
 352		case SPEED_1000:
 353			if (cmd->base.duplex == DUPLEX_FULL)
 354				setting = SUPPORTED_1000baseT_Full;
 355			else if (cmd->base.duplex == DUPLEX_HALF)
 356				setting = SUPPORTED_1000baseT_Half;
 357			else
 358				return -EINVAL;
 359			break;
 360		case SPEED_100:
 361			if (cmd->base.duplex == DUPLEX_FULL)
 362				setting = SUPPORTED_100baseT_Full;
 363			else if (cmd->base.duplex == DUPLEX_HALF)
 364				setting = SUPPORTED_100baseT_Half;
 365			else
 366				return -EINVAL;
 367			break;
 368
 369		case SPEED_10:
 370			if (cmd->base.duplex == DUPLEX_FULL)
 371				setting = SUPPORTED_10baseT_Full;
 372			else if (cmd->base.duplex == DUPLEX_HALF)
 373				setting = SUPPORTED_10baseT_Half;
 374			else
 375				return -EINVAL;
 376			break;
 377		default:
 378			return -EINVAL;
 379		}
 380
 381		if ((setting & supported) == 0)
 382			return -EINVAL;
 383
 384		skge->speed = speed;
 385		skge->duplex = cmd->base.duplex;
 386	}
 387
 388	skge->autoneg = cmd->base.autoneg;
 389	skge->advertising = advertising;
 390
 391	if (netif_running(dev)) {
 392		skge_down(dev);
 393		err = skge_up(dev);
 394		if (err) {
 395			dev_close(dev);
 396			return err;
 397		}
 398	}
 399
 400	return 0;
 401}
 402
 403static void skge_get_drvinfo(struct net_device *dev,
 404			     struct ethtool_drvinfo *info)
 405{
 406	struct skge_port *skge = netdev_priv(dev);
 407
 408	strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
 409	strlcpy(info->version, DRV_VERSION, sizeof(info->version));
 410	strlcpy(info->bus_info, pci_name(skge->hw->pdev),
 411		sizeof(info->bus_info));
 412}
 413
 414static const struct skge_stat {
 415	char 	   name[ETH_GSTRING_LEN];
 416	u16	   xmac_offset;
 417	u16	   gma_offset;
 418} skge_stats[] = {
 419	{ "tx_bytes",		XM_TXO_OK_HI,  GM_TXO_OK_HI },
 420	{ "rx_bytes",		XM_RXO_OK_HI,  GM_RXO_OK_HI },
 421
 422	{ "tx_broadcast",	XM_TXF_BC_OK,  GM_TXF_BC_OK },
 423	{ "rx_broadcast",	XM_RXF_BC_OK,  GM_RXF_BC_OK },
 424	{ "tx_multicast",	XM_TXF_MC_OK,  GM_TXF_MC_OK },
 425	{ "rx_multicast",	XM_RXF_MC_OK,  GM_RXF_MC_OK },
 426	{ "tx_unicast",		XM_TXF_UC_OK,  GM_TXF_UC_OK },
 427	{ "rx_unicast",		XM_RXF_UC_OK,  GM_RXF_UC_OK },
 428	{ "tx_mac_pause",	XM_TXF_MPAUSE, GM_TXF_MPAUSE },
 429	{ "rx_mac_pause",	XM_RXF_MPAUSE, GM_RXF_MPAUSE },
 430
 431	{ "collisions",		XM_TXF_SNG_COL, GM_TXF_SNG_COL },
 432	{ "multi_collisions",	XM_TXF_MUL_COL, GM_TXF_MUL_COL },
 433	{ "aborted",		XM_TXF_ABO_COL, GM_TXF_ABO_COL },
 434	{ "late_collision",	XM_TXF_LAT_COL, GM_TXF_LAT_COL },
 435	{ "fifo_underrun",	XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
 436	{ "fifo_overflow",	XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
 437
 438	{ "rx_toolong",		XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
 439	{ "rx_jabber",		XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
 440	{ "rx_runt",		XM_RXE_RUNT, 	GM_RXE_FRAG },
 441	{ "rx_too_long",	XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
 442	{ "rx_fcs_error",	XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
 443};
 444
 445static int skge_get_sset_count(struct net_device *dev, int sset)
 446{
 447	switch (sset) {
 448	case ETH_SS_STATS:
 449		return ARRAY_SIZE(skge_stats);
 450	default:
 451		return -EOPNOTSUPP;
 452	}
 453}
 454
 455static void skge_get_ethtool_stats(struct net_device *dev,
 456				   struct ethtool_stats *stats, u64 *data)
 457{
 458	struct skge_port *skge = netdev_priv(dev);
 459
 460	if (is_genesis(skge->hw))
 461		genesis_get_stats(skge, data);
 462	else
 463		yukon_get_stats(skge, data);
 464}
 465
 466/* Use hardware MIB variables for critical path statistics and
 467 * transmit feedback not reported at interrupt.
 468 * Other errors are accounted for in interrupt handler.
 469 */
 470static struct net_device_stats *skge_get_stats(struct net_device *dev)
 471{
 472	struct skge_port *skge = netdev_priv(dev);
 473	u64 data[ARRAY_SIZE(skge_stats)];
 474
 475	if (is_genesis(skge->hw))
 476		genesis_get_stats(skge, data);
 477	else
 478		yukon_get_stats(skge, data);
 479
 480	dev->stats.tx_bytes = data[0];
 481	dev->stats.rx_bytes = data[1];
 482	dev->stats.tx_packets = data[2] + data[4] + data[6];
 483	dev->stats.rx_packets = data[3] + data[5] + data[7];
 484	dev->stats.multicast = data[3] + data[5];
 485	dev->stats.collisions = data[10];
 486	dev->stats.tx_aborted_errors = data[12];
 487
 488	return &dev->stats;
 489}
 490
 491static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
 492{
 493	int i;
 494
 495	switch (stringset) {
 496	case ETH_SS_STATS:
 497		for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
 498			memcpy(data + i * ETH_GSTRING_LEN,
 499			       skge_stats[i].name, ETH_GSTRING_LEN);
 500		break;
 501	}
 502}
 503
 504static void skge_get_ring_param(struct net_device *dev,
 505				struct ethtool_ringparam *p)
 506{
 507	struct skge_port *skge = netdev_priv(dev);
 508
 509	p->rx_max_pending = MAX_RX_RING_SIZE;
 510	p->tx_max_pending = MAX_TX_RING_SIZE;
 511
 512	p->rx_pending = skge->rx_ring.count;
 513	p->tx_pending = skge->tx_ring.count;
 514}
 515
 516static int skge_set_ring_param(struct net_device *dev,
 517			       struct ethtool_ringparam *p)
 518{
 519	struct skge_port *skge = netdev_priv(dev);
 520	int err = 0;
 521
 522	if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
 523	    p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
 524		return -EINVAL;
 525
 526	skge->rx_ring.count = p->rx_pending;
 527	skge->tx_ring.count = p->tx_pending;
 528
 529	if (netif_running(dev)) {
 530		skge_down(dev);
 531		err = skge_up(dev);
 532		if (err)
 533			dev_close(dev);
 534	}
 535
 536	return err;
 537}
 538
 539static u32 skge_get_msglevel(struct net_device *netdev)
 540{
 541	struct skge_port *skge = netdev_priv(netdev);
 542	return skge->msg_enable;
 543}
 544
 545static void skge_set_msglevel(struct net_device *netdev, u32 value)
 546{
 547	struct skge_port *skge = netdev_priv(netdev);
 548	skge->msg_enable = value;
 549}
 550
 551static int skge_nway_reset(struct net_device *dev)
 552{
 553	struct skge_port *skge = netdev_priv(dev);
 554
 555	if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
 556		return -EINVAL;
 557
 558	skge_phy_reset(skge);
 559	return 0;
 560}
 561
 562static void skge_get_pauseparam(struct net_device *dev,
 563				struct ethtool_pauseparam *ecmd)
 564{
 565	struct skge_port *skge = netdev_priv(dev);
 566
 567	ecmd->rx_pause = ((skge->flow_control == FLOW_MODE_SYMMETRIC) ||
 568			  (skge->flow_control == FLOW_MODE_SYM_OR_REM));
 569	ecmd->tx_pause = (ecmd->rx_pause ||
 570			  (skge->flow_control == FLOW_MODE_LOC_SEND));
 571
 572	ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
 573}
 574
 575static int skge_set_pauseparam(struct net_device *dev,
 576			       struct ethtool_pauseparam *ecmd)
 577{
 578	struct skge_port *skge = netdev_priv(dev);
 579	struct ethtool_pauseparam old;
 580	int err = 0;
 581
 582	skge_get_pauseparam(dev, &old);
 583
 584	if (ecmd->autoneg != old.autoneg)
 585		skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
 586	else {
 587		if (ecmd->rx_pause && ecmd->tx_pause)
 588			skge->flow_control = FLOW_MODE_SYMMETRIC;
 589		else if (ecmd->rx_pause && !ecmd->tx_pause)
 590			skge->flow_control = FLOW_MODE_SYM_OR_REM;
 591		else if (!ecmd->rx_pause && ecmd->tx_pause)
 592			skge->flow_control = FLOW_MODE_LOC_SEND;
 593		else
 594			skge->flow_control = FLOW_MODE_NONE;
 595	}
 596
 597	if (netif_running(dev)) {
 598		skge_down(dev);
 599		err = skge_up(dev);
 600		if (err) {
 601			dev_close(dev);
 602			return err;
 603		}
 604	}
 605
 606	return 0;
 607}
 608
 609/* Chip internal frequency for clock calculations */
 610static inline u32 hwkhz(const struct skge_hw *hw)
 611{
 612	return is_genesis(hw) ? 53125 : 78125;
 613}
 614
 615/* Chip HZ to microseconds */
 616static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
 617{
 618	return (ticks * 1000) / hwkhz(hw);
 619}
 620
 621/* Microseconds to chip HZ */
 622static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
 623{
 624	return hwkhz(hw) * usec / 1000;
 625}
 626
 627static int skge_get_coalesce(struct net_device *dev,
 628			     struct ethtool_coalesce *ecmd)
 629{
 630	struct skge_port *skge = netdev_priv(dev);
 631	struct skge_hw *hw = skge->hw;
 632	int port = skge->port;
 633
 634	ecmd->rx_coalesce_usecs = 0;
 635	ecmd->tx_coalesce_usecs = 0;
 636
 637	if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
 638		u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
 639		u32 msk = skge_read32(hw, B2_IRQM_MSK);
 640
 641		if (msk & rxirqmask[port])
 642			ecmd->rx_coalesce_usecs = delay;
 643		if (msk & txirqmask[port])
 644			ecmd->tx_coalesce_usecs = delay;
 645	}
 646
 647	return 0;
 648}
 649
 650/* Note: interrupt timer is per board, but can turn on/off per port */
 651static int skge_set_coalesce(struct net_device *dev,
 652			     struct ethtool_coalesce *ecmd)
 653{
 654	struct skge_port *skge = netdev_priv(dev);
 655	struct skge_hw *hw = skge->hw;
 656	int port = skge->port;
 657	u32 msk = skge_read32(hw, B2_IRQM_MSK);
 658	u32 delay = 25;
 659
 660	if (ecmd->rx_coalesce_usecs == 0)
 661		msk &= ~rxirqmask[port];
 662	else if (ecmd->rx_coalesce_usecs < 25 ||
 663		 ecmd->rx_coalesce_usecs > 33333)
 664		return -EINVAL;
 665	else {
 666		msk |= rxirqmask[port];
 667		delay = ecmd->rx_coalesce_usecs;
 668	}
 669
 670	if (ecmd->tx_coalesce_usecs == 0)
 671		msk &= ~txirqmask[port];
 672	else if (ecmd->tx_coalesce_usecs < 25 ||
 673		 ecmd->tx_coalesce_usecs > 33333)
 674		return -EINVAL;
 675	else {
 676		msk |= txirqmask[port];
 677		delay = min(delay, ecmd->rx_coalesce_usecs);
 678	}
 679
 680	skge_write32(hw, B2_IRQM_MSK, msk);
 681	if (msk == 0)
 682		skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
 683	else {
 684		skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
 685		skge_write32(hw, B2_IRQM_CTRL, TIM_START);
 686	}
 687	return 0;
 688}
 689
 690enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
 691static void skge_led(struct skge_port *skge, enum led_mode mode)
 692{
 693	struct skge_hw *hw = skge->hw;
 694	int port = skge->port;
 695
 696	spin_lock_bh(&hw->phy_lock);
 697	if (is_genesis(hw)) {
 698		switch (mode) {
 699		case LED_MODE_OFF:
 700			if (hw->phy_type == SK_PHY_BCOM)
 701				xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
 702			else {
 703				skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
 704				skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
 705			}
 706			skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
 707			skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
 708			skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
 709			break;
 710
 711		case LED_MODE_ON:
 712			skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
 713			skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
 714
 715			skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
 716			skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
 717
 718			break;
 719
 720		case LED_MODE_TST:
 721			skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
 722			skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
 723			skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
 724
 725			if (hw->phy_type == SK_PHY_BCOM)
 726				xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
 727			else {
 728				skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
 729				skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
 730				skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
 731			}
 732
 733		}
 734	} else {
 735		switch (mode) {
 736		case LED_MODE_OFF:
 737			gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
 738			gm_phy_write(hw, port, PHY_MARV_LED_OVER,
 739				     PHY_M_LED_MO_DUP(MO_LED_OFF)  |
 740				     PHY_M_LED_MO_10(MO_LED_OFF)   |
 741				     PHY_M_LED_MO_100(MO_LED_OFF)  |
 742				     PHY_M_LED_MO_1000(MO_LED_OFF) |
 743				     PHY_M_LED_MO_RX(MO_LED_OFF));
 744			break;
 745		case LED_MODE_ON:
 746			gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
 747				     PHY_M_LED_PULS_DUR(PULS_170MS) |
 748				     PHY_M_LED_BLINK_RT(BLINK_84MS) |
 749				     PHY_M_LEDC_TX_CTRL |
 750				     PHY_M_LEDC_DP_CTRL);
 751
 752			gm_phy_write(hw, port, PHY_MARV_LED_OVER,
 753				     PHY_M_LED_MO_RX(MO_LED_OFF) |
 754				     (skge->speed == SPEED_100 ?
 755				      PHY_M_LED_MO_100(MO_LED_ON) : 0));
 756			break;
 757		case LED_MODE_TST:
 758			gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
 759			gm_phy_write(hw, port, PHY_MARV_LED_OVER,
 760				     PHY_M_LED_MO_DUP(MO_LED_ON)  |
 761				     PHY_M_LED_MO_10(MO_LED_ON)   |
 762				     PHY_M_LED_MO_100(MO_LED_ON)  |
 763				     PHY_M_LED_MO_1000(MO_LED_ON) |
 764				     PHY_M_LED_MO_RX(MO_LED_ON));
 765		}
 766	}
 767	spin_unlock_bh(&hw->phy_lock);
 768}
 769
 770/* blink LED's for finding board */
 771static int skge_set_phys_id(struct net_device *dev,
 772			    enum ethtool_phys_id_state state)
 773{
 774	struct skge_port *skge = netdev_priv(dev);
 775
 776	switch (state) {
 777	case ETHTOOL_ID_ACTIVE:
 778		return 2;	/* cycle on/off twice per second */
 779
 780	case ETHTOOL_ID_ON:
 781		skge_led(skge, LED_MODE_TST);
 782		break;
 783
 784	case ETHTOOL_ID_OFF:
 785		skge_led(skge, LED_MODE_OFF);
 786		break;
 787
 788	case ETHTOOL_ID_INACTIVE:
 789		/* back to regular LED state */
 790		skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
 791	}
 792
 793	return 0;
 794}
 795
 796static int skge_get_eeprom_len(struct net_device *dev)
 797{
 798	struct skge_port *skge = netdev_priv(dev);
 799	u32 reg2;
 800
 801	pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, &reg2);
 802	return 1 << (((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
 803}
 804
 805static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
 806{
 807	u32 val;
 808
 809	pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
 810
 811	do {
 812		pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
 813	} while (!(offset & PCI_VPD_ADDR_F));
 814
 815	pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
 816	return val;
 817}
 818
 819static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
 820{
 821	pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
 822	pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
 823			      offset | PCI_VPD_ADDR_F);
 824
 825	do {
 826		pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
 827	} while (offset & PCI_VPD_ADDR_F);
 828}
 829
 830static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
 831			   u8 *data)
 832{
 833	struct skge_port *skge = netdev_priv(dev);
 834	struct pci_dev *pdev = skge->hw->pdev;
 835	int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
 836	int length = eeprom->len;
 837	u16 offset = eeprom->offset;
 838
 839	if (!cap)
 840		return -EINVAL;
 841
 842	eeprom->magic = SKGE_EEPROM_MAGIC;
 843
 844	while (length > 0) {
 845		u32 val = skge_vpd_read(pdev, cap, offset);
 846		int n = min_t(int, length, sizeof(val));
 847
 848		memcpy(data, &val, n);
 849		length -= n;
 850		data += n;
 851		offset += n;
 852	}
 853	return 0;
 854}
 855
 856static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
 857			   u8 *data)
 858{
 859	struct skge_port *skge = netdev_priv(dev);
 860	struct pci_dev *pdev = skge->hw->pdev;
 861	int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
 862	int length = eeprom->len;
 863	u16 offset = eeprom->offset;
 864
 865	if (!cap)
 866		return -EINVAL;
 867
 868	if (eeprom->magic != SKGE_EEPROM_MAGIC)
 869		return -EINVAL;
 870
 871	while (length > 0) {
 872		u32 val;
 873		int n = min_t(int, length, sizeof(val));
 874
 875		if (n < sizeof(val))
 876			val = skge_vpd_read(pdev, cap, offset);
 877		memcpy(&val, data, n);
 878
 879		skge_vpd_write(pdev, cap, offset, val);
 880
 881		length -= n;
 882		data += n;
 883		offset += n;
 884	}
 885	return 0;
 886}
 887
 888static const struct ethtool_ops skge_ethtool_ops = {
 889	.get_drvinfo	= skge_get_drvinfo,
 890	.get_regs_len	= skge_get_regs_len,
 891	.get_regs	= skge_get_regs,
 892	.get_wol	= skge_get_wol,
 893	.set_wol	= skge_set_wol,
 894	.get_msglevel	= skge_get_msglevel,
 895	.set_msglevel	= skge_set_msglevel,
 896	.nway_reset	= skge_nway_reset,
 897	.get_link	= ethtool_op_get_link,
 898	.get_eeprom_len	= skge_get_eeprom_len,
 899	.get_eeprom	= skge_get_eeprom,
 900	.set_eeprom	= skge_set_eeprom,
 901	.get_ringparam	= skge_get_ring_param,
 902	.set_ringparam	= skge_set_ring_param,
 903	.get_pauseparam = skge_get_pauseparam,
 904	.set_pauseparam = skge_set_pauseparam,
 905	.get_coalesce	= skge_get_coalesce,
 906	.set_coalesce	= skge_set_coalesce,
 907	.get_strings	= skge_get_strings,
 908	.set_phys_id	= skge_set_phys_id,
 909	.get_sset_count = skge_get_sset_count,
 910	.get_ethtool_stats = skge_get_ethtool_stats,
 911	.get_link_ksettings = skge_get_link_ksettings,
 912	.set_link_ksettings = skge_set_link_ksettings,
 913};
 914
 915/*
 916 * Allocate ring elements and chain them together
 917 * One-to-one association of board descriptors with ring elements
 918 */
 919static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
 920{
 921	struct skge_tx_desc *d;
 922	struct skge_element *e;
 923	int i;
 924
 925	ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
 926	if (!ring->start)
 927		return -ENOMEM;
 928
 929	for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
 930		e->desc = d;
 931		if (i == ring->count - 1) {
 932			e->next = ring->start;
 933			d->next_offset = base;
 934		} else {
 935			e->next = e + 1;
 936			d->next_offset = base + (i+1) * sizeof(*d);
 937		}
 938	}
 939	ring->to_use = ring->to_clean = ring->start;
 940
 941	return 0;
 942}
 943
 944/* Allocate and setup a new buffer for receiving */
 945static int skge_rx_setup(struct skge_port *skge, struct skge_element *e,
 946			 struct sk_buff *skb, unsigned int bufsize)
 947{
 948	struct skge_rx_desc *rd = e->desc;
 949	dma_addr_t map;
 950
 951	map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
 952			     PCI_DMA_FROMDEVICE);
 953
 954	if (pci_dma_mapping_error(skge->hw->pdev, map))
 955		return -1;
 956
 957	rd->dma_lo = lower_32_bits(map);
 958	rd->dma_hi = upper_32_bits(map);
 959	e->skb = skb;
 960	rd->csum1_start = ETH_HLEN;
 961	rd->csum2_start = ETH_HLEN;
 962	rd->csum1 = 0;
 963	rd->csum2 = 0;
 964
 965	wmb();
 966
 967	rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
 968	dma_unmap_addr_set(e, mapaddr, map);
 969	dma_unmap_len_set(e, maplen, bufsize);
 970	return 0;
 971}
 972
 973/* Resume receiving using existing skb,
 974 * Note: DMA address is not changed by chip.
 975 * 	 MTU not changed while receiver active.
 976 */
 977static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
 978{
 979	struct skge_rx_desc *rd = e->desc;
 980
 981	rd->csum2 = 0;
 982	rd->csum2_start = ETH_HLEN;
 983
 984	wmb();
 985
 986	rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
 987}
 988
 989
 990/* Free all  buffers in receive ring, assumes receiver stopped */
 991static void skge_rx_clean(struct skge_port *skge)
 992{
 993	struct skge_hw *hw = skge->hw;
 994	struct skge_ring *ring = &skge->rx_ring;
 995	struct skge_element *e;
 996
 997	e = ring->start;
 998	do {
 999		struct skge_rx_desc *rd = e->desc;
1000		rd->control = 0;
1001		if (e->skb) {
1002			pci_unmap_single(hw->pdev,
1003					 dma_unmap_addr(e, mapaddr),
1004					 dma_unmap_len(e, maplen),
1005					 PCI_DMA_FROMDEVICE);
1006			dev_kfree_skb(e->skb);
1007			e->skb = NULL;
1008		}
1009	} while ((e = e->next) != ring->start);
1010}
1011
1012
1013/* Allocate buffers for receive ring
1014 * For receive:  to_clean is next received frame.
1015 */
1016static int skge_rx_fill(struct net_device *dev)
1017{
1018	struct skge_port *skge = netdev_priv(dev);
1019	struct skge_ring *ring = &skge->rx_ring;
1020	struct skge_element *e;
1021
1022	e = ring->start;
1023	do {
1024		struct sk_buff *skb;
1025
1026		skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
1027					 GFP_KERNEL);
1028		if (!skb)
1029			return -ENOMEM;
1030
1031		skb_reserve(skb, NET_IP_ALIGN);
1032		if (skge_rx_setup(skge, e, skb, skge->rx_buf_size) < 0) {
1033			dev_kfree_skb(skb);
1034			return -EIO;
1035		}
1036	} while ((e = e->next) != ring->start);
1037
1038	ring->to_clean = ring->start;
1039	return 0;
1040}
1041
1042static const char *skge_pause(enum pause_status status)
1043{
1044	switch (status) {
1045	case FLOW_STAT_NONE:
1046		return "none";
1047	case FLOW_STAT_REM_SEND:
1048		return "rx only";
1049	case FLOW_STAT_LOC_SEND:
1050		return "tx_only";
1051	case FLOW_STAT_SYMMETRIC:		/* Both station may send PAUSE */
1052		return "both";
1053	default:
1054		return "indeterminated";
1055	}
1056}
1057
1058
1059static void skge_link_up(struct skge_port *skge)
1060{
1061	skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
1062		    LED_BLK_OFF|LED_SYNC_OFF|LED_REG_ON);
1063
1064	netif_carrier_on(skge->netdev);
1065	netif_wake_queue(skge->netdev);
1066
1067	netif_info(skge, link, skge->netdev,
1068		   "Link is up at %d Mbps, %s duplex, flow control %s\n",
1069		   skge->speed,
1070		   skge->duplex == DUPLEX_FULL ? "full" : "half",
1071		   skge_pause(skge->flow_status));
1072}
1073
1074static void skge_link_down(struct skge_port *skge)
1075{
1076	skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF);
1077	netif_carrier_off(skge->netdev);
1078	netif_stop_queue(skge->netdev);
1079
1080	netif_info(skge, link, skge->netdev, "Link is down\n");
1081}
1082
1083static void xm_link_down(struct skge_hw *hw, int port)
1084{
1085	struct net_device *dev = hw->dev[port];
1086	struct skge_port *skge = netdev_priv(dev);
1087
1088	xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1089
1090	if (netif_carrier_ok(dev))
1091		skge_link_down(skge);
1092}
1093
1094static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1095{
1096	int i;
1097
1098	xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1099	*val = xm_read16(hw, port, XM_PHY_DATA);
1100
1101	if (hw->phy_type == SK_PHY_XMAC)
1102		goto ready;
1103
1104	for (i = 0; i < PHY_RETRIES; i++) {
1105		if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
1106			goto ready;
1107		udelay(1);
1108	}
1109
1110	return -ETIMEDOUT;
1111 ready:
1112	*val = xm_read16(hw, port, XM_PHY_DATA);
1113
1114	return 0;
1115}
1116
1117static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1118{
1119	u16 v = 0;
1120	if (__xm_phy_read(hw, port, reg, &v))
1121		pr_warn("%s: phy read timed out\n", hw->dev[port]->name);
1122	return v;
1123}
1124
1125static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1126{
1127	int i;
1128
1129	xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1130	for (i = 0; i < PHY_RETRIES; i++) {
1131		if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1132			goto ready;
1133		udelay(1);
1134	}
1135	return -EIO;
1136
1137 ready:
1138	xm_write16(hw, port, XM_PHY_DATA, val);
1139	for (i = 0; i < PHY_RETRIES; i++) {
1140		if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1141			return 0;
1142		udelay(1);
1143	}
1144	return -ETIMEDOUT;
1145}
1146
1147static void genesis_init(struct skge_hw *hw)
1148{
1149	/* set blink source counter */
1150	skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1151	skge_write8(hw, B2_BSC_CTRL, BSC_START);
1152
1153	/* configure mac arbiter */
1154	skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1155
1156	/* configure mac arbiter timeout values */
1157	skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1158	skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1159	skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1160	skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1161
1162	skge_write8(hw, B3_MA_RCINI_RX1, 0);
1163	skge_write8(hw, B3_MA_RCINI_RX2, 0);
1164	skge_write8(hw, B3_MA_RCINI_TX1, 0);
1165	skge_write8(hw, B3_MA_RCINI_TX2, 0);
1166
1167	/* configure packet arbiter timeout */
1168	skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1169	skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1170	skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1171	skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1172	skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1173}
1174
1175static void genesis_reset(struct skge_hw *hw, int port)
1176{
1177	static const u8 zero[8]  = { 0 };
1178	u32 reg;
1179
1180	skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1181
1182	/* reset the statistics module */
1183	xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1184	xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1185	xm_write32(hw, port, XM_MODE, 0);		/* clear Mode Reg */
1186	xm_write16(hw, port, XM_TX_CMD, 0);	/* reset TX CMD Reg */
1187	xm_write16(hw, port, XM_RX_CMD, 0);	/* reset RX CMD Reg */
1188
1189	/* disable Broadcom PHY IRQ */
1190	if (hw->phy_type == SK_PHY_BCOM)
1191		xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1192
1193	xm_outhash(hw, port, XM_HSM, zero);
1194
1195	/* Flush TX and RX fifo */
1196	reg = xm_read32(hw, port, XM_MODE);
1197	xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
1198	xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
1199}
1200
1201/* Convert mode to MII values  */
1202static const u16 phy_pause_map[] = {
1203	[FLOW_MODE_NONE] =	0,
1204	[FLOW_MODE_LOC_SEND] =	PHY_AN_PAUSE_ASYM,
1205	[FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1206	[FLOW_MODE_SYM_OR_REM]  = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1207};
1208
1209/* special defines for FIBER (88E1011S only) */
1210static const u16 fiber_pause_map[] = {
1211	[FLOW_MODE_NONE]	= PHY_X_P_NO_PAUSE,
1212	[FLOW_MODE_LOC_SEND]	= PHY_X_P_ASYM_MD,
1213	[FLOW_MODE_SYMMETRIC]	= PHY_X_P_SYM_MD,
1214	[FLOW_MODE_SYM_OR_REM]	= PHY_X_P_BOTH_MD,
1215};
1216
1217
1218/* Check status of Broadcom phy link */
1219static void bcom_check_link(struct skge_hw *hw, int port)
1220{
1221	struct net_device *dev = hw->dev[port];
1222	struct skge_port *skge = netdev_priv(dev);
1223	u16 status;
1224
1225	/* read twice because of latch */
1226	xm_phy_read(hw, port, PHY_BCOM_STAT);
1227	status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1228
1229	if ((status & PHY_ST_LSYNC) == 0) {
1230		xm_link_down(hw, port);
1231		return;
1232	}
1233
1234	if (skge->autoneg == AUTONEG_ENABLE) {
1235		u16 lpa, aux;
1236
1237		if (!(status & PHY_ST_AN_OVER))
1238			return;
1239
1240		lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1241		if (lpa & PHY_B_AN_RF) {
1242			netdev_notice(dev, "remote fault\n");
1243			return;
1244		}
1245
1246		aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1247
1248		/* Check Duplex mismatch */
1249		switch (aux & PHY_B_AS_AN_RES_MSK) {
1250		case PHY_B_RES_1000FD:
1251			skge->duplex = DUPLEX_FULL;
1252			break;
1253		case PHY_B_RES_1000HD:
1254			skge->duplex = DUPLEX_HALF;
1255			break;
1256		default:
1257			netdev_notice(dev, "duplex mismatch\n");
1258			return;
1259		}
1260
1261		/* We are using IEEE 802.3z/D5.0 Table 37-4 */
1262		switch (aux & PHY_B_AS_PAUSE_MSK) {
1263		case PHY_B_AS_PAUSE_MSK:
1264			skge->flow_status = FLOW_STAT_SYMMETRIC;
1265			break;
1266		case PHY_B_AS_PRR:
1267			skge->flow_status = FLOW_STAT_REM_SEND;
1268			break;
1269		case PHY_B_AS_PRT:
1270			skge->flow_status = FLOW_STAT_LOC_SEND;
1271			break;
1272		default:
1273			skge->flow_status = FLOW_STAT_NONE;
1274		}
1275		skge->speed = SPEED_1000;
1276	}
1277
1278	if (!netif_carrier_ok(dev))
1279		genesis_link_up(skge);
1280}
1281
1282/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1283 * Phy on for 100 or 10Mbit operation
1284 */
1285static void bcom_phy_init(struct skge_port *skge)
1286{
1287	struct skge_hw *hw = skge->hw;
1288	int port = skge->port;
1289	int i;
1290	u16 id1, r, ext, ctl;
1291
1292	/* magic workaround patterns for Broadcom */
1293	static const struct {
1294		u16 reg;
1295		u16 val;
1296	} A1hack[] = {
1297		{ 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1298		{ 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1299		{ 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1300		{ 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1301	}, C0hack[] = {
1302		{ 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1303		{ 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1304	};
1305
1306	/* read Id from external PHY (all have the same address) */
1307	id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1308
1309	/* Optimize MDIO transfer by suppressing preamble. */
1310	r = xm_read16(hw, port, XM_MMU_CMD);
1311	r |=  XM_MMU_NO_PRE;
1312	xm_write16(hw, port, XM_MMU_CMD, r);
1313
1314	switch (id1) {
1315	case PHY_BCOM_ID1_C0:
1316		/*
1317		 * Workaround BCOM Errata for the C0 type.
1318		 * Write magic patterns to reserved registers.
1319		 */
1320		for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1321			xm_phy_write(hw, port,
1322				     C0hack[i].reg, C0hack[i].val);
1323
1324		break;
1325	case PHY_BCOM_ID1_A1:
1326		/*
1327		 * Workaround BCOM Errata for the A1 type.
1328		 * Write magic patterns to reserved registers.
1329		 */
1330		for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1331			xm_phy_write(hw, port,
1332				     A1hack[i].reg, A1hack[i].val);
1333		break;
1334	}
1335
1336	/*
1337	 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1338	 * Disable Power Management after reset.
1339	 */
1340	r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1341	r |= PHY_B_AC_DIS_PM;
1342	xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1343
1344	/* Dummy read */
1345	xm_read16(hw, port, XM_ISRC);
1346
1347	ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1348	ctl = PHY_CT_SP1000;	/* always 1000mbit */
1349
1350	if (skge->autoneg == AUTONEG_ENABLE) {
1351		/*
1352		 * Workaround BCOM Errata #1 for the C5 type.
1353		 * 1000Base-T Link Acquisition Failure in Slave Mode
1354		 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1355		 */
1356		u16 adv = PHY_B_1000C_RD;
1357		if (skge->advertising & ADVERTISED_1000baseT_Half)
1358			adv |= PHY_B_1000C_AHD;
1359		if (skge->advertising & ADVERTISED_1000baseT_Full)
1360			adv |= PHY_B_1000C_AFD;
1361		xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1362
1363		ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1364	} else {
1365		if (skge->duplex == DUPLEX_FULL)
1366			ctl |= PHY_CT_DUP_MD;
1367		/* Force to slave */
1368		xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1369	}
1370
1371	/* Set autonegotiation pause parameters */
1372	xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1373		     phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1374
1375	/* Handle Jumbo frames */
1376	if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1377		xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1378			     PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1379
1380		ext |= PHY_B_PEC_HIGH_LA;
1381
1382	}
1383
1384	xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1385	xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1386
1387	/* Use link status change interrupt */
1388	xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1389}
1390
1391static void xm_phy_init(struct skge_port *skge)
1392{
1393	struct skge_hw *hw = skge->hw;
1394	int port = skge->port;
1395	u16 ctrl = 0;
1396
1397	if (skge->autoneg == AUTONEG_ENABLE) {
1398		if (skge->advertising & ADVERTISED_1000baseT_Half)
1399			ctrl |= PHY_X_AN_HD;
1400		if (skge->advertising & ADVERTISED_1000baseT_Full)
1401			ctrl |= PHY_X_AN_FD;
1402
1403		ctrl |= fiber_pause_map[skge->flow_control];
1404
1405		xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1406
1407		/* Restart Auto-negotiation */
1408		ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1409	} else {
1410		/* Set DuplexMode in Config register */
1411		if (skge->duplex == DUPLEX_FULL)
1412			ctrl |= PHY_CT_DUP_MD;
1413		/*
1414		 * Do NOT enable Auto-negotiation here. This would hold
1415		 * the link down because no IDLEs are transmitted
1416		 */
1417	}
1418
1419	xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1420
1421	/* Poll PHY for status changes */
1422	mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1423}
1424
1425static int xm_check_link(struct net_device *dev)
1426{
1427	struct skge_port *skge = netdev_priv(dev);
1428	struct skge_hw *hw = skge->hw;
1429	int port = skge->port;
1430	u16 status;
1431
1432	/* read twice because of latch */
1433	xm_phy_read(hw, port, PHY_XMAC_STAT);
1434	status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1435
1436	if ((status & PHY_ST_LSYNC) == 0) {
1437		xm_link_down(hw, port);
1438		return 0;
1439	}
1440
1441	if (skge->autoneg == AUTONEG_ENABLE) {
1442		u16 lpa, res;
1443
1444		if (!(status & PHY_ST_AN_OVER))
1445			return 0;
1446
1447		lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1448		if (lpa & PHY_B_AN_RF) {
1449			netdev_notice(dev, "remote fault\n");
1450			return 0;
1451		}
1452
1453		res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1454
1455		/* Check Duplex mismatch */
1456		switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1457		case PHY_X_RS_FD:
1458			skge->duplex = DUPLEX_FULL;
1459			break;
1460		case PHY_X_RS_HD:
1461			skge->duplex = DUPLEX_HALF;
1462			break;
1463		default:
1464			netdev_notice(dev, "duplex mismatch\n");
1465			return 0;
1466		}
1467
1468		/* We are using IEEE 802.3z/D5.0 Table 37-4 */
1469		if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1470		     skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1471		    (lpa & PHY_X_P_SYM_MD))
1472			skge->flow_status = FLOW_STAT_SYMMETRIC;
1473		else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1474			 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1475			/* Enable PAUSE receive, disable PAUSE transmit */
1476			skge->flow_status  = FLOW_STAT_REM_SEND;
1477		else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1478			 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1479			/* Disable PAUSE receive, enable PAUSE transmit */
1480			skge->flow_status = FLOW_STAT_LOC_SEND;
1481		else
1482			skge->flow_status = FLOW_STAT_NONE;
1483
1484		skge->speed = SPEED_1000;
1485	}
1486
1487	if (!netif_carrier_ok(dev))
1488		genesis_link_up(skge);
1489	return 1;
1490}
1491
1492/* Poll to check for link coming up.
1493 *
1494 * Since internal PHY is wired to a level triggered pin, can't
1495 * get an interrupt when carrier is detected, need to poll for
1496 * link coming up.
1497 */
1498static void xm_link_timer(struct timer_list *t)
1499{
1500	struct skge_port *skge = from_timer(skge, t, link_timer);
1501	struct net_device *dev = skge->netdev;
1502	struct skge_hw *hw = skge->hw;
1503	int port = skge->port;
1504	int i;
1505	unsigned long flags;
1506
1507	if (!netif_running(dev))
1508		return;
1509
1510	spin_lock_irqsave(&hw->phy_lock, flags);
1511
1512	/*
1513	 * Verify that the link by checking GPIO register three times.
1514	 * This pin has the signal from the link_sync pin connected to it.
1515	 */
1516	for (i = 0; i < 3; i++) {
1517		if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1518			goto link_down;
1519	}
1520
1521	/* Re-enable interrupt to detect link down */
1522	if (xm_check_link(dev)) {
1523		u16 msk = xm_read16(hw, port, XM_IMSK);
1524		msk &= ~XM_IS_INP_ASS;
1525		xm_write16(hw, port, XM_IMSK, msk);
1526		xm_read16(hw, port, XM_ISRC);
1527	} else {
1528link_down:
1529		mod_timer(&skge->link_timer,
1530			  round_jiffies(jiffies + LINK_HZ));
1531	}
1532	spin_unlock_irqrestore(&hw->phy_lock, flags);
1533}
1534
1535static void genesis_mac_init(struct skge_hw *hw, int port)
1536{
1537	struct net_device *dev = hw->dev[port];
1538	struct skge_port *skge = netdev_priv(dev);
1539	int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1540	int i;
1541	u32 r;
1542	static const u8 zero[6]  = { 0 };
1543
1544	for (i = 0; i < 10; i++) {
1545		skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1546			     MFF_SET_MAC_RST);
1547		if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1548			goto reset_ok;
1549		udelay(1);
1550	}
1551
1552	netdev_warn(dev, "genesis reset failed\n");
1553
1554 reset_ok:
1555	/* Unreset the XMAC. */
1556	skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1557
1558	/*
1559	 * Perform additional initialization for external PHYs,
1560	 * namely for the 1000baseTX cards that use the XMAC's
1561	 * GMII mode.
1562	 */
1563	if (hw->phy_type != SK_PHY_XMAC) {
1564		/* Take external Phy out of reset */
1565		r = skge_read32(hw, B2_GP_IO);
1566		if (port == 0)
1567			r |= GP_DIR_0|GP_IO_0;
1568		else
1569			r |= GP_DIR_2|GP_IO_2;
1570
1571		skge_write32(hw, B2_GP_IO, r);
1572
1573		/* Enable GMII interface */
1574		xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1575	}
1576
1577
1578	switch (hw->phy_type) {
1579	case SK_PHY_XMAC:
1580		xm_phy_init(skge);
1581		break;
1582	case SK_PHY_BCOM:
1583		bcom_phy_init(skge);
1584		bcom_check_link(hw, port);
1585	}
1586
1587	/* Set Station Address */
1588	xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1589
1590	/* We don't use match addresses so clear */
1591	for (i = 1; i < 16; i++)
1592		xm_outaddr(hw, port, XM_EXM(i), zero);
1593
1594	/* Clear MIB counters */
1595	xm_write16(hw, port, XM_STAT_CMD,
1596			XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1597	/* Clear two times according to Errata #3 */
1598	xm_write16(hw, port, XM_STAT_CMD,
1599			XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1600
1601	/* configure Rx High Water Mark (XM_RX_HI_WM) */
1602	xm_write16(hw, port, XM_RX_HI_WM, 1450);
1603
1604	/* We don't need the FCS appended to the packet. */
1605	r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1606	if (jumbo)
1607		r |= XM_RX_BIG_PK_OK;
1608
1609	if (skge->duplex == DUPLEX_HALF) {
1610		/*
1611		 * If in manual half duplex mode the other side might be in
1612		 * full duplex mode, so ignore if a carrier extension is not seen
1613		 * on frames received
1614		 */
1615		r |= XM_RX_DIS_CEXT;
1616	}
1617	xm_write16(hw, port, XM_RX_CMD, r);
1618
1619	/* We want short frames padded to 60 bytes. */
1620	xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1621
1622	/* Increase threshold for jumbo frames on dual port */
1623	if (hw->ports > 1 && jumbo)
1624		xm_write16(hw, port, XM_TX_THR, 1020);
1625	else
1626		xm_write16(hw, port, XM_TX_THR, 512);
1627
1628	/*
1629	 * Enable the reception of all error frames. This is is
1630	 * a necessary evil due to the design of the XMAC. The
1631	 * XMAC's receive FIFO is only 8K in size, however jumbo
1632	 * frames can be up to 9000 bytes in length. When bad
1633	 * frame filtering is enabled, the XMAC's RX FIFO operates
1634	 * in 'store and forward' mode. For this to work, the
1635	 * entire frame has to fit into the FIFO, but that means
1636	 * that jumbo frames larger than 8192 bytes will be
1637	 * truncated. Disabling all bad frame filtering causes
1638	 * the RX FIFO to operate in streaming mode, in which
1639	 * case the XMAC will start transferring frames out of the
1640	 * RX FIFO as soon as the FIFO threshold is reached.
1641	 */
1642	xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1643
1644
1645	/*
1646	 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1647	 *	- Enable all bits excepting 'Octets Rx OK Low CntOv'
1648	 *	  and 'Octets Rx OK Hi Cnt Ov'.
1649	 */
1650	xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1651
1652	/*
1653	 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1654	 *	- Enable all bits excepting 'Octets Tx OK Low CntOv'
1655	 *	  and 'Octets Tx OK Hi Cnt Ov'.
1656	 */
1657	xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1658
1659	/* Configure MAC arbiter */
1660	skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1661
1662	/* configure timeout values */
1663	skge_write8(hw, B3_MA_TOINI_RX1, 72);
1664	skge_write8(hw, B3_MA_TOINI_RX2, 72);
1665	skge_write8(hw, B3_MA_TOINI_TX1, 72);
1666	skge_write8(hw, B3_MA_TOINI_TX2, 72);
1667
1668	skge_write8(hw, B3_MA_RCINI_RX1, 0);
1669	skge_write8(hw, B3_MA_RCINI_RX2, 0);
1670	skge_write8(hw, B3_MA_RCINI_TX1, 0);
1671	skge_write8(hw, B3_MA_RCINI_TX2, 0);
1672
1673	/* Configure Rx MAC FIFO */
1674	skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1675	skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1676	skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1677
1678	/* Configure Tx MAC FIFO */
1679	skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1680	skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1681	skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1682
1683	if (jumbo) {
1684		/* Enable frame flushing if jumbo frames used */
1685		skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
1686	} else {
1687		/* enable timeout timers if normal frames */
1688		skge_write16(hw, B3_PA_CTRL,
1689			     (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1690	}
1691}
1692
1693static void genesis_stop(struct skge_port *skge)
1694{
1695	struct skge_hw *hw = skge->hw;
1696	int port = skge->port;
1697	unsigned retries = 1000;
1698	u16 cmd;
1699
1700	/* Disable Tx and Rx */
1701	cmd = xm_read16(hw, port, XM_MMU_CMD);
1702	cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1703	xm_write16(hw, port, XM_MMU_CMD, cmd);
1704
1705	genesis_reset(hw, port);
1706
1707	/* Clear Tx packet arbiter timeout IRQ */
1708	skge_write16(hw, B3_PA_CTRL,
1709		     port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1710
1711	/* Reset the MAC */
1712	skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1713	do {
1714		skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1715		if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1716			break;
1717	} while (--retries > 0);
1718
1719	/* For external PHYs there must be special handling */
1720	if (hw->phy_type != SK_PHY_XMAC) {
1721		u32 reg = skge_read32(hw, B2_GP_IO);
1722		if (port == 0) {
1723			reg |= GP_DIR_0;
1724			reg &= ~GP_IO_0;
1725		} else {
1726			reg |= GP_DIR_2;
1727			reg &= ~GP_IO_2;
1728		}
1729		skge_write32(hw, B2_GP_IO, reg);
1730		skge_read32(hw, B2_GP_IO);
1731	}
1732
1733	xm_write16(hw, port, XM_MMU_CMD,
1734			xm_read16(hw, port, XM_MMU_CMD)
1735			& ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1736
1737	xm_read16(hw, port, XM_MMU_CMD);
1738}
1739
1740
1741static void genesis_get_stats(struct skge_port *skge, u64 *data)
1742{
1743	struct skge_hw *hw = skge->hw;
1744	int port = skge->port;
1745	int i;
1746	unsigned long timeout = jiffies + HZ;
1747
1748	xm_write16(hw, port,
1749			XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1750
1751	/* wait for update to complete */
1752	while (xm_read16(hw, port, XM_STAT_CMD)
1753	       & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1754		if (time_after(jiffies, timeout))
1755			break;
1756		udelay(10);
1757	}
1758
1759	/* special case for 64 bit octet counter */
1760	data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1761		| xm_read32(hw, port, XM_TXO_OK_LO);
1762	data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1763		| xm_read32(hw, port, XM_RXO_OK_LO);
1764
1765	for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1766		data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1767}
1768
1769static void genesis_mac_intr(struct skge_hw *hw, int port)
1770{
1771	struct net_device *dev = hw->dev[port];
1772	struct skge_port *skge = netdev_priv(dev);
1773	u16 status = xm_read16(hw, port, XM_ISRC);
1774
1775	netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1776		     "mac interrupt status 0x%x\n", status);
1777
1778	if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
1779		xm_link_down(hw, port);
1780		mod_timer(&skge->link_timer, jiffies + 1);
1781	}
1782
1783	if (status & XM_IS_TXF_UR) {
1784		xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1785		++dev->stats.tx_fifo_errors;
1786	}
1787}
1788
1789static void genesis_link_up(struct skge_port *skge)
1790{
1791	struct skge_hw *hw = skge->hw;
1792	int port = skge->port;
1793	u16 cmd, msk;
1794	u32 mode;
1795
1796	cmd = xm_read16(hw, port, XM_MMU_CMD);
1797
1798	/*
1799	 * enabling pause frame reception is required for 1000BT
1800	 * because the XMAC is not reset if the link is going down
1801	 */
1802	if (skge->flow_status == FLOW_STAT_NONE ||
1803	    skge->flow_status == FLOW_STAT_LOC_SEND)
1804		/* Disable Pause Frame Reception */
1805		cmd |= XM_MMU_IGN_PF;
1806	else
1807		/* Enable Pause Frame Reception */
1808		cmd &= ~XM_MMU_IGN_PF;
1809
1810	xm_write16(hw, port, XM_MMU_CMD, cmd);
1811
1812	mode = xm_read32(hw, port, XM_MODE);
1813	if (skge->flow_status == FLOW_STAT_SYMMETRIC ||
1814	    skge->flow_status == FLOW_STAT_LOC_SEND) {
1815		/*
1816		 * Configure Pause Frame Generation
1817		 * Use internal and external Pause Frame Generation.
1818		 * Sending pause frames is edge triggered.
1819		 * Send a Pause frame with the maximum pause time if
1820		 * internal oder external FIFO full condition occurs.
1821		 * Send a zero pause time frame to re-start transmission.
1822		 */
1823		/* XM_PAUSE_DA = '010000C28001' (default) */
1824		/* XM_MAC_PTIME = 0xffff (maximum) */
1825		/* remember this value is defined in big endian (!) */
1826		xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1827
1828		mode |= XM_PAUSE_MODE;
1829		skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1830	} else {
1831		/*
1832		 * disable pause frame generation is required for 1000BT
1833		 * because the XMAC is not reset if the link is going down
1834		 */
1835		/* Disable Pause Mode in Mode Register */
1836		mode &= ~XM_PAUSE_MODE;
1837
1838		skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1839	}
1840
1841	xm_write32(hw, port, XM_MODE, mode);
1842
1843	/* Turn on detection of Tx underrun */
1844	msk = xm_read16(hw, port, XM_IMSK);
1845	msk &= ~XM_IS_TXF_UR;
1846	xm_write16(hw, port, XM_IMSK, msk);
1847
1848	xm_read16(hw, port, XM_ISRC);
1849
1850	/* get MMU Command Reg. */
1851	cmd = xm_read16(hw, port, XM_MMU_CMD);
1852	if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1853		cmd |= XM_MMU_GMII_FD;
1854
1855	/*
1856	 * Workaround BCOM Errata (#10523) for all BCom Phys
1857	 * Enable Power Management after link up
1858	 */
1859	if (hw->phy_type == SK_PHY_BCOM) {
1860		xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1861			     xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1862			     & ~PHY_B_AC_DIS_PM);
1863		xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1864	}
1865
1866	/* enable Rx/Tx */
1867	xm_write16(hw, port, XM_MMU_CMD,
1868			cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1869	skge_link_up(skge);
1870}
1871
1872
1873static inline void bcom_phy_intr(struct skge_port *skge)
1874{
1875	struct skge_hw *hw = skge->hw;
1876	int port = skge->port;
1877	u16 isrc;
1878
1879	isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1880	netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1881		     "phy interrupt status 0x%x\n", isrc);
1882
1883	if (isrc & PHY_B_IS_PSE)
1884		pr_err("%s: uncorrectable pair swap error\n",
1885		       hw->dev[port]->name);
1886
1887	/* Workaround BCom Errata:
1888	 *	enable and disable loopback mode if "NO HCD" occurs.
1889	 */
1890	if (isrc & PHY_B_IS_NO_HDCL) {
1891		u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1892		xm_phy_write(hw, port, PHY_BCOM_CTRL,
1893				  ctrl | PHY_CT_LOOP);
1894		xm_phy_write(hw, port, PHY_BCOM_CTRL,
1895				  ctrl & ~PHY_CT_LOOP);
1896	}
1897
1898	if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1899		bcom_check_link(hw, port);
1900
1901}
1902
1903static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1904{
1905	int i;
1906
1907	gma_write16(hw, port, GM_SMI_DATA, val);
1908	gma_write16(hw, port, GM_SMI_CTRL,
1909			 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1910	for (i = 0; i < PHY_RETRIES; i++) {
1911		udelay(1);
1912
1913		if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1914			return 0;
1915	}
1916
1917	pr_warn("%s: phy write timeout\n", hw->dev[port]->name);
1918	return -EIO;
1919}
1920
1921static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1922{
1923	int i;
1924
1925	gma_write16(hw, port, GM_SMI_CTRL,
1926			 GM_SMI_CT_PHY_AD(hw->phy_addr)
1927			 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1928
1929	for (i = 0; i < PHY_RETRIES; i++) {
1930		udelay(1);
1931		if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1932			goto ready;
1933	}
1934
1935	return -ETIMEDOUT;
1936 ready:
1937	*val = gma_read16(hw, port, GM_SMI_DATA);
1938	return 0;
1939}
1940
1941static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1942{
1943	u16 v = 0;
1944	if (__gm_phy_read(hw, port, reg, &v))
1945		pr_warn("%s: phy read timeout\n", hw->dev[port]->name);
1946	return v;
1947}
1948
1949/* Marvell Phy Initialization */
1950static void yukon_init(struct skge_hw *hw, int port)
1951{
1952	struct skge_port *skge = netdev_priv(hw->dev[port]);
1953	u16 ctrl, ct1000, adv;
1954
1955	if (skge->autoneg == AUTONEG_ENABLE) {
1956		u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1957
1958		ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1959			  PHY_M_EC_MAC_S_MSK);
1960		ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1961
1962		ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1963
1964		gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1965	}
1966
1967	ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1968	if (skge->autoneg == AUTONEG_DISABLE)
1969		ctrl &= ~PHY_CT_ANE;
1970
1971	ctrl |= PHY_CT_RESET;
1972	gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1973
1974	ctrl = 0;
1975	ct1000 = 0;
1976	adv = PHY_AN_CSMA;
1977
1978	if (skge->autoneg == AUTONEG_ENABLE) {
1979		if (hw->copper) {
1980			if (skge->advertising & ADVERTISED_1000baseT_Full)
1981				ct1000 |= PHY_M_1000C_AFD;
1982			if (skge->advertising & ADVERTISED_1000baseT_Half)
1983				ct1000 |= PHY_M_1000C_AHD;
1984			if (skge->advertising & ADVERTISED_100baseT_Full)
1985				adv |= PHY_M_AN_100_FD;
1986			if (skge->advertising & ADVERTISED_100baseT_Half)
1987				adv |= PHY_M_AN_100_HD;
1988			if (skge->advertising & ADVERTISED_10baseT_Full)
1989				adv |= PHY_M_AN_10_FD;
1990			if (skge->advertising & ADVERTISED_10baseT_Half)
1991				adv |= PHY_M_AN_10_HD;
1992
1993			/* Set Flow-control capabilities */
1994			adv |= phy_pause_map[skge->flow_control];
1995		} else {
1996			if (skge->advertising & ADVERTISED_1000baseT_Full)
1997				adv |= PHY_M_AN_1000X_AFD;
1998			if (skge->advertising & ADVERTISED_1000baseT_Half)
1999				adv |= PHY_M_AN_1000X_AHD;
2000
2001			adv |= fiber_pause_map[skge->flow_control];
2002		}
2003
2004		/* Restart Auto-negotiation */
2005		ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
2006	} else {
2007		/* forced speed/duplex settings */
2008		ct1000 = PHY_M_1000C_MSE;
2009
2010		if (skge->duplex == DUPLEX_FULL)
2011			ctrl |= PHY_CT_DUP_MD;
2012
2013		switch (skge->speed) {
2014		case SPEED_1000:
2015			ctrl |= PHY_CT_SP1000;
2016			break;
2017		case SPEED_100:
2018			ctrl |= PHY_CT_SP100;
2019			break;
2020		}
2021
2022		ctrl |= PHY_CT_RESET;
2023	}
2024
2025	gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
2026
2027	gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2028	gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2029
2030	/* Enable phy interrupt on autonegotiation complete (or link up) */
2031	if (skge->autoneg == AUTONEG_ENABLE)
2032		gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
2033	else
2034		gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2035}
2036
2037static void yukon_reset(struct skge_hw *hw, int port)
2038{
2039	gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2040	gma_write16(hw, port, GM_MC_ADDR_H1, 0);	/* clear MC hash */
2041	gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2042	gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2043	gma_write16(hw, port, GM_MC_ADDR_H4, 0);
2044
2045	gma_write16(hw, port, GM_RX_CTRL,
2046			 gma_read16(hw, port, GM_RX_CTRL)
2047			 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2048}
2049
2050/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
2051static int is_yukon_lite_a0(struct skge_hw *hw)
2052{
2053	u32 reg;
2054	int ret;
2055
2056	if (hw->chip_id != CHIP_ID_YUKON)
2057		return 0;
2058
2059	reg = skge_read32(hw, B2_FAR);
2060	skge_write8(hw, B2_FAR + 3, 0xff);
2061	ret = (skge_read8(hw, B2_FAR + 3) != 0);
2062	skge_write32(hw, B2_FAR, reg);
2063	return ret;
2064}
2065
2066static void yukon_mac_init(struct skge_hw *hw, int port)
2067{
2068	struct skge_port *skge = netdev_priv(hw->dev[port]);
2069	int i;
2070	u32 reg;
2071	const u8 *addr = hw->dev[port]->dev_addr;
2072
2073	/* WA code for COMA mode -- set PHY reset */
2074	if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2075	    hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2076		reg = skge_read32(hw, B2_GP_IO);
2077		reg |= GP_DIR_9 | GP_IO_9;
2078		skge_write32(hw, B2_GP_IO, reg);
2079	}
2080
2081	/* hard reset */
2082	skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2083	skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2084
2085	/* WA code for COMA mode -- clear PHY reset */
2086	if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2087	    hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2088		reg = skge_read32(hw, B2_GP_IO);
2089		reg |= GP_DIR_9;
2090		reg &= ~GP_IO_9;
2091		skge_write32(hw, B2_GP_IO, reg);
2092	}
2093
2094	/* Set hardware config mode */
2095	reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2096		GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
2097	reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
2098
2099	/* Clear GMC reset */
2100	skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2101	skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2102	skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
2103
2104	if (skge->autoneg == AUTONEG_DISABLE) {
2105		reg = GM_GPCR_AU_ALL_DIS;
2106		gma_write16(hw, port, GM_GP_CTRL,
2107				 gma_read16(hw, port, GM_GP_CTRL) | reg);
2108
2109		switch (skge->speed) {
2110		case SPEED_1000:
2111			reg &= ~GM_GPCR_SPEED_100;
2112			reg |= GM_GPCR_SPEED_1000;
2113			break;
2114		case SPEED_100:
2115			reg &= ~GM_GPCR_SPEED_1000;
2116			reg |= GM_GPCR_SPEED_100;
2117			break;
2118		case SPEED_10:
2119			reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2120			break;
2121		}
2122
2123		if (skge->duplex == DUPLEX_FULL)
2124			reg |= GM_GPCR_DUP_FULL;
2125	} else
2126		reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
2127
2128	switch (skge->flow_control) {
2129	case FLOW_MODE_NONE:
2130		skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2131		reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2132		break;
2133	case FLOW_MODE_LOC_SEND:
2134		/* disable Rx flow-control */
2135		reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2136		break;
2137	case FLOW_MODE_SYMMETRIC:
2138	case FLOW_MODE_SYM_OR_REM:
2139		/* enable Tx & Rx flow-control */
2140		break;
2141	}
2142
2143	gma_write16(hw, port, GM_GP_CTRL, reg);
2144	skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
2145
2146	yukon_init(hw, port);
2147
2148	/* MIB clear */
2149	reg = gma_read16(hw, port, GM_PHY_ADDR);
2150	gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
2151
2152	for (i = 0; i < GM_MIB_CNT_SIZE; i++)
2153		gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2154	gma_write16(hw, port, GM_PHY_ADDR, reg);
2155
2156	/* transmit control */
2157	gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
2158
2159	/* receive control reg: unicast + multicast + no FCS  */
2160	gma_write16(hw, port, GM_RX_CTRL,
2161			 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2162
2163	/* transmit flow control */
2164	gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
2165
2166	/* transmit parameter */
2167	gma_write16(hw, port, GM_TX_PARAM,
2168			 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2169			 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2170			 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2171
2172	/* configure the Serial Mode Register */
2173	reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
2174		| GM_SMOD_VLAN_ENA
2175		| IPG_DATA_VAL(IPG_DATA_DEF);
2176
2177	if (hw->dev[port]->mtu > ETH_DATA_LEN)
2178		reg |= GM_SMOD_JUMBO_ENA;
2179
2180	gma_write16(hw, port, GM_SERIAL_MODE, reg);
2181
2182	/* physical address: used for pause frames */
2183	gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
2184	/* virtual address for data */
2185	gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
2186
2187	/* enable interrupt mask for counter overflows */
2188	gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2189	gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2190	gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
2191
2192	/* Initialize Mac Fifo */
2193
2194	/* Configure Rx MAC FIFO */
2195	skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
2196	reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
2197
2198	/* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2199	if (is_yukon_lite_a0(hw))
2200		reg &= ~GMF_RX_F_FL_ON;
2201
2202	skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2203	skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
2204	/*
2205	 * because Pause Packet Truncation in GMAC is not working
2206	 * we have to increase the Flush Threshold to 64 bytes
2207	 * in order to flush pause packets in Rx FIFO on Yukon-1
2208	 */
2209	skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
2210
2211	/* Configure Tx MAC FIFO */
2212	skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2213	skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
2214}
2215
2216/* Go into power down mode */
2217static void yukon_suspend(struct skge_hw *hw, int port)
2218{
2219	u16 ctrl;
2220
2221	ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2222	ctrl |= PHY_M_PC_POL_R_DIS;
2223	gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2224
2225	ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2226	ctrl |= PHY_CT_RESET;
2227	gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2228
2229	/* switch IEEE compatible power down mode on */
2230	ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2231	ctrl |= PHY_CT_PDOWN;
2232	gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2233}
2234
2235static void yukon_stop(struct skge_port *skge)
2236{
2237	struct skge_hw *hw = skge->hw;
2238	int port = skge->port;
2239
2240	skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2241	yukon_reset(hw, port);
2242
2243	gma_write16(hw, port, GM_GP_CTRL,
2244			 gma_read16(hw, port, GM_GP_CTRL)
2245			 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
2246	gma_read16(hw, port, GM_GP_CTRL);
2247
2248	yukon_suspend(hw, port);
2249
2250	/* set GPHY Control reset */
2251	skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2252	skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2253}
2254
2255static void yukon_get_stats(struct skge_port *skge, u64 *data)
2256{
2257	struct skge_hw *hw = skge->hw;
2258	int port = skge->port;
2259	int i;
2260
2261	data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2262		| gma_read32(hw, port, GM_TXO_OK_LO);
2263	data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2264		| gma_read32(hw, port, GM_RXO_OK_LO);
2265
2266	for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
2267		data[i] = gma_read32(hw, port,
2268					  skge_stats[i].gma_offset);
2269}
2270
2271static void yukon_mac_intr(struct skge_hw *hw, int port)
2272{
2273	struct net_device *dev = hw->dev[port];
2274	struct skge_port *skge = netdev_priv(dev);
2275	u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2276
2277	netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2278		     "mac interrupt status 0x%x\n", status);
2279
2280	if (status & GM_IS_RX_FF_OR) {
2281		++dev->stats.rx_fifo_errors;
2282		skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2283	}
2284
2285	if (status & GM_IS_TX_FF_UR) {
2286		++dev->stats.tx_fifo_errors;
2287		skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2288	}
2289
2290}
2291
2292static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2293{
2294	switch (aux & PHY_M_PS_SPEED_MSK) {
2295	case PHY_M_PS_SPEED_1000:
2296		return SPEED_1000;
2297	case PHY_M_PS_SPEED_100:
2298		return SPEED_100;
2299	default:
2300		return SPEED_10;
2301	}
2302}
2303
2304static void yukon_link_up(struct skge_port *skge)
2305{
2306	struct skge_hw *hw = skge->hw;
2307	int port = skge->port;
2308	u16 reg;
2309
2310	/* Enable Transmit FIFO Underrun */
2311	skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
2312
2313	reg = gma_read16(hw, port, GM_GP_CTRL);
2314	if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2315		reg |= GM_GPCR_DUP_FULL;
2316
2317	/* enable Rx/Tx */
2318	reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2319	gma_write16(hw, port, GM_GP_CTRL, reg);
2320
2321	gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2322	skge_link_up(skge);
2323}
2324
2325static void yukon_link_down(struct skge_port *skge)
2326{
2327	struct skge_hw *hw = skge->hw;
2328	int port = skge->port;
2329	u16 ctrl;
2330
2331	ctrl = gma_read16(hw, port, GM_GP_CTRL);
2332	ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2333	gma_write16(hw, port, GM_GP_CTRL, ctrl);
2334
2335	if (skge->flow_status == FLOW_STAT_REM_SEND) {
2336		ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2337		ctrl |= PHY_M_AN_ASP;
2338		/* restore Asymmetric Pause bit */
2339		gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
2340	}
2341
2342	skge_link_down(skge);
2343
2344	yukon_init(hw, port);
2345}
2346
2347static void yukon_phy_intr(struct skge_port *skge)
2348{
2349	struct skge_hw *hw = skge->hw;
2350	int port = skge->port;
2351	const char *reason = NULL;
2352	u16 istatus, phystat;
2353
2354	istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2355	phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2356
2357	netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2358		     "phy interrupt status 0x%x 0x%x\n", istatus, phystat);
2359
2360	if (istatus & PHY_M_IS_AN_COMPL) {
2361		if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2362		    & PHY_M_AN_RF) {
2363			reason = "remote fault";
2364			goto failed;
2365		}
2366
2367		if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
2368			reason = "master/slave fault";
2369			goto failed;
2370		}
2371
2372		if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2373			reason = "speed/duplex";
2374			goto failed;
2375		}
2376
2377		skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2378			? DUPLEX_FULL : DUPLEX_HALF;
2379		skge->speed = yukon_speed(hw, phystat);
2380
2381		/* We are using IEEE 802.3z/D5.0 Table 37-4 */
2382		switch (phystat & PHY_M_PS_PAUSE_MSK) {
2383		case PHY_M_PS_PAUSE_MSK:
2384			skge->flow_status = FLOW_STAT_SYMMETRIC;
2385			break;
2386		case PHY_M_PS_RX_P_EN:
2387			skge->flow_status = FLOW_STAT_REM_SEND;
2388			break;
2389		case PHY_M_PS_TX_P_EN:
2390			skge->flow_status = FLOW_STAT_LOC_SEND;
2391			break;
2392		default:
2393			skge->flow_status = FLOW_STAT_NONE;
2394		}
2395
2396		if (skge->flow_status == FLOW_STAT_NONE ||
2397		    (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2398			skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2399		else
2400			skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2401		yukon_link_up(skge);
2402		return;
2403	}
2404
2405	if (istatus & PHY_M_IS_LSP_CHANGE)
2406		skge->speed = yukon_speed(hw, phystat);
2407
2408	if (istatus & PHY_M_IS_DUP_CHANGE)
2409		skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2410	if (istatus & PHY_M_IS_LST_CHANGE) {
2411		if (phystat & PHY_M_PS_LINK_UP)
2412			yukon_link_up(skge);
2413		else
2414			yukon_link_down(skge);
2415	}
2416	return;
2417 failed:
2418	pr_err("%s: autonegotiation failed (%s)\n", skge->netdev->name, reason);
2419
2420	/* XXX restart autonegotiation? */
2421}
2422
2423static void skge_phy_reset(struct skge_port *skge)
2424{
2425	struct skge_hw *hw = skge->hw;
2426	int port = skge->port;
2427	struct net_device *dev = hw->dev[port];
2428
2429	netif_stop_queue(skge->netdev);
2430	netif_carrier_off(skge->netdev);
2431
2432	spin_lock_bh(&hw->phy_lock);
2433	if (is_genesis(hw)) {
2434		genesis_reset(hw, port);
2435		genesis_mac_init(hw, port);
2436	} else {
2437		yukon_reset(hw, port);
2438		yukon_init(hw, port);
2439	}
2440	spin_unlock_bh(&hw->phy_lock);
2441
2442	skge_set_multicast(dev);
2443}
2444
2445/* Basic MII support */
2446static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2447{
2448	struct mii_ioctl_data *data = if_mii(ifr);
2449	struct skge_port *skge = netdev_priv(dev);
2450	struct skge_hw *hw = skge->hw;
2451	int err = -EOPNOTSUPP;
2452
2453	if (!netif_running(dev))
2454		return -ENODEV;	/* Phy still in reset */
2455
2456	switch (cmd) {
2457	case SIOCGMIIPHY:
2458		data->phy_id = hw->phy_addr;
2459
2460		/* fallthru */
2461	case SIOCGMIIREG: {
2462		u16 val = 0;
2463		spin_lock_bh(&hw->phy_lock);
2464
2465		if (is_genesis(hw))
2466			err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2467		else
2468			err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2469		spin_unlock_bh(&hw->phy_lock);
2470		data->val_out = val;
2471		break;
2472	}
2473
2474	case SIOCSMIIREG:
2475		spin_lock_bh(&hw->phy_lock);
2476		if (is_genesis(hw))
2477			err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2478				   data->val_in);
2479		else
2480			err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2481				   data->val_in);
2482		spin_unlock_bh(&hw->phy_lock);
2483		break;
2484	}
2485	return err;
2486}
2487
2488static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2489{
2490	u32 end;
2491
2492	start /= 8;
2493	len /= 8;
2494	end = start + len - 1;
2495
2496	skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2497	skge_write32(hw, RB_ADDR(q, RB_START), start);
2498	skge_write32(hw, RB_ADDR(q, RB_WP), start);
2499	skge_write32(hw, RB_ADDR(q, RB_RP), start);
2500	skge_write32(hw, RB_ADDR(q, RB_END), end);
2501
2502	if (q == Q_R1 || q == Q_R2) {
2503		/* Set thresholds on receive queue's */
2504		skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2505			     start + (2*len)/3);
2506		skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2507			     start + (len/3));
2508	} else {
2509		/* Enable store & forward on Tx queue's because
2510		 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2511		 */
2512		skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2513	}
2514
2515	skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2516}
2517
2518/* Setup Bus Memory Interface */
2519static void skge_qset(struct skge_port *skge, u16 q,
2520		      const struct skge_element *e)
2521{
2522	struct skge_hw *hw = skge->hw;
2523	u32 watermark = 0x600;
2524	u64 base = skge->dma + (e->desc - skge->mem);
2525
2526	/* optimization to reduce window on 32bit/33mhz */
2527	if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2528		watermark /= 2;
2529
2530	skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2531	skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2532	skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2533	skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2534}
2535
2536static int skge_up(struct net_device *dev)
2537{
2538	struct skge_port *skge = netdev_priv(dev);
2539	struct skge_hw *hw = skge->hw;
2540	int port = skge->port;
2541	u32 chunk, ram_addr;
2542	size_t rx_size, tx_size;
2543	int err;
2544
2545	if (!is_valid_ether_addr(dev->dev_addr))
2546		return -EINVAL;
2547
2548	netif_info(skge, ifup, skge->netdev, "enabling interface\n");
2549
2550	if (dev->mtu > RX_BUF_SIZE)
2551		skge->rx_buf_size = dev->mtu + ETH_HLEN;
2552	else
2553		skge->rx_buf_size = RX_BUF_SIZE;
2554
2555
2556	rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2557	tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2558	skge->mem_size = tx_size + rx_size;
2559	skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2560	if (!skge->mem)
2561		return -ENOMEM;
2562
2563	BUG_ON(skge->dma & 7);
2564
2565	if (upper_32_bits(skge->dma) != upper_32_bits(skge->dma + skge->mem_size)) {
2566		dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
2567		err = -EINVAL;
2568		goto free_pci_mem;
2569	}
2570
2571	memset(skge->mem, 0, skge->mem_size);
2572
2573	err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2574	if (err)
2575		goto free_pci_mem;
2576
2577	err = skge_rx_fill(dev);
2578	if (err)
2579		goto free_rx_ring;
2580
2581	err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2582			      skge->dma + rx_size);
2583	if (err)
2584		goto free_rx_ring;
2585
2586	if (hw->ports == 1) {
2587		err = request_irq(hw->pdev->irq, skge_intr, IRQF_SHARED,
2588				  dev->name, hw);
2589		if (err) {
2590			netdev_err(dev, "Unable to allocate interrupt %d error: %d\n",
2591				   hw->pdev->irq, err);
2592			goto free_tx_ring;
2593		}
2594	}
2595
2596	/* Initialize MAC */
2597	netif_carrier_off(dev);
2598	spin_lock_bh(&hw->phy_lock);
2599	if (is_genesis(hw))
2600		genesis_mac_init(hw, port);
2601	else
2602		yukon_mac_init(hw, port);
2603	spin_unlock_bh(&hw->phy_lock);
2604
2605	/* Configure RAMbuffers - equally between ports and tx/rx */
2606	chunk = (hw->ram_size  - hw->ram_offset) / (hw->ports * 2);
2607	ram_addr = hw->ram_offset + 2 * chunk * port;
2608
2609	skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2610	skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2611
2612	BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2613	skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2614	skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2615
2616	/* Start receiver BMU */
2617	wmb();
2618	skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2619	skge_led(skge, LED_MODE_ON);
2620
2621	spin_lock_irq(&hw->hw_lock);
2622	hw->intr_mask |= portmask[port];
2623	skge_write32(hw, B0_IMSK, hw->intr_mask);
2624	skge_read32(hw, B0_IMSK);
2625	spin_unlock_irq(&hw->hw_lock);
2626
2627	napi_enable(&skge->napi);
2628
2629	skge_set_multicast(dev);
2630
2631	return 0;
2632
2633 free_tx_ring:
2634	kfree(skge->tx_ring.start);
2635 free_rx_ring:
2636	skge_rx_clean(skge);
2637	kfree(skge->rx_ring.start);
2638 free_pci_mem:
2639	pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2640	skge->mem = NULL;
2641
2642	return err;
2643}
2644
2645/* stop receiver */
2646static void skge_rx_stop(struct skge_hw *hw, int port)
2647{
2648	skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2649	skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2650		     RB_RST_SET|RB_DIS_OP_MD);
2651	skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2652}
2653
2654static int skge_down(struct net_device *dev)
2655{
2656	struct skge_port *skge = netdev_priv(dev);
2657	struct skge_hw *hw = skge->hw;
2658	int port = skge->port;
2659
2660	if (!skge->mem)
2661		return 0;
2662
2663	netif_info(skge, ifdown, skge->netdev, "disabling interface\n");
2664
2665	netif_tx_disable(dev);
2666
2667	if (is_genesis(hw) && hw->phy_type == SK_PHY_XMAC)
2668		del_timer_sync(&skge->link_timer);
2669
2670	napi_disable(&skge->napi);
2671	netif_carrier_off(dev);
2672
2673	spin_lock_irq(&hw->hw_lock);
2674	hw->intr_mask &= ~portmask[port];
2675	skge_write32(hw, B0_IMSK, (hw->ports == 1) ? 0 : hw->intr_mask);
2676	skge_read32(hw, B0_IMSK);
2677	spin_unlock_irq(&hw->hw_lock);
2678
2679	if (hw->ports == 1)
2680		free_irq(hw->pdev->irq, hw);
2681
2682	skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF);
2683	if (is_genesis(hw))
2684		genesis_stop(skge);
2685	else
2686		yukon_stop(skge);
2687
2688	/* Stop transmitter */
2689	skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2690	skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2691		     RB_RST_SET|RB_DIS_OP_MD);
2692
2693
2694	/* Disable Force Sync bit and Enable Alloc bit */
2695	skge_write8(hw, SK_REG(port, TXA_CTRL),
2696		    TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2697
2698	/* Stop Interval Timer and Limit Counter of Tx Arbiter */
2699	skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2700	skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2701
2702	/* Reset PCI FIFO */
2703	skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2704	skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2705
2706	/* Reset the RAM Buffer async Tx queue */
2707	skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2708
2709	skge_rx_stop(hw, port);
2710
2711	if (is_genesis(hw)) {
2712		skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2713		skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2714	} else {
2715		skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2716		skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2717	}
2718
2719	skge_led(skge, LED_MODE_OFF);
2720
2721	netif_tx_lock_bh(dev);
2722	skge_tx_clean(dev);
2723	netif_tx_unlock_bh(dev);
2724
2725	skge_rx_clean(skge);
2726
2727	kfree(skge->rx_ring.start);
2728	kfree(skge->tx_ring.start);
2729	pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2730	skge->mem = NULL;
2731	return 0;
2732}
2733
2734static inline int skge_avail(const struct skge_ring *ring)
2735{
2736	smp_mb();
2737	return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2738		+ (ring->to_clean - ring->to_use) - 1;
2739}
2740
2741static netdev_tx_t skge_xmit_frame(struct sk_buff *skb,
2742				   struct net_device *dev)
2743{
2744	struct skge_port *skge = netdev_priv(dev);
2745	struct skge_hw *hw = skge->hw;
2746	struct skge_element *e;
2747	struct skge_tx_desc *td;
2748	int i;
2749	u32 control, len;
2750	dma_addr_t map;
2751
2752	if (skb_padto(skb, ETH_ZLEN))
2753		return NETDEV_TX_OK;
2754
2755	if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
2756		return NETDEV_TX_BUSY;
2757
2758	e = skge->tx_ring.to_use;
2759	td = e->desc;
2760	BUG_ON(td->control & BMU_OWN);
2761	e->skb = skb;
2762	len = skb_headlen(skb);
2763	map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2764	if (pci_dma_mapping_error(hw->pdev, map))
2765		goto mapping_error;
2766
2767	dma_unmap_addr_set(e, mapaddr, map);
2768	dma_unmap_len_set(e, maplen, len);
2769
2770	td->dma_lo = lower_32_bits(map);
2771	td->dma_hi = upper_32_bits(map);
2772
2773	if (skb->ip_summed == CHECKSUM_PARTIAL) {
2774		const int offset = skb_checksum_start_offset(skb);
2775
2776		/* This seems backwards, but it is what the sk98lin
2777		 * does.  Looks like hardware is wrong?
2778		 */
2779		if (ipip_hdr(skb)->protocol == IPPROTO_UDP &&
2780		    hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2781			control = BMU_TCP_CHECK;
2782		else
2783			control = BMU_UDP_CHECK;
2784
2785		td->csum_offs = 0;
2786		td->csum_start = offset;
2787		td->csum_write = offset + skb->csum_offset;
2788	} else
2789		control = BMU_CHECK;
2790
2791	if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2792		control |= BMU_EOF | BMU_IRQ_EOF;
2793	else {
2794		struct skge_tx_desc *tf = td;
2795
2796		control |= BMU_STFWD;
2797		for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2798			const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2799
2800			map = skb_frag_dma_map(&hw->pdev->dev, frag, 0,
2801					       skb_frag_size(frag), DMA_TO_DEVICE);
2802			if (dma_mapping_error(&hw->pdev->dev, map))
2803				goto mapping_unwind;
2804
2805			e = e->next;
2806			e->skb = skb;
2807			tf = e->desc;
2808			BUG_ON(tf->control & BMU_OWN);
2809
2810			tf->dma_lo = lower_32_bits(map);
2811			tf->dma_hi = upper_32_bits(map);
2812			dma_unmap_addr_set(e, mapaddr, map);
2813			dma_unmap_len_set(e, maplen, skb_frag_size(frag));
2814
2815			tf->control = BMU_OWN | BMU_SW | control | skb_frag_size(frag);
2816		}
2817		tf->control |= BMU_EOF | BMU_IRQ_EOF;
2818	}
2819	/* Make sure all the descriptors written */
2820	wmb();
2821	td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2822	wmb();
2823
2824	netdev_sent_queue(dev, skb->len);
2825
2826	skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2827
2828	netif_printk(skge, tx_queued, KERN_DEBUG, skge->netdev,
2829		     "tx queued, slot %td, len %d\n",
2830		     e - skge->tx_ring.start, skb->len);
2831
2832	skge->tx_ring.to_use = e->next;
2833	smp_wmb();
2834
2835	if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
2836		netdev_dbg(dev, "transmit queue full\n");
2837		netif_stop_queue(dev);
2838	}
2839
2840	return NETDEV_TX_OK;
2841
2842mapping_unwind:
2843	e = skge->tx_ring.to_use;
2844	pci_unmap_single(hw->pdev,
2845			 dma_unmap_addr(e, mapaddr),
2846			 dma_unmap_len(e, maplen),
2847			 PCI_DMA_TODEVICE);
2848	while (i-- > 0) {
2849		e = e->next;
2850		pci_unmap_page(hw->pdev,
2851			       dma_unmap_addr(e, mapaddr),
2852			       dma_unmap_len(e, maplen),
2853			       PCI_DMA_TODEVICE);
2854	}
2855
2856mapping_error:
2857	if (net_ratelimit())
2858		dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
2859	dev_kfree_skb_any(skb);
2860	return NETDEV_TX_OK;
2861}
2862
2863
2864/* Free resources associated with this reing element */
2865static inline void skge_tx_unmap(struct pci_dev *pdev, struct skge_element *e,
2866				 u32 control)
2867{
2868	/* skb header vs. fragment */
2869	if (control & BMU_STF)
2870		pci_unmap_single(pdev, dma_unmap_addr(e, mapaddr),
2871				 dma_unmap_len(e, maplen),
2872				 PCI_DMA_TODEVICE);
2873	else
2874		pci_unmap_page(pdev, dma_unmap_addr(e, mapaddr),
2875			       dma_unmap_len(e, maplen),
2876			       PCI_DMA_TODEVICE);
2877}
2878
2879/* Free all buffers in transmit ring */
2880static void skge_tx_clean(struct net_device *dev)
2881{
2882	struct skge_port *skge = netdev_priv(dev);
2883	struct skge_element *e;
2884
2885	for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2886		struct skge_tx_desc *td = e->desc;
2887
2888		skge_tx_unmap(skge->hw->pdev, e, td->control);
2889
2890		if (td->control & BMU_EOF)
2891			dev_kfree_skb(e->skb);
2892		td->control = 0;
2893	}
2894
2895	netdev_reset_queue(dev);
2896	skge->tx_ring.to_clean = e;
2897}
2898
2899static void skge_tx_timeout(struct net_device *dev)
2900{
2901	struct skge_port *skge = netdev_priv(dev);
2902
2903	netif_printk(skge, timer, KERN_DEBUG, skge->netdev, "tx timeout\n");
2904
2905	skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2906	skge_tx_clean(dev);
2907	netif_wake_queue(dev);
2908}
2909
2910static int skge_change_mtu(struct net_device *dev, int new_mtu)
2911{
2912	int err;
2913
2914	if (!netif_running(dev)) {
2915		dev->mtu = new_mtu;
2916		return 0;
2917	}
2918
2919	skge_down(dev);
2920
2921	dev->mtu = new_mtu;
2922
2923	err = skge_up(dev);
2924	if (err)
2925		dev_close(dev);
2926
2927	return err;
2928}
2929
2930static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2931
2932static void genesis_add_filter(u8 filter[8], const u8 *addr)
2933{
2934	u32 crc, bit;
2935
2936	crc = ether_crc_le(ETH_ALEN, addr);
2937	bit = ~crc & 0x3f;
2938	filter[bit/8] |= 1 << (bit%8);
2939}
2940
2941static void genesis_set_multicast(struct net_device *dev)
2942{
2943	struct skge_port *skge = netdev_priv(dev);
2944	struct skge_hw *hw = skge->hw;
2945	int port = skge->port;
2946	struct netdev_hw_addr *ha;
2947	u32 mode;
2948	u8 filter[8];
2949
2950	mode = xm_read32(hw, port, XM_MODE);
2951	mode |= XM_MD_ENA_HASH;
2952	if (dev->flags & IFF_PROMISC)
2953		mode |= XM_MD_ENA_PROM;
2954	else
2955		mode &= ~XM_MD_ENA_PROM;
2956
2957	if (dev->flags & IFF_ALLMULTI)
2958		memset(filter, 0xff, sizeof(filter));
2959	else {
2960		memset(filter, 0, sizeof(filter));
2961
2962		if (skge->flow_status == FLOW_STAT_REM_SEND ||
2963		    skge->flow_status == FLOW_STAT_SYMMETRIC)
2964			genesis_add_filter(filter, pause_mc_addr);
2965
2966		netdev_for_each_mc_addr(ha, dev)
2967			genesis_add_filter(filter, ha->addr);
2968	}
2969
2970	xm_write32(hw, port, XM_MODE, mode);
2971	xm_outhash(hw, port, XM_HSM, filter);
2972}
2973
2974static void yukon_add_filter(u8 filter[8], const u8 *addr)
2975{
2976	 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2977	 filter[bit/8] |= 1 << (bit%8);
2978}
2979
2980static void yukon_set_multicast(struct net_device *dev)
2981{
2982	struct skge_port *skge = netdev_priv(dev);
2983	struct skge_hw *hw = skge->hw;
2984	int port = skge->port;
2985	struct netdev_hw_addr *ha;
2986	int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND ||
2987			skge->flow_status == FLOW_STAT_SYMMETRIC);
2988	u16 reg;
2989	u8 filter[8];
2990
2991	memset(filter, 0, sizeof(filter));
2992
2993	reg = gma_read16(hw, port, GM_RX_CTRL);
2994	reg |= GM_RXCR_UCF_ENA;
2995
2996	if (dev->flags & IFF_PROMISC) 		/* promiscuous */
2997		reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2998	else if (dev->flags & IFF_ALLMULTI)	/* all multicast */
2999		memset(filter, 0xff, sizeof(filter));
3000	else if (netdev_mc_empty(dev) && !rx_pause)/* no multicast */
3001		reg &= ~GM_RXCR_MCF_ENA;
3002	else {
3003		reg |= GM_RXCR_MCF_ENA;
3004
3005		if (rx_pause)
3006			yukon_add_filter(filter, pause_mc_addr);
3007
3008		netdev_for_each_mc_addr(ha, dev)
3009			yukon_add_filter(filter, ha->addr);
3010	}
3011
3012
3013	gma_write16(hw, port, GM_MC_ADDR_H1,
3014			 (u16)filter[0] | ((u16)filter[1] << 8));
3015	gma_write16(hw, port, GM_MC_ADDR_H2,
3016			 (u16)filter[2] | ((u16)filter[3] << 8));
3017	gma_write16(hw, port, GM_MC_ADDR_H3,
3018			 (u16)filter[4] | ((u16)filter[5] << 8));
3019	gma_write16(hw, port, GM_MC_ADDR_H4,
3020			 (u16)filter[6] | ((u16)filter[7] << 8));
3021
3022	gma_write16(hw, port, GM_RX_CTRL, reg);
3023}
3024
3025static inline u16 phy_length(const struct skge_hw *hw, u32 status)
3026{
3027	if (is_genesis(hw))
3028		return status >> XMR_FS_LEN_SHIFT;
3029	else
3030		return status >> GMR_FS_LEN_SHIFT;
3031}
3032
3033static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
3034{
3035	if (is_genesis(hw))
3036		return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
3037	else
3038		return (status & GMR_FS_ANY_ERR) ||
3039			(status & GMR_FS_RX_OK) == 0;
3040}
3041
3042static void skge_set_multicast(struct net_device *dev)
3043{
3044	struct skge_port *skge = netdev_priv(dev);
3045
3046	if (is_genesis(skge->hw))
3047		genesis_set_multicast(dev);
3048	else
3049		yukon_set_multicast(dev);
3050
3051}
3052
3053
3054/* Get receive buffer from descriptor.
3055 * Handles copy of small buffers and reallocation failures
3056 */
3057static struct sk_buff *skge_rx_get(struct net_device *dev,
3058				   struct skge_element *e,
3059				   u32 control, u32 status, u16 csum)
3060{
3061	struct skge_port *skge = netdev_priv(dev);
3062	struct sk_buff *skb;
3063	u16 len = control & BMU_BBC;
3064
3065	netif_printk(skge, rx_status, KERN_DEBUG, skge->netdev,
3066		     "rx slot %td status 0x%x len %d\n",
3067		     e - skge->rx_ring.start, status, len);
3068
3069	if (len > skge->rx_buf_size)
3070		goto error;
3071
3072	if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
3073		goto error;
3074
3075	if (bad_phy_status(skge->hw, status))
3076		goto error;
3077
3078	if (phy_length(skge->hw, status) != len)
3079		goto error;
3080
3081	if (len < RX_COPY_THRESHOLD) {
3082		skb = netdev_alloc_skb_ip_align(dev, len);
3083		if (!skb)
3084			goto resubmit;
3085
3086		pci_dma_sync_single_for_cpu(skge->hw->pdev,
3087					    dma_unmap_addr(e, mapaddr),
3088					    dma_unmap_len(e, maplen),
3089					    PCI_DMA_FROMDEVICE);
3090		skb_copy_from_linear_data(e->skb, skb->data, len);
3091		pci_dma_sync_single_for_device(skge->hw->pdev,
3092					       dma_unmap_addr(e, mapaddr),
3093					       dma_unmap_len(e, maplen),
3094					       PCI_DMA_FROMDEVICE);
3095		skge_rx_reuse(e, skge->rx_buf_size);
3096	} else {
3097		struct skge_element ee;
3098		struct sk_buff *nskb;
3099
3100		nskb = netdev_alloc_skb_ip_align(dev, skge->rx_buf_size);
3101		if (!nskb)
3102			goto resubmit;
3103
3104		ee = *e;
3105
3106		skb = ee.skb;
3107		prefetch(skb->data);
3108
3109		if (skge_rx_setup(skge, e, nskb, skge->rx_buf_size) < 0) {
3110			dev_kfree_skb(nskb);
3111			goto resubmit;
3112		}
3113
3114		pci_unmap_single(skge->hw->pdev,
3115				 dma_unmap_addr(&ee, mapaddr),
3116				 dma_unmap_len(&ee, maplen),
3117				 PCI_DMA_FROMDEVICE);
3118	}
3119
3120	skb_put(skb, len);
3121
3122	if (dev->features & NETIF_F_RXCSUM) {
3123		skb->csum = csum;
3124		skb->ip_summed = CHECKSUM_COMPLETE;
3125	}
3126
3127	skb->protocol = eth_type_trans(skb, dev);
3128
3129	return skb;
3130error:
3131
3132	netif_printk(skge, rx_err, KERN_DEBUG, skge->netdev,
3133		     "rx err, slot %td control 0x%x status 0x%x\n",
3134		     e - skge->rx_ring.start, control, status);
3135
3136	if (is_genesis(skge->hw)) {
3137		if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
3138			dev->stats.rx_length_errors++;
3139		if (status & XMR_FS_FRA_ERR)
3140			dev->stats.rx_frame_errors++;
3141		if (status & XMR_FS_FCS_ERR)
3142			dev->stats.rx_crc_errors++;
3143	} else {
3144		if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
3145			dev->stats.rx_length_errors++;
3146		if (status & GMR_FS_FRAGMENT)
3147			dev->stats.rx_frame_errors++;
3148		if (status & GMR_FS_CRC_ERR)
3149			dev->stats.rx_crc_errors++;
3150	}
3151
3152resubmit:
3153	skge_rx_reuse(e, skge->rx_buf_size);
3154	return NULL;
3155}
3156
3157/* Free all buffers in Tx ring which are no longer owned by device */
3158static void skge_tx_done(struct net_device *dev)
3159{
3160	struct skge_port *skge = netdev_priv(dev);
3161	struct skge_ring *ring = &skge->tx_ring;
3162	struct skge_element *e;
3163	unsigned int bytes_compl = 0, pkts_compl = 0;
3164
3165	skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3166
3167	for (e = ring->to_clean; e != ring->to_use; e = e->next) {
3168		u32 control = ((const struct skge_tx_desc *) e->desc)->control;
3169
3170		if (control & BMU_OWN)
3171			break;
3172
3173		skge_tx_unmap(skge->hw->pdev, e, control);
3174
3175		if (control & BMU_EOF) {
3176			netif_printk(skge, tx_done, KERN_DEBUG, skge->netdev,
3177				     "tx done slot %td\n",
3178				     e - skge->tx_ring.start);
3179
3180			pkts_compl++;
3181			bytes_compl += e->skb->len;
3182
3183			dev_consume_skb_any(e->skb);
3184		}
3185	}
3186	netdev_completed_queue(dev, pkts_compl, bytes_compl);
3187	skge->tx_ring.to_clean = e;
3188
3189	/* Can run lockless until we need to synchronize to restart queue. */
3190	smp_mb();
3191
3192	if (unlikely(netif_queue_stopped(dev) &&
3193		     skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3194		netif_tx_lock(dev);
3195		if (unlikely(netif_queue_stopped(dev) &&
3196			     skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3197			netif_wake_queue(dev);
3198
3199		}
3200		netif_tx_unlock(dev);
3201	}
3202}
3203
3204static int skge_poll(struct napi_struct *napi, int budget)
3205{
3206	struct skge_port *skge = container_of(napi, struct skge_port, napi);
3207	struct net_device *dev = skge->netdev;
3208	struct skge_hw *hw = skge->hw;
3209	struct skge_ring *ring = &skge->rx_ring;
3210	struct skge_element *e;
3211	int work_done = 0;
3212
3213	skge_tx_done(dev);
3214
3215	skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3216
3217	for (e = ring->to_clean; prefetch(e->next), work_done < budget; e = e->next) {
3218		struct skge_rx_desc *rd = e->desc;
3219		struct sk_buff *skb;
3220		u32 control;
3221
3222		rmb();
3223		control = rd->control;
3224		if (control & BMU_OWN)
3225			break;
3226
3227		skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
3228		if (likely(skb)) {
3229			napi_gro_receive(napi, skb);
3230			++work_done;
3231		}
3232	}
3233	ring->to_clean = e;
3234
3235	/* restart receiver */
3236	wmb();
3237	skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
3238
3239	if (work_done < budget && napi_complete_done(napi, work_done)) {
3240		unsigned long flags;
3241
3242		spin_lock_irqsave(&hw->hw_lock, flags);
3243		hw->intr_mask |= napimask[skge->port];
3244		skge_write32(hw, B0_IMSK, hw->intr_mask);
3245		skge_read32(hw, B0_IMSK);
3246		spin_unlock_irqrestore(&hw->hw_lock, flags);
3247	}
3248
3249	return work_done;
3250}
3251
3252/* Parity errors seem to happen when Genesis is connected to a switch
3253 * with no other ports present. Heartbeat error??
3254 */
3255static void skge_mac_parity(struct skge_hw *hw, int port)
3256{
3257	struct net_device *dev = hw->dev[port];
3258
3259	++dev->stats.tx_heartbeat_errors;
3260
3261	if (is_genesis(hw))
3262		skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
3263			     MFF_CLR_PERR);
3264	else
3265		/* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
3266		skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
3267			    (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
3268			    ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3269}
3270
3271static void skge_mac_intr(struct skge_hw *hw, int port)
3272{
3273	if (is_genesis(hw))
3274		genesis_mac_intr(hw, port);
3275	else
3276		yukon_mac_intr(hw, port);
3277}
3278
3279/* Handle device specific framing and timeout interrupts */
3280static void skge_error_irq(struct skge_hw *hw)
3281{
3282	struct pci_dev *pdev = hw->pdev;
3283	u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3284
3285	if (is_genesis(hw)) {
3286		/* clear xmac errors */
3287		if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
3288			skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
3289		if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
3290			skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
3291	} else {
3292		/* Timestamp (unused) overflow */
3293		if (hwstatus & IS_IRQ_TIST_OV)
3294			skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3295	}
3296
3297	if (hwstatus & IS_RAM_RD_PAR) {
3298		dev_err(&pdev->dev, "Ram read data parity error\n");
3299		skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3300	}
3301
3302	if (hwstatus & IS_RAM_WR_PAR) {
3303		dev_err(&pdev->dev, "Ram write data parity error\n");
3304		skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3305	}
3306
3307	if (hwstatus & IS_M1_PAR_ERR)
3308		skge_mac_parity(hw, 0);
3309
3310	if (hwstatus & IS_M2_PAR_ERR)
3311		skge_mac_parity(hw, 1);
3312
3313	if (hwstatus & IS_R1_PAR_ERR) {
3314		dev_err(&pdev->dev, "%s: receive queue parity error\n",
3315			hw->dev[0]->name);
3316		skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
3317	}
3318
3319	if (hwstatus & IS_R2_PAR_ERR) {
3320		dev_err(&pdev->dev, "%s: receive queue parity error\n",
3321			hw->dev[1]->name);
3322		skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
3323	}
3324
3325	if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
3326		u16 pci_status, pci_cmd;
3327
3328		pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3329		pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3330
3331		dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3332			pci_cmd, pci_status);
3333
3334		/* Write the error bits back to clear them. */
3335		pci_status &= PCI_STATUS_ERROR_BITS;
3336		skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3337		pci_write_config_word(pdev, PCI_COMMAND,
3338				      pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
3339		pci_write_config_word(pdev, PCI_STATUS, pci_status);
3340		skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3341
3342		/* if error still set then just ignore it */
3343		hwstatus = skge_read32(hw, B0_HWE_ISRC);
3344		if (hwstatus & IS_IRQ_STAT) {
3345			dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
3346			hw->intr_mask &= ~IS_HW_ERR;
3347		}
3348	}
3349}
3350
3351/*
3352 * Interrupt from PHY are handled in tasklet (softirq)
3353 * because accessing phy registers requires spin wait which might
3354 * cause excess interrupt latency.
3355 */
3356static void skge_extirq(unsigned long arg)
3357{
3358	struct skge_hw *hw = (struct skge_hw *) arg;
3359	int port;
3360
3361	for (port = 0; port < hw->ports; port++) {
3362		struct net_device *dev = hw->dev[port];
3363
3364		if (netif_running(dev)) {
3365			struct skge_port *skge = netdev_priv(dev);
3366
3367			spin_lock(&hw->phy_lock);
3368			if (!is_genesis(hw))
3369				yukon_phy_intr(skge);
3370			else if (hw->phy_type == SK_PHY_BCOM)
3371				bcom_phy_intr(skge);
3372			spin_unlock(&hw->phy_lock);
3373		}
3374	}
3375
3376	spin_lock_irq(&hw->hw_lock);
3377	hw->intr_mask |= IS_EXT_REG;
3378	skge_write32(hw, B0_IMSK, hw->intr_mask);
3379	skge_read32(hw, B0_IMSK);
3380	spin_unlock_irq(&hw->hw_lock);
3381}
3382
3383static irqreturn_t skge_intr(int irq, void *dev_id)
3384{
3385	struct skge_hw *hw = dev_id;
3386	u32 status;
3387	int handled = 0;
3388
3389	spin_lock(&hw->hw_lock);
3390	/* Reading this register masks IRQ */
3391	status = skge_read32(hw, B0_SP_ISRC);
3392	if (status == 0 || status == ~0)
3393		goto out;
3394
3395	handled = 1;
3396	status &= hw->intr_mask;
3397	if (status & IS_EXT_REG) {
3398		hw->intr_mask &= ~IS_EXT_REG;
3399		tasklet_schedule(&hw->phy_task);
3400	}
3401
3402	if (status & (IS_XA1_F|IS_R1_F)) {
3403		struct skge_port *skge = netdev_priv(hw->dev[0]);
3404		hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
3405		napi_schedule(&skge->napi);
3406	}
3407
3408	if (status & IS_PA_TO_TX1)
3409		skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3410
3411	if (status & IS_PA_TO_RX1) {
3412		++hw->dev[0]->stats.rx_over_errors;
3413		skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3414	}
3415
3416
3417	if (status & IS_MAC1)
3418		skge_mac_intr(hw, 0);
3419
3420	if (hw->dev[1]) {
3421		struct skge_port *skge = netdev_priv(hw->dev[1]);
3422
3423		if (status & (IS_XA2_F|IS_R2_F)) {
3424			hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
3425			napi_schedule(&skge->napi);
3426		}
3427
3428		if (status & IS_PA_TO_RX2) {
3429			++hw->dev[1]->stats.rx_over_errors;
3430			skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3431		}
3432
3433		if (status & IS_PA_TO_TX2)
3434			skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3435
3436		if (status & IS_MAC2)
3437			skge_mac_intr(hw, 1);
3438	}
3439
3440	if (status & IS_HW_ERR)
3441		skge_error_irq(hw);
3442out:
3443	skge_write32(hw, B0_IMSK, hw->intr_mask);
3444	skge_read32(hw, B0_IMSK);
3445	spin_unlock(&hw->hw_lock);
3446
3447	return IRQ_RETVAL(handled);
3448}
3449
3450#ifdef CONFIG_NET_POLL_CONTROLLER
3451static void skge_netpoll(struct net_device *dev)
3452{
3453	struct skge_port *skge = netdev_priv(dev);
3454
3455	disable_irq(dev->irq);
3456	skge_intr(dev->irq, skge->hw);
3457	enable_irq(dev->irq);
3458}
3459#endif
3460
3461static int skge_set_mac_address(struct net_device *dev, void *p)
3462{
3463	struct skge_port *skge = netdev_priv(dev);
3464	struct skge_hw *hw = skge->hw;
3465	unsigned port = skge->port;
3466	const struct sockaddr *addr = p;
3467	u16 ctrl;
3468
3469	if (!is_valid_ether_addr(addr->sa_data))
3470		return -EADDRNOTAVAIL;
3471
3472	memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3473
3474	if (!netif_running(dev)) {
3475		memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3476		memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3477	} else {
3478		/* disable Rx */
3479		spin_lock_bh(&hw->phy_lock);
3480		ctrl = gma_read16(hw, port, GM_GP_CTRL);
3481		gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3482
3483		memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3484		memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3485
3486		if (is_genesis(hw))
3487			xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3488		else {
3489			gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3490			gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3491		}
3492
3493		gma_write16(hw, port, GM_GP_CTRL, ctrl);
3494		spin_unlock_bh(&hw->phy_lock);
3495	}
3496
3497	return 0;
3498}
3499
3500static const struct {
3501	u8 id;
3502	const char *name;
3503} skge_chips[] = {
3504	{ CHIP_ID_GENESIS,	"Genesis" },
3505	{ CHIP_ID_YUKON,	 "Yukon" },
3506	{ CHIP_ID_YUKON_LITE,	 "Yukon-Lite"},
3507	{ CHIP_ID_YUKON_LP,	 "Yukon-LP"},
3508};
3509
3510static const char *skge_board_name(const struct skge_hw *hw)
3511{
3512	int i;
3513	static char buf[16];
3514
3515	for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3516		if (skge_chips[i].id == hw->chip_id)
3517			return skge_chips[i].name;
3518
3519	snprintf(buf, sizeof(buf), "chipid 0x%x", hw->chip_id);
3520	return buf;
3521}
3522
3523
3524/*
3525 * Setup the board data structure, but don't bring up
3526 * the port(s)
3527 */
3528static int skge_reset(struct skge_hw *hw)
3529{
3530	u32 reg;
3531	u16 ctst, pci_status;
3532	u8 t8, mac_cfg, pmd_type;
3533	int i;
3534
3535	ctst = skge_read16(hw, B0_CTST);
3536
3537	/* do a SW reset */
3538	skge_write8(hw, B0_CTST, CS_RST_SET);
3539	skge_write8(hw, B0_CTST, CS_RST_CLR);
3540
3541	/* clear PCI errors, if any */
3542	skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3543	skge_write8(hw, B2_TST_CTRL2, 0);
3544
3545	pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3546	pci_write_config_word(hw->pdev, PCI_STATUS,
3547			      pci_status | PCI_STATUS_ERROR_BITS);
3548	skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3549	skge_write8(hw, B0_CTST, CS_MRST_CLR);
3550
3551	/* restore CLK_RUN bits (for Yukon-Lite) */
3552	skge_write16(hw, B0_CTST,
3553		     ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3554
3555	hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3556	hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
3557	pmd_type = skge_read8(hw, B2_PMD_TYP);
3558	hw->copper = (pmd_type == 'T' || pmd_type == '1');
3559
3560	switch (hw->chip_id) {
3561	case CHIP_ID_GENESIS:
3562#ifdef CONFIG_SKGE_GENESIS
3563		switch (hw->phy_type) {
3564		case SK_PHY_XMAC:
3565			hw->phy_addr = PHY_ADDR_XMAC;
3566			break;
3567		case SK_PHY_BCOM:
3568			hw->phy_addr = PHY_ADDR_BCOM;
3569			break;
3570		default:
3571			dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3572			       hw->phy_type);
3573			return -EOPNOTSUPP;
3574		}
3575		break;
3576#else
3577		dev_err(&hw->pdev->dev, "Genesis chip detected but not configured\n");
3578		return -EOPNOTSUPP;
3579#endif
3580
3581	case CHIP_ID_YUKON:
3582	case CHIP_ID_YUKON_LITE:
3583	case CHIP_ID_YUKON_LP:
3584		if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3585			hw->copper = 1;
3586
3587		hw->phy_addr = PHY_ADDR_MARV;
3588		break;
3589
3590	default:
3591		dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3592		       hw->chip_id);
3593		return -EOPNOTSUPP;
3594	}
3595
3596	mac_cfg = skge_read8(hw, B2_MAC_CFG);
3597	hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3598	hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3599
3600	/* read the adapters RAM size */
3601	t8 = skge_read8(hw, B2_E_0);
3602	if (is_genesis(hw)) {
3603		if (t8 == 3) {
3604			/* special case: 4 x 64k x 36, offset = 0x80000 */
3605			hw->ram_size = 0x100000;
3606			hw->ram_offset = 0x80000;
3607		} else
3608			hw->ram_size = t8 * 512;
3609	} else if (t8 == 0)
3610		hw->ram_size = 0x20000;
3611	else
3612		hw->ram_size = t8 * 4096;
3613
3614	hw->intr_mask = IS_HW_ERR;
3615
3616	/* Use PHY IRQ for all but fiber based Genesis board */
3617	if (!(is_genesis(hw) && hw->phy_type == SK_PHY_XMAC))
3618		hw->intr_mask |= IS_EXT_REG;
3619
3620	if (is_genesis(hw))
3621		genesis_init(hw);
3622	else {
3623		/* switch power to VCC (WA for VAUX problem) */
3624		skge_write8(hw, B0_POWER_CTRL,
3625			    PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3626
3627		/* avoid boards with stuck Hardware error bits */
3628		if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3629		    (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3630			dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
3631			hw->intr_mask &= ~IS_HW_ERR;
3632		}
3633
3634		/* Clear PHY COMA */
3635		skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3636		pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3637		reg &= ~PCI_PHY_COMA;
3638		pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3639		skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3640
3641
3642		for (i = 0; i < hw->ports; i++) {
3643			skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3644			skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3645		}
3646	}
3647
3648	/* turn off hardware timer (unused) */
3649	skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3650	skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3651	skge_write8(hw, B0_LED, LED_STAT_ON);
3652
3653	/* enable the Tx Arbiters */
3654	for (i = 0; i < hw->ports; i++)
3655		skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3656
3657	/* Initialize ram interface */
3658	skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3659
3660	skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3661	skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3662	skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3663	skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3664	skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3665	skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3666	skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3667	skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3668	skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3669	skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3670	skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3671	skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3672
3673	skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3674
3675	/* Set interrupt moderation for Transmit only
3676	 * Receive interrupts avoided by NAPI
3677	 */
3678	skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3679	skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3680	skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3681
3682	/* Leave irq disabled until first port is brought up. */
3683	skge_write32(hw, B0_IMSK, 0);
3684
3685	for (i = 0; i < hw->ports; i++) {
3686		if (is_genesis(hw))
3687			genesis_reset(hw, i);
3688		else
3689			yukon_reset(hw, i);
3690	}
3691
3692	return 0;
3693}
3694
3695
3696#ifdef CONFIG_SKGE_DEBUG
3697
3698static struct dentry *skge_debug;
3699
3700static int skge_debug_show(struct seq_file *seq, void *v)
3701{
3702	struct net_device *dev = seq->private;
3703	const struct skge_port *skge = netdev_priv(dev);
3704	const struct skge_hw *hw = skge->hw;
3705	const struct skge_element *e;
3706
3707	if (!netif_running(dev))
3708		return -ENETDOWN;
3709
3710	seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
3711		   skge_read32(hw, B0_IMSK));
3712
3713	seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring));
3714	for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
3715		const struct skge_tx_desc *t = e->desc;
3716		seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
3717			   t->control, t->dma_hi, t->dma_lo, t->status,
3718			   t->csum_offs, t->csum_write, t->csum_start);
3719	}
3720
3721	seq_puts(seq, "\nRx Ring:\n");
3722	for (e = skge->rx_ring.to_clean; ; e = e->next) {
3723		const struct skge_rx_desc *r = e->desc;
3724
3725		if (r->control & BMU_OWN)
3726			break;
3727
3728		seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
3729			   r->control, r->dma_hi, r->dma_lo, r->status,
3730			   r->timestamp, r->csum1, r->csum1_start);
3731	}
3732
3733	return 0;
3734}
3735
3736static int skge_debug_open(struct inode *inode, struct file *file)
3737{
3738	return single_open(file, skge_debug_show, inode->i_private);
3739}
3740
3741static const struct file_operations skge_debug_fops = {
3742	.owner		= THIS_MODULE,
3743	.open		= skge_debug_open,
3744	.read		= seq_read,
3745	.llseek		= seq_lseek,
3746	.release	= single_release,
3747};
3748
3749/*
3750 * Use network device events to create/remove/rename
3751 * debugfs file entries
3752 */
3753static int skge_device_event(struct notifier_block *unused,
3754			     unsigned long event, void *ptr)
3755{
3756	struct net_device *dev = netdev_notifier_info_to_dev(ptr);
3757	struct skge_port *skge;
3758	struct dentry *d;
3759
3760	if (dev->netdev_ops->ndo_open != &skge_up || !skge_debug)
3761		goto done;
3762
3763	skge = netdev_priv(dev);
3764	switch (event) {
3765	case NETDEV_CHANGENAME:
3766		if (skge->debugfs) {
3767			d = debugfs_rename(skge_debug, skge->debugfs,
3768					   skge_debug, dev->name);
3769			if (d)
3770				skge->debugfs = d;
3771			else {
3772				netdev_info(dev, "rename failed\n");
3773				debugfs_remove(skge->debugfs);
3774			}
3775		}
3776		break;
3777
3778	case NETDEV_GOING_DOWN:
3779		if (skge->debugfs) {
3780			debugfs_remove(skge->debugfs);
3781			skge->debugfs = NULL;
3782		}
3783		break;
3784
3785	case NETDEV_UP:
3786		d = debugfs_create_file(dev->name, 0444,
3787					skge_debug, dev,
3788					&skge_debug_fops);
3789		if (!d || IS_ERR(d))
3790			netdev_info(dev, "debugfs create failed\n");
3791		else
3792			skge->debugfs = d;
3793		break;
3794	}
3795
3796done:
3797	return NOTIFY_DONE;
3798}
3799
3800static struct notifier_block skge_notifier = {
3801	.notifier_call = skge_device_event,
3802};
3803
3804
3805static __init void skge_debug_init(void)
3806{
3807	struct dentry *ent;
3808
3809	ent = debugfs_create_dir("skge", NULL);
3810	if (!ent || IS_ERR(ent)) {
3811		pr_info("debugfs create directory failed\n");
3812		return;
3813	}
3814
3815	skge_debug = ent;
3816	register_netdevice_notifier(&skge_notifier);
3817}
3818
3819static __exit void skge_debug_cleanup(void)
3820{
3821	if (skge_debug) {
3822		unregister_netdevice_notifier(&skge_notifier);
3823		debugfs_remove(skge_debug);
3824		skge_debug = NULL;
3825	}
3826}
3827
3828#else
3829#define skge_debug_init()
3830#define skge_debug_cleanup()
3831#endif
3832
3833static const struct net_device_ops skge_netdev_ops = {
3834	.ndo_open		= skge_up,
3835	.ndo_stop		= skge_down,
3836	.ndo_start_xmit		= skge_xmit_frame,
3837	.ndo_do_ioctl		= skge_ioctl,
3838	.ndo_get_stats		= skge_get_stats,
3839	.ndo_tx_timeout		= skge_tx_timeout,
3840	.ndo_change_mtu		= skge_change_mtu,
3841	.ndo_validate_addr	= eth_validate_addr,
3842	.ndo_set_rx_mode	= skge_set_multicast,
3843	.ndo_set_mac_address	= skge_set_mac_address,
3844#ifdef CONFIG_NET_POLL_CONTROLLER
3845	.ndo_poll_controller	= skge_netpoll,
3846#endif
3847};
3848
3849
3850/* Initialize network device */
3851static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3852				       int highmem)
3853{
3854	struct skge_port *skge;
3855	struct net_device *dev = alloc_etherdev(sizeof(*skge));
3856
3857	if (!dev)
3858		return NULL;
3859
3860	SET_NETDEV_DEV(dev, &hw->pdev->dev);
3861	dev->netdev_ops = &skge_netdev_ops;
3862	dev->ethtool_ops = &skge_ethtool_ops;
3863	dev->watchdog_timeo = TX_WATCHDOG;
3864	dev->irq = hw->pdev->irq;
3865
3866	/* MTU range: 60 - 9000 */
3867	dev->min_mtu = ETH_ZLEN;
3868	dev->max_mtu = ETH_JUMBO_MTU;
3869
3870	if (highmem)
3871		dev->features |= NETIF_F_HIGHDMA;
3872
3873	skge = netdev_priv(dev);
3874	netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT);
3875	skge->netdev = dev;
3876	skge->hw = hw;
3877	skge->msg_enable = netif_msg_init(debug, default_msg);
3878
3879	skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3880	skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3881
3882	/* Auto speed and flow control */
3883	skge->autoneg = AUTONEG_ENABLE;
3884	skge->flow_control = FLOW_MODE_SYM_OR_REM;
3885	skge->duplex = -1;
3886	skge->speed = -1;
3887	skge->advertising = skge_supported_modes(hw);
3888
3889	if (device_can_wakeup(&hw->pdev->dev)) {
3890		skge->wol = wol_supported(hw) & WAKE_MAGIC;
3891		device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
3892	}
3893
3894	hw->dev[port] = dev;
3895
3896	skge->port = port;
3897
3898	/* Only used for Genesis XMAC */
3899	if (is_genesis(hw))
3900	    timer_setup(&skge->link_timer, xm_link_timer, 0);
3901	else {
3902		dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
3903		                   NETIF_F_RXCSUM;
3904		dev->features |= dev->hw_features;
3905	}
3906
3907	/* read the mac address */
3908	memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3909
3910	return dev;
3911}
3912
3913static void skge_show_addr(struct net_device *dev)
3914{
3915	const struct skge_port *skge = netdev_priv(dev);
3916
3917	netif_info(skge, probe, skge->netdev, "addr %pM\n", dev->dev_addr);
3918}
3919
3920static int only_32bit_dma;
3921
3922static int skge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3923{
3924	struct net_device *dev, *dev1;
3925	struct skge_hw *hw;
3926	int err, using_dac = 0;
3927
3928	err = pci_enable_device(pdev);
3929	if (err) {
3930		dev_err(&pdev->dev, "cannot enable PCI device\n");
3931		goto err_out;
3932	}
3933
3934	err = pci_request_regions(pdev, DRV_NAME);
3935	if (err) {
3936		dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3937		goto err_out_disable_pdev;
3938	}
3939
3940	pci_set_master(pdev);
3941
3942	if (!only_32bit_dma && !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3943		using_dac = 1;
3944		err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3945	} else if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
3946		using_dac = 0;
3947		err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3948	}
3949
3950	if (err) {
3951		dev_err(&pdev->dev, "no usable DMA configuration\n");
3952		goto err_out_free_regions;
3953	}
3954
3955#ifdef __BIG_ENDIAN
3956	/* byte swap descriptors in hardware */
3957	{
3958		u32 reg;
3959
3960		pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3961		reg |= PCI_REV_DESC;
3962		pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3963	}
3964#endif
3965
3966	err = -ENOMEM;
3967	/* space for skge@pci:0000:04:00.0 */
3968	hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
3969		     + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
3970	if (!hw)
3971		goto err_out_free_regions;
3972
3973	sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
3974
3975	hw->pdev = pdev;
3976	spin_lock_init(&hw->hw_lock);
3977	spin_lock_init(&hw->phy_lock);
3978	tasklet_init(&hw->phy_task, skge_extirq, (unsigned long) hw);
3979
3980	hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3981	if (!hw->regs) {
3982		dev_err(&pdev->dev, "cannot map device registers\n");
3983		goto err_out_free_hw;
3984	}
3985
3986	err = skge_reset(hw);
3987	if (err)
3988		goto err_out_iounmap;
3989
3990	pr_info("%s addr 0x%llx irq %d chip %s rev %d\n",
3991		DRV_VERSION,
3992		(unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3993		skge_board_name(hw), hw->chip_rev);
3994
3995	dev = skge_devinit(hw, 0, using_dac);
3996	if (!dev) {
3997		err = -ENOMEM;
3998		goto err_out_led_off;
3999	}
4000
4001	/* Some motherboards are broken and has zero in ROM. */
4002	if (!is_valid_ether_addr(dev->dev_addr))
4003		dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
4004
4005	err = register_netdev(dev);
4006	if (err) {
4007		dev_err(&pdev->dev, "cannot register net device\n");
4008		goto err_out_free_netdev;
4009	}
4010
4011	skge_show_addr(dev);
4012
4013	if (hw->ports > 1) {
4014		dev1 = skge_devinit(hw, 1, using_dac);
4015		if (!dev1) {
4016			err = -ENOMEM;
4017			goto err_out_unregister;
4018		}
4019
4020		err = register_netdev(dev1);
4021		if (err) {
4022			dev_err(&pdev->dev, "cannot register second net device\n");
4023			goto err_out_free_dev1;
4024		}
4025
4026		err = request_irq(pdev->irq, skge_intr, IRQF_SHARED,
4027				  hw->irq_name, hw);
4028		if (err) {
4029			dev_err(&pdev->dev, "cannot assign irq %d\n",
4030				pdev->irq);
4031			goto err_out_unregister_dev1;
4032		}
4033
4034		skge_show_addr(dev1);
4035	}
4036	pci_set_drvdata(pdev, hw);
4037
4038	return 0;
4039
4040err_out_unregister_dev1:
4041	unregister_netdev(dev1);
4042err_out_free_dev1:
4043	free_netdev(dev1);
4044err_out_unregister:
4045	unregister_netdev(dev);
4046err_out_free_netdev:
4047	free_netdev(dev);
4048err_out_led_off:
4049	skge_write16(hw, B0_LED, LED_STAT_OFF);
4050err_out_iounmap:
4051	iounmap(hw->regs);
4052err_out_free_hw:
4053	kfree(hw);
4054err_out_free_regions:
4055	pci_release_regions(pdev);
4056err_out_disable_pdev:
4057	pci_disable_device(pdev);
4058err_out:
4059	return err;
4060}
4061
4062static void skge_remove(struct pci_dev *pdev)
4063{
4064	struct skge_hw *hw  = pci_get_drvdata(pdev);
4065	struct net_device *dev0, *dev1;
4066
4067	if (!hw)
4068		return;
4069
4070	dev1 = hw->dev[1];
4071	if (dev1)
4072		unregister_netdev(dev1);
4073	dev0 = hw->dev[0];
4074	unregister_netdev(dev0);
4075
4076	tasklet_kill(&hw->phy_task);
4077
4078	spin_lock_irq(&hw->hw_lock);
4079	hw->intr_mask = 0;
4080
4081	if (hw->ports > 1) {
4082		skge_write32(hw, B0_IMSK, 0);
4083		skge_read32(hw, B0_IMSK);
4084	}
4085	spin_unlock_irq(&hw->hw_lock);
4086
4087	skge_write16(hw, B0_LED, LED_STAT_OFF);
4088	skge_write8(hw, B0_CTST, CS_RST_SET);
4089
4090	if (hw->ports > 1)
4091		free_irq(pdev->irq, hw);
4092	pci_release_regions(pdev);
4093	pci_disable_device(pdev);
4094	if (dev1)
4095		free_netdev(dev1);
4096	free_netdev(dev0);
4097
4098	iounmap(hw->regs);
4099	kfree(hw);
4100}
4101
4102#ifdef CONFIG_PM_SLEEP
4103static int skge_suspend(struct device *dev)
4104{
4105	struct pci_dev *pdev = to_pci_dev(dev);
4106	struct skge_hw *hw  = pci_get_drvdata(pdev);
4107	int i;
4108
4109	if (!hw)
4110		return 0;
4111
4112	for (i = 0; i < hw->ports; i++) {
4113		struct net_device *dev = hw->dev[i];
4114		struct skge_port *skge = netdev_priv(dev);
4115
4116		if (netif_running(dev))
4117			skge_down(dev);
4118
4119		if (skge->wol)
4120			skge_wol_init(skge);
4121	}
4122
4123	skge_write32(hw, B0_IMSK, 0);
4124
4125	return 0;
4126}
4127
4128static int skge_resume(struct device *dev)
4129{
4130	struct pci_dev *pdev = to_pci_dev(dev);
4131	struct skge_hw *hw  = pci_get_drvdata(pdev);
4132	int i, err;
4133
4134	if (!hw)
4135		return 0;
4136
4137	err = skge_reset(hw);
4138	if (err)
4139		goto out;
4140
4141	for (i = 0; i < hw->ports; i++) {
4142		struct net_device *dev = hw->dev[i];
4143
4144		if (netif_running(dev)) {
4145			err = skge_up(dev);
4146
4147			if (err) {
4148				netdev_err(dev, "could not up: %d\n", err);
4149				dev_close(dev);
4150				goto out;
4151			}
4152		}
4153	}
4154out:
4155	return err;
4156}
4157
4158static SIMPLE_DEV_PM_OPS(skge_pm_ops, skge_suspend, skge_resume);
4159#define SKGE_PM_OPS (&skge_pm_ops)
4160
4161#else
4162
4163#define SKGE_PM_OPS NULL
4164#endif /* CONFIG_PM_SLEEP */
4165
4166static void skge_shutdown(struct pci_dev *pdev)
4167{
4168	struct skge_hw *hw  = pci_get_drvdata(pdev);
4169	int i;
4170
4171	if (!hw)
4172		return;
4173
4174	for (i = 0; i < hw->ports; i++) {
4175		struct net_device *dev = hw->dev[i];
4176		struct skge_port *skge = netdev_priv(dev);
4177
4178		if (skge->wol)
4179			skge_wol_init(skge);
4180	}
4181
4182	pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
4183	pci_set_power_state(pdev, PCI_D3hot);
4184}
4185
4186static struct pci_driver skge_driver = {
4187	.name =         DRV_NAME,
4188	.id_table =     skge_id_table,
4189	.probe =        skge_probe,
4190	.remove =       skge_remove,
4191	.shutdown =	skge_shutdown,
4192	.driver.pm =	SKGE_PM_OPS,
4193};
4194
4195static const struct dmi_system_id skge_32bit_dma_boards[] = {
4196	{
4197		.ident = "Gigabyte nForce boards",
4198		.matches = {
4199			DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co"),
4200			DMI_MATCH(DMI_BOARD_NAME, "nForce"),
4201		},
4202	},
4203	{
4204		.ident = "ASUS P5NSLI",
4205		.matches = {
4206			DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
4207			DMI_MATCH(DMI_BOARD_NAME, "P5NSLI")
4208		},
4209	},
4210	{
4211		.ident = "FUJITSU SIEMENS A8NE-FM",
4212		.matches = {
4213			DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTek Computer INC."),
4214			DMI_MATCH(DMI_BOARD_NAME, "A8NE-FM")
4215		},
4216	},
4217	{}
4218};
4219
4220static int __init skge_init_module(void)
4221{
4222	if (dmi_check_system(skge_32bit_dma_boards))
4223		only_32bit_dma = 1;
4224	skge_debug_init();
4225	return pci_register_driver(&skge_driver);
4226}
4227
4228static void __exit skge_cleanup_module(void)
4229{
4230	pci_unregister_driver(&skge_driver);
4231	skge_debug_cleanup();
4232}
4233
4234module_init(skge_init_module);
4235module_exit(skge_cleanup_module);