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1/*
2 *
3 * Alchemy Au1x00 ethernet driver
4 *
5 * Copyright 2001-2003, 2006 MontaVista Software Inc.
6 * Copyright 2002 TimeSys Corp.
7 * Added ethtool/mii-tool support,
8 * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
9 * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de
10 * or riemer@riemer-nt.de: fixed the link beat detection with
11 * ioctls (SIOCGMIIPHY)
12 * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org>
13 * converted to use linux-2.6.x's PHY framework
14 *
15 * Author: MontaVista Software, Inc.
16 * ppopov@mvista.com or source@mvista.com
17 *
18 * ########################################################################
19 *
20 * This program is free software; you can distribute it and/or modify it
21 * under the terms of the GNU General Public License (Version 2) as
22 * published by the Free Software Foundation.
23 *
24 * This program is distributed in the hope it will be useful, but WITHOUT
25 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
26 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
27 * for more details.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
32 *
33 * ########################################################################
34 *
35 *
36 */
37#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
38
39#include <linux/capability.h>
40#include <linux/dma-mapping.h>
41#include <linux/module.h>
42#include <linux/kernel.h>
43#include <linux/string.h>
44#include <linux/timer.h>
45#include <linux/errno.h>
46#include <linux/in.h>
47#include <linux/ioport.h>
48#include <linux/bitops.h>
49#include <linux/slab.h>
50#include <linux/interrupt.h>
51#include <linux/init.h>
52#include <linux/netdevice.h>
53#include <linux/etherdevice.h>
54#include <linux/ethtool.h>
55#include <linux/mii.h>
56#include <linux/skbuff.h>
57#include <linux/delay.h>
58#include <linux/crc32.h>
59#include <linux/phy.h>
60#include <linux/platform_device.h>
61#include <linux/cpu.h>
62#include <linux/io.h>
63
64#include <asm/mipsregs.h>
65#include <asm/irq.h>
66#include <asm/processor.h>
67
68#include <au1000.h>
69#include <au1xxx_eth.h>
70#include <prom.h>
71
72#include "au1000_eth.h"
73
74#ifdef AU1000_ETH_DEBUG
75static int au1000_debug = 5;
76#else
77static int au1000_debug = 3;
78#endif
79
80#define AU1000_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
81 NETIF_MSG_PROBE | \
82 NETIF_MSG_LINK)
83
84#define DRV_NAME "au1000_eth"
85#define DRV_VERSION "1.7"
86#define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>"
87#define DRV_DESC "Au1xxx on-chip Ethernet driver"
88
89MODULE_AUTHOR(DRV_AUTHOR);
90MODULE_DESCRIPTION(DRV_DESC);
91MODULE_LICENSE("GPL");
92MODULE_VERSION(DRV_VERSION);
93
94/*
95 * Theory of operation
96 *
97 * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
98 * There are four receive and four transmit descriptors. These
99 * descriptors are not in memory; rather, they are just a set of
100 * hardware registers.
101 *
102 * Since the Au1000 has a coherent data cache, the receive and
103 * transmit buffers are allocated from the KSEG0 segment. The
104 * hardware registers, however, are still mapped at KSEG1 to
105 * make sure there's no out-of-order writes, and that all writes
106 * complete immediately.
107 */
108
109/*
110 * board-specific configurations
111 *
112 * PHY detection algorithm
113 *
114 * If phy_static_config is undefined, the PHY setup is
115 * autodetected:
116 *
117 * mii_probe() first searches the current MAC's MII bus for a PHY,
118 * selecting the first (or last, if phy_search_highest_addr is
119 * defined) PHY address not already claimed by another netdev.
120 *
121 * If nothing was found that way when searching for the 2nd ethernet
122 * controller's PHY and phy1_search_mac0 is defined, then
123 * the first MII bus is searched as well for an unclaimed PHY; this is
124 * needed in case of a dual-PHY accessible only through the MAC0's MII
125 * bus.
126 *
127 * Finally, if no PHY is found, then the corresponding ethernet
128 * controller is not registered to the network subsystem.
129 */
130
131/* autodetection defaults: phy1_search_mac0 */
132
133/* static PHY setup
134 *
135 * most boards PHY setup should be detectable properly with the
136 * autodetection algorithm in mii_probe(), but in some cases (e.g. if
137 * you have a switch attached, or want to use the PHY's interrupt
138 * notification capabilities) you can provide a static PHY
139 * configuration here
140 *
141 * IRQs may only be set, if a PHY address was configured
142 * If a PHY address is given, also a bus id is required to be set
143 *
144 * ps: make sure the used irqs are configured properly in the board
145 * specific irq-map
146 */
147
148static void au1000_enable_mac(struct net_device *dev, int force_reset)
149{
150 unsigned long flags;
151 struct au1000_private *aup = netdev_priv(dev);
152
153 spin_lock_irqsave(&aup->lock, flags);
154
155 if (force_reset || (!aup->mac_enabled)) {
156 writel(MAC_EN_CLOCK_ENABLE, aup->enable);
157 au_sync_delay(2);
158 writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2
159 | MAC_EN_CLOCK_ENABLE), aup->enable);
160 au_sync_delay(2);
161
162 aup->mac_enabled = 1;
163 }
164
165 spin_unlock_irqrestore(&aup->lock, flags);
166}
167
168/*
169 * MII operations
170 */
171static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg)
172{
173 struct au1000_private *aup = netdev_priv(dev);
174 u32 *const mii_control_reg = &aup->mac->mii_control;
175 u32 *const mii_data_reg = &aup->mac->mii_data;
176 u32 timedout = 20;
177 u32 mii_control;
178
179 while (readl(mii_control_reg) & MAC_MII_BUSY) {
180 mdelay(1);
181 if (--timedout == 0) {
182 netdev_err(dev, "read_MII busy timeout!!\n");
183 return -1;
184 }
185 }
186
187 mii_control = MAC_SET_MII_SELECT_REG(reg) |
188 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ;
189
190 writel(mii_control, mii_control_reg);
191
192 timedout = 20;
193 while (readl(mii_control_reg) & MAC_MII_BUSY) {
194 mdelay(1);
195 if (--timedout == 0) {
196 netdev_err(dev, "mdio_read busy timeout!!\n");
197 return -1;
198 }
199 }
200 return readl(mii_data_reg);
201}
202
203static void au1000_mdio_write(struct net_device *dev, int phy_addr,
204 int reg, u16 value)
205{
206 struct au1000_private *aup = netdev_priv(dev);
207 u32 *const mii_control_reg = &aup->mac->mii_control;
208 u32 *const mii_data_reg = &aup->mac->mii_data;
209 u32 timedout = 20;
210 u32 mii_control;
211
212 while (readl(mii_control_reg) & MAC_MII_BUSY) {
213 mdelay(1);
214 if (--timedout == 0) {
215 netdev_err(dev, "mdio_write busy timeout!!\n");
216 return;
217 }
218 }
219
220 mii_control = MAC_SET_MII_SELECT_REG(reg) |
221 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE;
222
223 writel(value, mii_data_reg);
224 writel(mii_control, mii_control_reg);
225}
226
227static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
228{
229 /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does
230 * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus)
231 */
232 struct net_device *const dev = bus->priv;
233
234 /* make sure the MAC associated with this
235 * mii_bus is enabled
236 */
237 au1000_enable_mac(dev, 0);
238
239 return au1000_mdio_read(dev, phy_addr, regnum);
240}
241
242static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
243 u16 value)
244{
245 struct net_device *const dev = bus->priv;
246
247 /* make sure the MAC associated with this
248 * mii_bus is enabled
249 */
250 au1000_enable_mac(dev, 0);
251
252 au1000_mdio_write(dev, phy_addr, regnum, value);
253 return 0;
254}
255
256static int au1000_mdiobus_reset(struct mii_bus *bus)
257{
258 struct net_device *const dev = bus->priv;
259
260 /* make sure the MAC associated with this
261 * mii_bus is enabled
262 */
263 au1000_enable_mac(dev, 0);
264
265 return 0;
266}
267
268static void au1000_hard_stop(struct net_device *dev)
269{
270 struct au1000_private *aup = netdev_priv(dev);
271 u32 reg;
272
273 netif_dbg(aup, drv, dev, "hard stop\n");
274
275 reg = readl(&aup->mac->control);
276 reg &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
277 writel(reg, &aup->mac->control);
278 au_sync_delay(10);
279}
280
281static void au1000_enable_rx_tx(struct net_device *dev)
282{
283 struct au1000_private *aup = netdev_priv(dev);
284 u32 reg;
285
286 netif_dbg(aup, hw, dev, "enable_rx_tx\n");
287
288 reg = readl(&aup->mac->control);
289 reg |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
290 writel(reg, &aup->mac->control);
291 au_sync_delay(10);
292}
293
294static void
295au1000_adjust_link(struct net_device *dev)
296{
297 struct au1000_private *aup = netdev_priv(dev);
298 struct phy_device *phydev = aup->phy_dev;
299 unsigned long flags;
300 u32 reg;
301
302 int status_change = 0;
303
304 BUG_ON(!aup->phy_dev);
305
306 spin_lock_irqsave(&aup->lock, flags);
307
308 if (phydev->link && (aup->old_speed != phydev->speed)) {
309 /* speed changed */
310
311 switch (phydev->speed) {
312 case SPEED_10:
313 case SPEED_100:
314 break;
315 default:
316 netdev_warn(dev, "Speed (%d) is not 10/100 ???\n",
317 phydev->speed);
318 break;
319 }
320
321 aup->old_speed = phydev->speed;
322
323 status_change = 1;
324 }
325
326 if (phydev->link && (aup->old_duplex != phydev->duplex)) {
327 /* duplex mode changed */
328
329 /* switching duplex mode requires to disable rx and tx! */
330 au1000_hard_stop(dev);
331
332 reg = readl(&aup->mac->control);
333 if (DUPLEX_FULL == phydev->duplex) {
334 reg |= MAC_FULL_DUPLEX;
335 reg &= ~MAC_DISABLE_RX_OWN;
336 } else {
337 reg &= ~MAC_FULL_DUPLEX;
338 reg |= MAC_DISABLE_RX_OWN;
339 }
340 writel(reg, &aup->mac->control);
341 au_sync_delay(1);
342
343 au1000_enable_rx_tx(dev);
344 aup->old_duplex = phydev->duplex;
345
346 status_change = 1;
347 }
348
349 if (phydev->link != aup->old_link) {
350 /* link state changed */
351
352 if (!phydev->link) {
353 /* link went down */
354 aup->old_speed = 0;
355 aup->old_duplex = -1;
356 }
357
358 aup->old_link = phydev->link;
359 status_change = 1;
360 }
361
362 spin_unlock_irqrestore(&aup->lock, flags);
363
364 if (status_change) {
365 if (phydev->link)
366 netdev_info(dev, "link up (%d/%s)\n",
367 phydev->speed,
368 DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
369 else
370 netdev_info(dev, "link down\n");
371 }
372}
373
374static int au1000_mii_probe(struct net_device *dev)
375{
376 struct au1000_private *const aup = netdev_priv(dev);
377 struct phy_device *phydev = NULL;
378 int phy_addr;
379
380 if (aup->phy_static_config) {
381 BUG_ON(aup->mac_id < 0 || aup->mac_id > 1);
382
383 if (aup->phy_addr)
384 phydev = aup->mii_bus->phy_map[aup->phy_addr];
385 else
386 netdev_info(dev, "using PHY-less setup\n");
387 return 0;
388 }
389
390 /* find the first (lowest address) PHY
391 * on the current MAC's MII bus
392 */
393 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
394 if (aup->mii_bus->phy_map[phy_addr]) {
395 phydev = aup->mii_bus->phy_map[phy_addr];
396 if (!aup->phy_search_highest_addr)
397 /* break out with first one found */
398 break;
399 }
400
401 if (aup->phy1_search_mac0) {
402 /* try harder to find a PHY */
403 if (!phydev && (aup->mac_id == 1)) {
404 /* no PHY found, maybe we have a dual PHY? */
405 dev_info(&dev->dev, ": no PHY found on MAC1, "
406 "let's see if it's attached to MAC0...\n");
407
408 /* find the first (lowest address) non-attached
409 * PHY on the MAC0 MII bus
410 */
411 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
412 struct phy_device *const tmp_phydev =
413 aup->mii_bus->phy_map[phy_addr];
414
415 if (aup->mac_id == 1)
416 break;
417
418 /* no PHY here... */
419 if (!tmp_phydev)
420 continue;
421
422 /* already claimed by MAC0 */
423 if (tmp_phydev->attached_dev)
424 continue;
425
426 phydev = tmp_phydev;
427 break; /* found it */
428 }
429 }
430 }
431
432 if (!phydev) {
433 netdev_err(dev, "no PHY found\n");
434 return -1;
435 }
436
437 /* now we are supposed to have a proper phydev, to attach to... */
438 BUG_ON(phydev->attached_dev);
439
440 phydev = phy_connect(dev, dev_name(&phydev->dev), &au1000_adjust_link,
441 0, PHY_INTERFACE_MODE_MII);
442
443 if (IS_ERR(phydev)) {
444 netdev_err(dev, "Could not attach to PHY\n");
445 return PTR_ERR(phydev);
446 }
447
448 /* mask with MAC supported features */
449 phydev->supported &= (SUPPORTED_10baseT_Half
450 | SUPPORTED_10baseT_Full
451 | SUPPORTED_100baseT_Half
452 | SUPPORTED_100baseT_Full
453 | SUPPORTED_Autoneg
454 /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
455 | SUPPORTED_MII
456 | SUPPORTED_TP);
457
458 phydev->advertising = phydev->supported;
459
460 aup->old_link = 0;
461 aup->old_speed = 0;
462 aup->old_duplex = -1;
463 aup->phy_dev = phydev;
464
465 netdev_info(dev, "attached PHY driver [%s] "
466 "(mii_bus:phy_addr=%s, irq=%d)\n",
467 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
468
469 return 0;
470}
471
472
473/*
474 * Buffer allocation/deallocation routines. The buffer descriptor returned
475 * has the virtual and dma address of a buffer suitable for
476 * both, receive and transmit operations.
477 */
478static struct db_dest *au1000_GetFreeDB(struct au1000_private *aup)
479{
480 struct db_dest *pDB;
481 pDB = aup->pDBfree;
482
483 if (pDB)
484 aup->pDBfree = pDB->pnext;
485
486 return pDB;
487}
488
489void au1000_ReleaseDB(struct au1000_private *aup, struct db_dest *pDB)
490{
491 struct db_dest *pDBfree = aup->pDBfree;
492 if (pDBfree)
493 pDBfree->pnext = pDB;
494 aup->pDBfree = pDB;
495}
496
497static void au1000_reset_mac_unlocked(struct net_device *dev)
498{
499 struct au1000_private *const aup = netdev_priv(dev);
500 int i;
501
502 au1000_hard_stop(dev);
503
504 writel(MAC_EN_CLOCK_ENABLE, aup->enable);
505 au_sync_delay(2);
506 writel(0, aup->enable);
507 au_sync_delay(2);
508
509 aup->tx_full = 0;
510 for (i = 0; i < NUM_RX_DMA; i++) {
511 /* reset control bits */
512 aup->rx_dma_ring[i]->buff_stat &= ~0xf;
513 }
514 for (i = 0; i < NUM_TX_DMA; i++) {
515 /* reset control bits */
516 aup->tx_dma_ring[i]->buff_stat &= ~0xf;
517 }
518
519 aup->mac_enabled = 0;
520
521}
522
523static void au1000_reset_mac(struct net_device *dev)
524{
525 struct au1000_private *const aup = netdev_priv(dev);
526 unsigned long flags;
527
528 netif_dbg(aup, hw, dev, "reset mac, aup %x\n",
529 (unsigned)aup);
530
531 spin_lock_irqsave(&aup->lock, flags);
532
533 au1000_reset_mac_unlocked(dev);
534
535 spin_unlock_irqrestore(&aup->lock, flags);
536}
537
538/*
539 * Setup the receive and transmit "rings". These pointers are the addresses
540 * of the rx and tx MAC DMA registers so they are fixed by the hardware --
541 * these are not descriptors sitting in memory.
542 */
543static void
544au1000_setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base)
545{
546 int i;
547
548 for (i = 0; i < NUM_RX_DMA; i++) {
549 aup->rx_dma_ring[i] =
550 (struct rx_dma *)
551 (rx_base + sizeof(struct rx_dma)*i);
552 }
553 for (i = 0; i < NUM_TX_DMA; i++) {
554 aup->tx_dma_ring[i] =
555 (struct tx_dma *)
556 (tx_base + sizeof(struct tx_dma)*i);
557 }
558}
559
560/*
561 * ethtool operations
562 */
563
564static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
565{
566 struct au1000_private *aup = netdev_priv(dev);
567
568 if (aup->phy_dev)
569 return phy_ethtool_gset(aup->phy_dev, cmd);
570
571 return -EINVAL;
572}
573
574static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
575{
576 struct au1000_private *aup = netdev_priv(dev);
577
578 if (!capable(CAP_NET_ADMIN))
579 return -EPERM;
580
581 if (aup->phy_dev)
582 return phy_ethtool_sset(aup->phy_dev, cmd);
583
584 return -EINVAL;
585}
586
587static void
588au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
589{
590 struct au1000_private *aup = netdev_priv(dev);
591
592 strcpy(info->driver, DRV_NAME);
593 strcpy(info->version, DRV_VERSION);
594 info->fw_version[0] = '\0';
595 sprintf(info->bus_info, "%s %d", DRV_NAME, aup->mac_id);
596 info->regdump_len = 0;
597}
598
599static void au1000_set_msglevel(struct net_device *dev, u32 value)
600{
601 struct au1000_private *aup = netdev_priv(dev);
602 aup->msg_enable = value;
603}
604
605static u32 au1000_get_msglevel(struct net_device *dev)
606{
607 struct au1000_private *aup = netdev_priv(dev);
608 return aup->msg_enable;
609}
610
611static const struct ethtool_ops au1000_ethtool_ops = {
612 .get_settings = au1000_get_settings,
613 .set_settings = au1000_set_settings,
614 .get_drvinfo = au1000_get_drvinfo,
615 .get_link = ethtool_op_get_link,
616 .get_msglevel = au1000_get_msglevel,
617 .set_msglevel = au1000_set_msglevel,
618};
619
620
621/*
622 * Initialize the interface.
623 *
624 * When the device powers up, the clocks are disabled and the
625 * mac is in reset state. When the interface is closed, we
626 * do the same -- reset the device and disable the clocks to
627 * conserve power. Thus, whenever au1000_init() is called,
628 * the device should already be in reset state.
629 */
630static int au1000_init(struct net_device *dev)
631{
632 struct au1000_private *aup = netdev_priv(dev);
633 unsigned long flags;
634 int i;
635 u32 control;
636
637 netif_dbg(aup, hw, dev, "au1000_init\n");
638
639 /* bring the device out of reset */
640 au1000_enable_mac(dev, 1);
641
642 spin_lock_irqsave(&aup->lock, flags);
643
644 writel(0, &aup->mac->control);
645 aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
646 aup->tx_tail = aup->tx_head;
647 aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
648
649 writel(dev->dev_addr[5]<<8 | dev->dev_addr[4],
650 &aup->mac->mac_addr_high);
651 writel(dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
652 dev->dev_addr[1]<<8 | dev->dev_addr[0],
653 &aup->mac->mac_addr_low);
654
655
656 for (i = 0; i < NUM_RX_DMA; i++)
657 aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
658
659 au_sync();
660
661 control = MAC_RX_ENABLE | MAC_TX_ENABLE;
662#ifndef CONFIG_CPU_LITTLE_ENDIAN
663 control |= MAC_BIG_ENDIAN;
664#endif
665 if (aup->phy_dev) {
666 if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex))
667 control |= MAC_FULL_DUPLEX;
668 else
669 control |= MAC_DISABLE_RX_OWN;
670 } else { /* PHY-less op, assume full-duplex */
671 control |= MAC_FULL_DUPLEX;
672 }
673
674 writel(control, &aup->mac->control);
675 writel(0x8100, &aup->mac->vlan1_tag); /* activate vlan support */
676 au_sync();
677
678 spin_unlock_irqrestore(&aup->lock, flags);
679 return 0;
680}
681
682static inline void au1000_update_rx_stats(struct net_device *dev, u32 status)
683{
684 struct net_device_stats *ps = &dev->stats;
685
686 ps->rx_packets++;
687 if (status & RX_MCAST_FRAME)
688 ps->multicast++;
689
690 if (status & RX_ERROR) {
691 ps->rx_errors++;
692 if (status & RX_MISSED_FRAME)
693 ps->rx_missed_errors++;
694 if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR))
695 ps->rx_length_errors++;
696 if (status & RX_CRC_ERROR)
697 ps->rx_crc_errors++;
698 if (status & RX_COLL)
699 ps->collisions++;
700 } else
701 ps->rx_bytes += status & RX_FRAME_LEN_MASK;
702
703}
704
705/*
706 * Au1000 receive routine.
707 */
708static int au1000_rx(struct net_device *dev)
709{
710 struct au1000_private *aup = netdev_priv(dev);
711 struct sk_buff *skb;
712 struct rx_dma *prxd;
713 u32 buff_stat, status;
714 struct db_dest *pDB;
715 u32 frmlen;
716
717 netif_dbg(aup, rx_status, dev, "au1000_rx head %d\n", aup->rx_head);
718
719 prxd = aup->rx_dma_ring[aup->rx_head];
720 buff_stat = prxd->buff_stat;
721 while (buff_stat & RX_T_DONE) {
722 status = prxd->status;
723 pDB = aup->rx_db_inuse[aup->rx_head];
724 au1000_update_rx_stats(dev, status);
725 if (!(status & RX_ERROR)) {
726
727 /* good frame */
728 frmlen = (status & RX_FRAME_LEN_MASK);
729 frmlen -= 4; /* Remove FCS */
730 skb = dev_alloc_skb(frmlen + 2);
731 if (skb == NULL) {
732 netdev_err(dev, "Memory squeeze, dropping packet.\n");
733 dev->stats.rx_dropped++;
734 continue;
735 }
736 skb_reserve(skb, 2); /* 16 byte IP header align */
737 skb_copy_to_linear_data(skb,
738 (unsigned char *)pDB->vaddr, frmlen);
739 skb_put(skb, frmlen);
740 skb->protocol = eth_type_trans(skb, dev);
741 netif_rx(skb); /* pass the packet to upper layers */
742 } else {
743 if (au1000_debug > 4) {
744 pr_err("rx_error(s):");
745 if (status & RX_MISSED_FRAME)
746 pr_cont(" miss");
747 if (status & RX_WDOG_TIMER)
748 pr_cont(" wdog");
749 if (status & RX_RUNT)
750 pr_cont(" runt");
751 if (status & RX_OVERLEN)
752 pr_cont(" overlen");
753 if (status & RX_COLL)
754 pr_cont(" coll");
755 if (status & RX_MII_ERROR)
756 pr_cont(" mii error");
757 if (status & RX_CRC_ERROR)
758 pr_cont(" crc error");
759 if (status & RX_LEN_ERROR)
760 pr_cont(" len error");
761 if (status & RX_U_CNTRL_FRAME)
762 pr_cont(" u control frame");
763 pr_cont("\n");
764 }
765 }
766 prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
767 aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
768 au_sync();
769
770 /* next descriptor */
771 prxd = aup->rx_dma_ring[aup->rx_head];
772 buff_stat = prxd->buff_stat;
773 }
774 return 0;
775}
776
777static void au1000_update_tx_stats(struct net_device *dev, u32 status)
778{
779 struct au1000_private *aup = netdev_priv(dev);
780 struct net_device_stats *ps = &dev->stats;
781
782 if (status & TX_FRAME_ABORTED) {
783 if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) {
784 if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
785 /* any other tx errors are only valid
786 * in half duplex mode
787 */
788 ps->tx_errors++;
789 ps->tx_aborted_errors++;
790 }
791 } else {
792 ps->tx_errors++;
793 ps->tx_aborted_errors++;
794 if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
795 ps->tx_carrier_errors++;
796 }
797 }
798}
799
800/*
801 * Called from the interrupt service routine to acknowledge
802 * the TX DONE bits. This is a must if the irq is setup as
803 * edge triggered.
804 */
805static void au1000_tx_ack(struct net_device *dev)
806{
807 struct au1000_private *aup = netdev_priv(dev);
808 struct tx_dma *ptxd;
809
810 ptxd = aup->tx_dma_ring[aup->tx_tail];
811
812 while (ptxd->buff_stat & TX_T_DONE) {
813 au1000_update_tx_stats(dev, ptxd->status);
814 ptxd->buff_stat &= ~TX_T_DONE;
815 ptxd->len = 0;
816 au_sync();
817
818 aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
819 ptxd = aup->tx_dma_ring[aup->tx_tail];
820
821 if (aup->tx_full) {
822 aup->tx_full = 0;
823 netif_wake_queue(dev);
824 }
825 }
826}
827
828/*
829 * Au1000 interrupt service routine.
830 */
831static irqreturn_t au1000_interrupt(int irq, void *dev_id)
832{
833 struct net_device *dev = dev_id;
834
835 /* Handle RX interrupts first to minimize chance of overrun */
836
837 au1000_rx(dev);
838 au1000_tx_ack(dev);
839 return IRQ_RETVAL(1);
840}
841
842static int au1000_open(struct net_device *dev)
843{
844 int retval;
845 struct au1000_private *aup = netdev_priv(dev);
846
847 netif_dbg(aup, drv, dev, "open: dev=%p\n", dev);
848
849 retval = request_irq(dev->irq, au1000_interrupt, 0,
850 dev->name, dev);
851 if (retval) {
852 netdev_err(dev, "unable to get IRQ %d\n", dev->irq);
853 return retval;
854 }
855
856 retval = au1000_init(dev);
857 if (retval) {
858 netdev_err(dev, "error in au1000_init\n");
859 free_irq(dev->irq, dev);
860 return retval;
861 }
862
863 if (aup->phy_dev) {
864 /* cause the PHY state machine to schedule a link state check */
865 aup->phy_dev->state = PHY_CHANGELINK;
866 phy_start(aup->phy_dev);
867 }
868
869 netif_start_queue(dev);
870
871 netif_dbg(aup, drv, dev, "open: Initialization done.\n");
872
873 return 0;
874}
875
876static int au1000_close(struct net_device *dev)
877{
878 unsigned long flags;
879 struct au1000_private *const aup = netdev_priv(dev);
880
881 netif_dbg(aup, drv, dev, "close: dev=%p\n", dev);
882
883 if (aup->phy_dev)
884 phy_stop(aup->phy_dev);
885
886 spin_lock_irqsave(&aup->lock, flags);
887
888 au1000_reset_mac_unlocked(dev);
889
890 /* stop the device */
891 netif_stop_queue(dev);
892
893 /* disable the interrupt */
894 free_irq(dev->irq, dev);
895 spin_unlock_irqrestore(&aup->lock, flags);
896
897 return 0;
898}
899
900/*
901 * Au1000 transmit routine.
902 */
903static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev)
904{
905 struct au1000_private *aup = netdev_priv(dev);
906 struct net_device_stats *ps = &dev->stats;
907 struct tx_dma *ptxd;
908 u32 buff_stat;
909 struct db_dest *pDB;
910 int i;
911
912 netif_dbg(aup, tx_queued, dev, "tx: aup %x len=%d, data=%p, head %d\n",
913 (unsigned)aup, skb->len,
914 skb->data, aup->tx_head);
915
916 ptxd = aup->tx_dma_ring[aup->tx_head];
917 buff_stat = ptxd->buff_stat;
918 if (buff_stat & TX_DMA_ENABLE) {
919 /* We've wrapped around and the transmitter is still busy */
920 netif_stop_queue(dev);
921 aup->tx_full = 1;
922 return NETDEV_TX_BUSY;
923 } else if (buff_stat & TX_T_DONE) {
924 au1000_update_tx_stats(dev, ptxd->status);
925 ptxd->len = 0;
926 }
927
928 if (aup->tx_full) {
929 aup->tx_full = 0;
930 netif_wake_queue(dev);
931 }
932
933 pDB = aup->tx_db_inuse[aup->tx_head];
934 skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len);
935 if (skb->len < ETH_ZLEN) {
936 for (i = skb->len; i < ETH_ZLEN; i++)
937 ((char *)pDB->vaddr)[i] = 0;
938
939 ptxd->len = ETH_ZLEN;
940 } else
941 ptxd->len = skb->len;
942
943 ps->tx_packets++;
944 ps->tx_bytes += ptxd->len;
945
946 ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
947 au_sync();
948 dev_kfree_skb(skb);
949 aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
950 return NETDEV_TX_OK;
951}
952
953/*
954 * The Tx ring has been full longer than the watchdog timeout
955 * value. The transmitter must be hung?
956 */
957static void au1000_tx_timeout(struct net_device *dev)
958{
959 netdev_err(dev, "au1000_tx_timeout: dev=%p\n", dev);
960 au1000_reset_mac(dev);
961 au1000_init(dev);
962 dev->trans_start = jiffies; /* prevent tx timeout */
963 netif_wake_queue(dev);
964}
965
966static void au1000_multicast_list(struct net_device *dev)
967{
968 struct au1000_private *aup = netdev_priv(dev);
969 u32 reg;
970
971 netif_dbg(aup, drv, dev, "%s: flags=%x\n", __func__, dev->flags);
972 reg = readl(&aup->mac->control);
973 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
974 reg |= MAC_PROMISCUOUS;
975 } else if ((dev->flags & IFF_ALLMULTI) ||
976 netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) {
977 reg |= MAC_PASS_ALL_MULTI;
978 reg &= ~MAC_PROMISCUOUS;
979 netdev_info(dev, "Pass all multicast\n");
980 } else {
981 struct netdev_hw_addr *ha;
982 u32 mc_filter[2]; /* Multicast hash filter */
983
984 mc_filter[1] = mc_filter[0] = 0;
985 netdev_for_each_mc_addr(ha, dev)
986 set_bit(ether_crc(ETH_ALEN, ha->addr)>>26,
987 (long *)mc_filter);
988 writel(mc_filter[1], &aup->mac->multi_hash_high);
989 writel(mc_filter[0], &aup->mac->multi_hash_low);
990 reg &= ~MAC_PROMISCUOUS;
991 reg |= MAC_HASH_MODE;
992 }
993 writel(reg, &aup->mac->control);
994}
995
996static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
997{
998 struct au1000_private *aup = netdev_priv(dev);
999
1000 if (!netif_running(dev))
1001 return -EINVAL;
1002
1003 if (!aup->phy_dev)
1004 return -EINVAL; /* PHY not controllable */
1005
1006 return phy_mii_ioctl(aup->phy_dev, rq, cmd);
1007}
1008
1009static const struct net_device_ops au1000_netdev_ops = {
1010 .ndo_open = au1000_open,
1011 .ndo_stop = au1000_close,
1012 .ndo_start_xmit = au1000_tx,
1013 .ndo_set_multicast_list = au1000_multicast_list,
1014 .ndo_do_ioctl = au1000_ioctl,
1015 .ndo_tx_timeout = au1000_tx_timeout,
1016 .ndo_set_mac_address = eth_mac_addr,
1017 .ndo_validate_addr = eth_validate_addr,
1018 .ndo_change_mtu = eth_change_mtu,
1019};
1020
1021static int __devinit au1000_probe(struct platform_device *pdev)
1022{
1023 static unsigned version_printed;
1024 struct au1000_private *aup = NULL;
1025 struct au1000_eth_platform_data *pd;
1026 struct net_device *dev = NULL;
1027 struct db_dest *pDB, *pDBfree;
1028 int irq, i, err = 0;
1029 struct resource *base, *macen;
1030
1031 base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1032 if (!base) {
1033 dev_err(&pdev->dev, "failed to retrieve base register\n");
1034 err = -ENODEV;
1035 goto out;
1036 }
1037
1038 macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1039 if (!macen) {
1040 dev_err(&pdev->dev, "failed to retrieve MAC Enable register\n");
1041 err = -ENODEV;
1042 goto out;
1043 }
1044
1045 irq = platform_get_irq(pdev, 0);
1046 if (irq < 0) {
1047 dev_err(&pdev->dev, "failed to retrieve IRQ\n");
1048 err = -ENODEV;
1049 goto out;
1050 }
1051
1052 if (!request_mem_region(base->start, resource_size(base),
1053 pdev->name)) {
1054 dev_err(&pdev->dev, "failed to request memory region for base registers\n");
1055 err = -ENXIO;
1056 goto out;
1057 }
1058
1059 if (!request_mem_region(macen->start, resource_size(macen),
1060 pdev->name)) {
1061 dev_err(&pdev->dev, "failed to request memory region for MAC enable register\n");
1062 err = -ENXIO;
1063 goto err_request;
1064 }
1065
1066 dev = alloc_etherdev(sizeof(struct au1000_private));
1067 if (!dev) {
1068 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1069 err = -ENOMEM;
1070 goto err_alloc;
1071 }
1072
1073 SET_NETDEV_DEV(dev, &pdev->dev);
1074 platform_set_drvdata(pdev, dev);
1075 aup = netdev_priv(dev);
1076
1077 spin_lock_init(&aup->lock);
1078 aup->msg_enable = (au1000_debug < 4 ?
1079 AU1000_DEF_MSG_ENABLE : au1000_debug);
1080
1081 /* Allocate the data buffers
1082 * Snooping works fine with eth on all au1xxx
1083 */
1084 aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE *
1085 (NUM_TX_BUFFS + NUM_RX_BUFFS),
1086 &aup->dma_addr, 0);
1087 if (!aup->vaddr) {
1088 dev_err(&pdev->dev, "failed to allocate data buffers\n");
1089 err = -ENOMEM;
1090 goto err_vaddr;
1091 }
1092
1093 /* aup->mac is the base address of the MAC's registers */
1094 aup->mac = (struct mac_reg *)
1095 ioremap_nocache(base->start, resource_size(base));
1096 if (!aup->mac) {
1097 dev_err(&pdev->dev, "failed to ioremap MAC registers\n");
1098 err = -ENXIO;
1099 goto err_remap1;
1100 }
1101
1102 /* Setup some variables for quick register address access */
1103 aup->enable = (u32 *)ioremap_nocache(macen->start,
1104 resource_size(macen));
1105 if (!aup->enable) {
1106 dev_err(&pdev->dev, "failed to ioremap MAC enable register\n");
1107 err = -ENXIO;
1108 goto err_remap2;
1109 }
1110 aup->mac_id = pdev->id;
1111
1112 if (pdev->id == 0)
1113 au1000_setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR);
1114 else if (pdev->id == 1)
1115 au1000_setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR);
1116
1117 /* set a random MAC now in case platform_data doesn't provide one */
1118 random_ether_addr(dev->dev_addr);
1119
1120 writel(0, aup->enable);
1121 aup->mac_enabled = 0;
1122
1123 pd = pdev->dev.platform_data;
1124 if (!pd) {
1125 dev_info(&pdev->dev, "no platform_data passed,"
1126 " PHY search on MAC0\n");
1127 aup->phy1_search_mac0 = 1;
1128 } else {
1129 if (is_valid_ether_addr(pd->mac))
1130 memcpy(dev->dev_addr, pd->mac, 6);
1131
1132 aup->phy_static_config = pd->phy_static_config;
1133 aup->phy_search_highest_addr = pd->phy_search_highest_addr;
1134 aup->phy1_search_mac0 = pd->phy1_search_mac0;
1135 aup->phy_addr = pd->phy_addr;
1136 aup->phy_busid = pd->phy_busid;
1137 aup->phy_irq = pd->phy_irq;
1138 }
1139
1140 if (aup->phy_busid && aup->phy_busid > 0) {
1141 dev_err(&pdev->dev, "MAC0-associated PHY attached 2nd MACs MII bus not supported yet\n");
1142 err = -ENODEV;
1143 goto err_mdiobus_alloc;
1144 }
1145
1146 aup->mii_bus = mdiobus_alloc();
1147 if (aup->mii_bus == NULL) {
1148 dev_err(&pdev->dev, "failed to allocate mdiobus structure\n");
1149 err = -ENOMEM;
1150 goto err_mdiobus_alloc;
1151 }
1152
1153 aup->mii_bus->priv = dev;
1154 aup->mii_bus->read = au1000_mdiobus_read;
1155 aup->mii_bus->write = au1000_mdiobus_write;
1156 aup->mii_bus->reset = au1000_mdiobus_reset;
1157 aup->mii_bus->name = "au1000_eth_mii";
1158 snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%x", aup->mac_id);
1159 aup->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1160 if (aup->mii_bus->irq == NULL)
1161 goto err_out;
1162
1163 for (i = 0; i < PHY_MAX_ADDR; ++i)
1164 aup->mii_bus->irq[i] = PHY_POLL;
1165 /* if known, set corresponding PHY IRQs */
1166 if (aup->phy_static_config)
1167 if (aup->phy_irq && aup->phy_busid == aup->mac_id)
1168 aup->mii_bus->irq[aup->phy_addr] = aup->phy_irq;
1169
1170 err = mdiobus_register(aup->mii_bus);
1171 if (err) {
1172 dev_err(&pdev->dev, "failed to register MDIO bus\n");
1173 goto err_mdiobus_reg;
1174 }
1175
1176 if (au1000_mii_probe(dev) != 0)
1177 goto err_out;
1178
1179 pDBfree = NULL;
1180 /* setup the data buffer descriptors and attach a buffer to each one */
1181 pDB = aup->db;
1182 for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
1183 pDB->pnext = pDBfree;
1184 pDBfree = pDB;
1185 pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i);
1186 pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
1187 pDB++;
1188 }
1189 aup->pDBfree = pDBfree;
1190
1191 for (i = 0; i < NUM_RX_DMA; i++) {
1192 pDB = au1000_GetFreeDB(aup);
1193 if (!pDB)
1194 goto err_out;
1195
1196 aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
1197 aup->rx_db_inuse[i] = pDB;
1198 }
1199 for (i = 0; i < NUM_TX_DMA; i++) {
1200 pDB = au1000_GetFreeDB(aup);
1201 if (!pDB)
1202 goto err_out;
1203
1204 aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
1205 aup->tx_dma_ring[i]->len = 0;
1206 aup->tx_db_inuse[i] = pDB;
1207 }
1208
1209 dev->base_addr = base->start;
1210 dev->irq = irq;
1211 dev->netdev_ops = &au1000_netdev_ops;
1212 SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops);
1213 dev->watchdog_timeo = ETH_TX_TIMEOUT;
1214
1215 /*
1216 * The boot code uses the ethernet controller, so reset it to start
1217 * fresh. au1000_init() expects that the device is in reset state.
1218 */
1219 au1000_reset_mac(dev);
1220
1221 err = register_netdev(dev);
1222 if (err) {
1223 netdev_err(dev, "Cannot register net device, aborting.\n");
1224 goto err_out;
1225 }
1226
1227 netdev_info(dev, "Au1xx0 Ethernet found at 0x%lx, irq %d\n",
1228 (unsigned long)base->start, irq);
1229 if (version_printed++ == 0)
1230 pr_info("%s version %s %s\n",
1231 DRV_NAME, DRV_VERSION, DRV_AUTHOR);
1232
1233 return 0;
1234
1235err_out:
1236 if (aup->mii_bus != NULL)
1237 mdiobus_unregister(aup->mii_bus);
1238
1239 /* here we should have a valid dev plus aup-> register addresses
1240 * so we can reset the mac properly.
1241 */
1242 au1000_reset_mac(dev);
1243
1244 for (i = 0; i < NUM_RX_DMA; i++) {
1245 if (aup->rx_db_inuse[i])
1246 au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
1247 }
1248 for (i = 0; i < NUM_TX_DMA; i++) {
1249 if (aup->tx_db_inuse[i])
1250 au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
1251 }
1252err_mdiobus_reg:
1253 mdiobus_free(aup->mii_bus);
1254err_mdiobus_alloc:
1255 iounmap(aup->enable);
1256err_remap2:
1257 iounmap(aup->mac);
1258err_remap1:
1259 dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
1260 (void *)aup->vaddr, aup->dma_addr);
1261err_vaddr:
1262 free_netdev(dev);
1263err_alloc:
1264 release_mem_region(macen->start, resource_size(macen));
1265err_request:
1266 release_mem_region(base->start, resource_size(base));
1267out:
1268 return err;
1269}
1270
1271static int __devexit au1000_remove(struct platform_device *pdev)
1272{
1273 struct net_device *dev = platform_get_drvdata(pdev);
1274 struct au1000_private *aup = netdev_priv(dev);
1275 int i;
1276 struct resource *base, *macen;
1277
1278 platform_set_drvdata(pdev, NULL);
1279
1280 unregister_netdev(dev);
1281 mdiobus_unregister(aup->mii_bus);
1282 mdiobus_free(aup->mii_bus);
1283
1284 for (i = 0; i < NUM_RX_DMA; i++)
1285 if (aup->rx_db_inuse[i])
1286 au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
1287
1288 for (i = 0; i < NUM_TX_DMA; i++)
1289 if (aup->tx_db_inuse[i])
1290 au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
1291
1292 dma_free_noncoherent(NULL, MAX_BUF_SIZE *
1293 (NUM_TX_BUFFS + NUM_RX_BUFFS),
1294 (void *)aup->vaddr, aup->dma_addr);
1295
1296 iounmap(aup->mac);
1297 iounmap(aup->enable);
1298
1299 base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1300 release_mem_region(base->start, resource_size(base));
1301
1302 macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1303 release_mem_region(macen->start, resource_size(macen));
1304
1305 free_netdev(dev);
1306
1307 return 0;
1308}
1309
1310static struct platform_driver au1000_eth_driver = {
1311 .probe = au1000_probe,
1312 .remove = __devexit_p(au1000_remove),
1313 .driver = {
1314 .name = "au1000-eth",
1315 .owner = THIS_MODULE,
1316 },
1317};
1318MODULE_ALIAS("platform:au1000-eth");
1319
1320
1321static int __init au1000_init_module(void)
1322{
1323 return platform_driver_register(&au1000_eth_driver);
1324}
1325
1326static void __exit au1000_exit_module(void)
1327{
1328 platform_driver_unregister(&au1000_eth_driver);
1329}
1330
1331module_init(au1000_init_module);
1332module_exit(au1000_exit_module);