1/*
  2 * Copyright 2017 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#ifndef DM_PP_SMU_IF__H
 27#define DM_PP_SMU_IF__H
 28
 29/*
 30 * interface to PPLIB/SMU to setup clocks and pstate requirements on SoC
 31 */
 32
 33
 34struct pp_smu {
 35	struct dc_context *ctx;
 36};
 37
 38enum wm_set_id {
 39	WM_A,
 40	WM_B,
 41	WM_C,
 42	WM_D,
 43	WM_COUNT,
 44};
 45
 46struct pp_smu_wm_set_range {
 47	enum wm_set_id wm_inst;
 48	uint32_t min_fill_clk_khz;
 49	uint32_t max_fill_clk_khz;
 50	uint32_t min_drain_clk_khz;
 51	uint32_t max_drain_clk_khz;
 52};
 53
 54struct pp_smu_wm_range_sets {
 55	uint32_t num_reader_wm_sets;
 56	struct pp_smu_wm_set_range reader_wm_sets[WM_COUNT];
 57
 58	uint32_t num_writer_wm_sets;
 59	struct pp_smu_wm_set_range writer_wm_sets[WM_COUNT];
 60};
 61
 62struct pp_smu_display_requirement_rv {
 63	/* PPSMC_MSG_SetDisplayCount: count
 64	 *  0 triggers S0i2 optimization
 65	 */
 66	unsigned int display_count;
 67
 68	/* PPSMC_MSG_SetHardMinFclkByFreq: khz
 69	 *  FCLK will vary with DPM, but never below requested hard min
 70	 */
 71	unsigned int hard_min_fclk_khz;
 72
 73	/* PPSMC_MSG_SetHardMinDcefclkByFreq: khz
 74	 *  fixed clock at requested freq, either from FCH bypass or DFS
 75	 */
 76	unsigned int hard_min_dcefclk_khz;
 77
 78	/* PPSMC_MSG_SetMinDeepSleepDcefclk: mhz
 79	 *  when DF is in cstate, dcf clock is further divided down
 80	 *  to just above given frequency
 81	 */
 82	unsigned int min_deep_sleep_dcefclk_mhz;
 83};
 84
 85struct pp_smu_funcs_rv {
 86	struct pp_smu pp_smu;
 87
 88	void (*set_display_requirement)(struct pp_smu *pp,
 89			struct pp_smu_display_requirement_rv *req);
 90
 91	/* which SMU message?  are reader and writer WM separate SMU msg? */
 92	void (*set_wm_ranges)(struct pp_smu *pp,
 93			struct pp_smu_wm_range_sets *ranges);
 94	/* PME w/a */
 95	void (*set_pme_wa_enable)(struct pp_smu *pp);
 96};
 97
 98#if 0
 99struct pp_smu_funcs_rv {
100
101	/* PPSMC_MSG_SetDisplayCount
102	 *  0 triggers S0i2 optimization
103	 */
104	void (*set_display_count)(struct pp_smu *pp, int count);
105
106	/* PPSMC_MSG_SetHardMinFclkByFreq
107	 *  FCLK will vary with DPM, but never below requested hard min
108	 */
109	void (*set_hard_min_fclk_by_freq)(struct pp_smu *pp, int khz);
110
111	/* PPSMC_MSG_SetHardMinDcefclkByFreq
112	 *  fixed clock at requested freq, either from FCH bypass or DFS
113	 */
114	void (*set_hard_min_dcefclk_by_freq)(struct pp_smu *pp, int khz);
115
116	/* PPSMC_MSG_SetMinDeepSleepDcefclk
117	 *  when DF is in cstate, dcf clock is further divided down
118	 *  to just above given frequency
119	 */
120	void (*set_min_deep_sleep_dcefclk)(struct pp_smu *pp, int mhz);
121
122	/* todo: aesthetic
123	 * watermark range table
124	 */
125
126	/* todo: functional/feature
127	 * PPSMC_MSG_SetHardMinSocclkByFreq: required to support DWB
128	 */
129};
130#endif
131
132#endif /* DM_PP_SMU_IF__H */