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1 /*
2 * x86 SMP booting functions
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
7 *
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
10 *
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
14 *
15 * This code is released under the GNU General Public License version 2 or
16 * later.
17 *
18 * Fixes
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
29 * from Jose Renau
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
40 */
41
42#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
43
44#include <linux/init.h>
45#include <linux/smp.h>
46#include <linux/export.h>
47#include <linux/sched.h>
48#include <linux/sched/topology.h>
49#include <linux/sched/hotplug.h>
50#include <linux/sched/task_stack.h>
51#include <linux/percpu.h>
52#include <linux/bootmem.h>
53#include <linux/err.h>
54#include <linux/nmi.h>
55#include <linux/tboot.h>
56#include <linux/stackprotector.h>
57#include <linux/gfp.h>
58#include <linux/cpuidle.h>
59
60#include <asm/acpi.h>
61#include <asm/desc.h>
62#include <asm/nmi.h>
63#include <asm/irq.h>
64#include <asm/realmode.h>
65#include <asm/cpu.h>
66#include <asm/numa.h>
67#include <asm/pgtable.h>
68#include <asm/tlbflush.h>
69#include <asm/mtrr.h>
70#include <asm/mwait.h>
71#include <asm/apic.h>
72#include <asm/io_apic.h>
73#include <asm/fpu/internal.h>
74#include <asm/setup.h>
75#include <asm/uv/uv.h>
76#include <linux/mc146818rtc.h>
77#include <asm/i8259.h>
78#include <asm/misc.h>
79#include <asm/qspinlock.h>
80#include <asm/intel-family.h>
81#include <asm/cpu_device_id.h>
82#include <asm/spec-ctrl.h>
83
84/* Number of siblings per CPU package */
85int smp_num_siblings = 1;
86EXPORT_SYMBOL(smp_num_siblings);
87
88/* Last level cache ID of each logical CPU */
89DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
90
91/* representing HT siblings of each logical CPU */
92DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
93EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
94
95/* representing HT and core siblings of each logical CPU */
96DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
97EXPORT_PER_CPU_SYMBOL(cpu_core_map);
98
99DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
100
101/* Per CPU bogomips and other parameters */
102DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
103EXPORT_PER_CPU_SYMBOL(cpu_info);
104
105/* Logical package management. We might want to allocate that dynamically */
106unsigned int __max_logical_packages __read_mostly;
107EXPORT_SYMBOL(__max_logical_packages);
108static unsigned int logical_packages __read_mostly;
109
110/* Maximum number of SMT threads on any online core */
111int __read_mostly __max_smt_threads = 1;
112
113/* Flag to indicate if a complete sched domain rebuild is required */
114bool x86_topology_update;
115
116int arch_update_cpu_topology(void)
117{
118 int retval = x86_topology_update;
119
120 x86_topology_update = false;
121 return retval;
122}
123
124static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
125{
126 unsigned long flags;
127
128 spin_lock_irqsave(&rtc_lock, flags);
129 CMOS_WRITE(0xa, 0xf);
130 spin_unlock_irqrestore(&rtc_lock, flags);
131 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
132 start_eip >> 4;
133 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
134 start_eip & 0xf;
135}
136
137static inline void smpboot_restore_warm_reset_vector(void)
138{
139 unsigned long flags;
140
141 /*
142 * Paranoid: Set warm reset code and vector here back
143 * to default values.
144 */
145 spin_lock_irqsave(&rtc_lock, flags);
146 CMOS_WRITE(0, 0xf);
147 spin_unlock_irqrestore(&rtc_lock, flags);
148
149 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
150}
151
152/*
153 * Report back to the Boot Processor during boot time or to the caller processor
154 * during CPU online.
155 */
156static void smp_callin(void)
157{
158 int cpuid, phys_id;
159
160 /*
161 * If waken up by an INIT in an 82489DX configuration
162 * cpu_callout_mask guarantees we don't get here before
163 * an INIT_deassert IPI reaches our local APIC, so it is
164 * now safe to touch our local APIC.
165 */
166 cpuid = smp_processor_id();
167
168 /*
169 * (This works even if the APIC is not enabled.)
170 */
171 phys_id = read_apic_id();
172
173 /*
174 * the boot CPU has finished the init stage and is spinning
175 * on callin_map until we finish. We are free to set up this
176 * CPU, first the APIC. (this is probably redundant on most
177 * boards)
178 */
179 apic_ap_setup();
180
181 /*
182 * Save our processor parameters. Note: this information
183 * is needed for clock calibration.
184 */
185 smp_store_cpu_info(cpuid);
186
187 /*
188 * The topology information must be up to date before
189 * calibrate_delay() and notify_cpu_starting().
190 */
191 set_cpu_sibling_map(raw_smp_processor_id());
192
193 /*
194 * Get our bogomips.
195 * Update loops_per_jiffy in cpu_data. Previous call to
196 * smp_store_cpu_info() stored a value that is close but not as
197 * accurate as the value just calculated.
198 */
199 calibrate_delay();
200 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
201 pr_debug("Stack at about %p\n", &cpuid);
202
203 wmb();
204
205 notify_cpu_starting(cpuid);
206
207 /*
208 * Allow the master to continue.
209 */
210 cpumask_set_cpu(cpuid, cpu_callin_mask);
211}
212
213static int cpu0_logical_apicid;
214static int enable_start_cpu0;
215/*
216 * Activate a secondary processor.
217 */
218static void notrace start_secondary(void *unused)
219{
220 /*
221 * Don't put *anything* except direct CPU state initialization
222 * before cpu_init(), SMP booting is too fragile that we want to
223 * limit the things done here to the most necessary things.
224 */
225 if (boot_cpu_has(X86_FEATURE_PCID))
226 __write_cr4(__read_cr4() | X86_CR4_PCIDE);
227
228#ifdef CONFIG_X86_32
229 /* switch away from the initial page table */
230 load_cr3(swapper_pg_dir);
231 __flush_tlb_all();
232#endif
233 load_current_idt();
234 cpu_init();
235 x86_cpuinit.early_percpu_clock_init();
236 preempt_disable();
237 smp_callin();
238
239 enable_start_cpu0 = 0;
240
241 /* otherwise gcc will move up smp_processor_id before the cpu_init */
242 barrier();
243 /*
244 * Check TSC synchronization with the boot CPU:
245 */
246 check_tsc_sync_target();
247
248 speculative_store_bypass_ht_init();
249
250 /*
251 * Lock vector_lock, set CPU online and bring the vector
252 * allocator online. Online must be set with vector_lock held
253 * to prevent a concurrent irq setup/teardown from seeing a
254 * half valid vector space.
255 */
256 lock_vector_lock();
257 set_cpu_online(smp_processor_id(), true);
258 lapic_online();
259 unlock_vector_lock();
260 cpu_set_state_online(smp_processor_id());
261 x86_platform.nmi_init();
262
263 /* enable local interrupts */
264 local_irq_enable();
265
266 /* to prevent fake stack check failure in clock setup */
267 boot_init_stack_canary();
268
269 x86_cpuinit.setup_percpu_clockev();
270
271 wmb();
272 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
273}
274
275/**
276 * topology_phys_to_logical_pkg - Map a physical package id to a logical
277 *
278 * Returns logical package id or -1 if not found
279 */
280int topology_phys_to_logical_pkg(unsigned int phys_pkg)
281{
282 int cpu;
283
284 for_each_possible_cpu(cpu) {
285 struct cpuinfo_x86 *c = &cpu_data(cpu);
286
287 if (c->initialized && c->phys_proc_id == phys_pkg)
288 return c->logical_proc_id;
289 }
290 return -1;
291}
292EXPORT_SYMBOL(topology_phys_to_logical_pkg);
293
294/**
295 * topology_update_package_map - Update the physical to logical package map
296 * @pkg: The physical package id as retrieved via CPUID
297 * @cpu: The cpu for which this is updated
298 */
299int topology_update_package_map(unsigned int pkg, unsigned int cpu)
300{
301 int new;
302
303 /* Already available somewhere? */
304 new = topology_phys_to_logical_pkg(pkg);
305 if (new >= 0)
306 goto found;
307
308 new = logical_packages++;
309 if (new != pkg) {
310 pr_info("CPU %u Converting physical %u to logical package %u\n",
311 cpu, pkg, new);
312 }
313found:
314 cpu_data(cpu).logical_proc_id = new;
315 return 0;
316}
317
318void __init smp_store_boot_cpu_info(void)
319{
320 int id = 0; /* CPU 0 */
321 struct cpuinfo_x86 *c = &cpu_data(id);
322
323 *c = boot_cpu_data;
324 c->cpu_index = id;
325 topology_update_package_map(c->phys_proc_id, id);
326 c->initialized = true;
327}
328
329/*
330 * The bootstrap kernel entry code has set these up. Save them for
331 * a given CPU
332 */
333void smp_store_cpu_info(int id)
334{
335 struct cpuinfo_x86 *c = &cpu_data(id);
336
337 /* Copy boot_cpu_data only on the first bringup */
338 if (!c->initialized)
339 *c = boot_cpu_data;
340 c->cpu_index = id;
341 /*
342 * During boot time, CPU0 has this setup already. Save the info when
343 * bringing up AP or offlined CPU0.
344 */
345 identify_secondary_cpu(c);
346 c->initialized = true;
347}
348
349static bool
350topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
351{
352 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
353
354 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
355}
356
357static bool
358topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
359{
360 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
361
362 return !WARN_ONCE(!topology_same_node(c, o),
363 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
364 "[node: %d != %d]. Ignoring dependency.\n",
365 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
366}
367
368#define link_mask(mfunc, c1, c2) \
369do { \
370 cpumask_set_cpu((c1), mfunc(c2)); \
371 cpumask_set_cpu((c2), mfunc(c1)); \
372} while (0)
373
374static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
375{
376 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
377 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
378
379 if (c->phys_proc_id == o->phys_proc_id &&
380 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
381 if (c->cpu_core_id == o->cpu_core_id)
382 return topology_sane(c, o, "smt");
383
384 if ((c->cu_id != 0xff) &&
385 (o->cu_id != 0xff) &&
386 (c->cu_id == o->cu_id))
387 return topology_sane(c, o, "smt");
388 }
389
390 } else if (c->phys_proc_id == o->phys_proc_id &&
391 c->cpu_core_id == o->cpu_core_id) {
392 return topology_sane(c, o, "smt");
393 }
394
395 return false;
396}
397
398/*
399 * Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs.
400 *
401 * These are Intel CPUs that enumerate an LLC that is shared by
402 * multiple NUMA nodes. The LLC on these systems is shared for
403 * off-package data access but private to the NUMA node (half
404 * of the package) for on-package access.
405 *
406 * CPUID (the source of the information about the LLC) can only
407 * enumerate the cache as being shared *or* unshared, but not
408 * this particular configuration. The CPU in this case enumerates
409 * the cache to be shared across the entire package (spanning both
410 * NUMA nodes).
411 */
412
413static const struct x86_cpu_id snc_cpu[] = {
414 { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_X },
415 {}
416};
417
418static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
419{
420 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
421
422 /* Do not match if we do not have a valid APICID for cpu: */
423 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID)
424 return false;
425
426 /* Do not match if LLC id does not match: */
427 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2))
428 return false;
429
430 /*
431 * Allow the SNC topology without warning. Return of false
432 * means 'c' does not share the LLC of 'o'. This will be
433 * reflected to userspace.
434 */
435 if (!topology_same_node(c, o) && x86_match_cpu(snc_cpu))
436 return false;
437
438 return topology_sane(c, o, "llc");
439}
440
441/*
442 * Unlike the other levels, we do not enforce keeping a
443 * multicore group inside a NUMA node. If this happens, we will
444 * discard the MC level of the topology later.
445 */
446static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
447{
448 if (c->phys_proc_id == o->phys_proc_id)
449 return true;
450 return false;
451}
452
453#if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
454static inline int x86_sched_itmt_flags(void)
455{
456 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
457}
458
459#ifdef CONFIG_SCHED_MC
460static int x86_core_flags(void)
461{
462 return cpu_core_flags() | x86_sched_itmt_flags();
463}
464#endif
465#ifdef CONFIG_SCHED_SMT
466static int x86_smt_flags(void)
467{
468 return cpu_smt_flags() | x86_sched_itmt_flags();
469}
470#endif
471#endif
472
473static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
474#ifdef CONFIG_SCHED_SMT
475 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
476#endif
477#ifdef CONFIG_SCHED_MC
478 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
479#endif
480 { NULL, },
481};
482
483static struct sched_domain_topology_level x86_topology[] = {
484#ifdef CONFIG_SCHED_SMT
485 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
486#endif
487#ifdef CONFIG_SCHED_MC
488 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
489#endif
490 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
491 { NULL, },
492};
493
494/*
495 * Set if a package/die has multiple NUMA nodes inside.
496 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
497 * Sub-NUMA Clustering have this.
498 */
499static bool x86_has_numa_in_package;
500
501void set_cpu_sibling_map(int cpu)
502{
503 bool has_smt = smp_num_siblings > 1;
504 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
505 struct cpuinfo_x86 *c = &cpu_data(cpu);
506 struct cpuinfo_x86 *o;
507 int i, threads;
508
509 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
510
511 if (!has_mp) {
512 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
513 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
514 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
515 c->booted_cores = 1;
516 return;
517 }
518
519 for_each_cpu(i, cpu_sibling_setup_mask) {
520 o = &cpu_data(i);
521
522 if ((i == cpu) || (has_smt && match_smt(c, o)))
523 link_mask(topology_sibling_cpumask, cpu, i);
524
525 if ((i == cpu) || (has_mp && match_llc(c, o)))
526 link_mask(cpu_llc_shared_mask, cpu, i);
527
528 }
529
530 /*
531 * This needs a separate iteration over the cpus because we rely on all
532 * topology_sibling_cpumask links to be set-up.
533 */
534 for_each_cpu(i, cpu_sibling_setup_mask) {
535 o = &cpu_data(i);
536
537 if ((i == cpu) || (has_mp && match_die(c, o))) {
538 link_mask(topology_core_cpumask, cpu, i);
539
540 /*
541 * Does this new cpu bringup a new core?
542 */
543 if (cpumask_weight(
544 topology_sibling_cpumask(cpu)) == 1) {
545 /*
546 * for each core in package, increment
547 * the booted_cores for this new cpu
548 */
549 if (cpumask_first(
550 topology_sibling_cpumask(i)) == i)
551 c->booted_cores++;
552 /*
553 * increment the core count for all
554 * the other cpus in this package
555 */
556 if (i != cpu)
557 cpu_data(i).booted_cores++;
558 } else if (i != cpu && !c->booted_cores)
559 c->booted_cores = cpu_data(i).booted_cores;
560 }
561 if (match_die(c, o) && !topology_same_node(c, o))
562 x86_has_numa_in_package = true;
563 }
564
565 threads = cpumask_weight(topology_sibling_cpumask(cpu));
566 if (threads > __max_smt_threads)
567 __max_smt_threads = threads;
568}
569
570/* maps the cpu to the sched domain representing multi-core */
571const struct cpumask *cpu_coregroup_mask(int cpu)
572{
573 return cpu_llc_shared_mask(cpu);
574}
575
576static void impress_friends(void)
577{
578 int cpu;
579 unsigned long bogosum = 0;
580 /*
581 * Allow the user to impress friends.
582 */
583 pr_debug("Before bogomips\n");
584 for_each_possible_cpu(cpu)
585 if (cpumask_test_cpu(cpu, cpu_callout_mask))
586 bogosum += cpu_data(cpu).loops_per_jiffy;
587 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
588 num_online_cpus(),
589 bogosum/(500000/HZ),
590 (bogosum/(5000/HZ))%100);
591
592 pr_debug("Before bogocount - setting activated=1\n");
593}
594
595void __inquire_remote_apic(int apicid)
596{
597 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
598 const char * const names[] = { "ID", "VERSION", "SPIV" };
599 int timeout;
600 u32 status;
601
602 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
603
604 for (i = 0; i < ARRAY_SIZE(regs); i++) {
605 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
606
607 /*
608 * Wait for idle.
609 */
610 status = safe_apic_wait_icr_idle();
611 if (status)
612 pr_cont("a previous APIC delivery may have failed\n");
613
614 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
615
616 timeout = 0;
617 do {
618 udelay(100);
619 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
620 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
621
622 switch (status) {
623 case APIC_ICR_RR_VALID:
624 status = apic_read(APIC_RRR);
625 pr_cont("%08x\n", status);
626 break;
627 default:
628 pr_cont("failed\n");
629 }
630 }
631}
632
633/*
634 * The Multiprocessor Specification 1.4 (1997) example code suggests
635 * that there should be a 10ms delay between the BSP asserting INIT
636 * and de-asserting INIT, when starting a remote processor.
637 * But that slows boot and resume on modern processors, which include
638 * many cores and don't require that delay.
639 *
640 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
641 * Modern processor families are quirked to remove the delay entirely.
642 */
643#define UDELAY_10MS_DEFAULT 10000
644
645static unsigned int init_udelay = UINT_MAX;
646
647static int __init cpu_init_udelay(char *str)
648{
649 get_option(&str, &init_udelay);
650
651 return 0;
652}
653early_param("cpu_init_udelay", cpu_init_udelay);
654
655static void __init smp_quirk_init_udelay(void)
656{
657 /* if cmdline changed it from default, leave it alone */
658 if (init_udelay != UINT_MAX)
659 return;
660
661 /* if modern processor, use no delay */
662 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
663 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
664 init_udelay = 0;
665 return;
666 }
667 /* else, use legacy delay */
668 init_udelay = UDELAY_10MS_DEFAULT;
669}
670
671/*
672 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
673 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
674 * won't ... remember to clear down the APIC, etc later.
675 */
676int
677wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
678{
679 unsigned long send_status, accept_status = 0;
680 int maxlvt;
681
682 /* Target chip */
683 /* Boot on the stack */
684 /* Kick the second */
685 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
686
687 pr_debug("Waiting for send to finish...\n");
688 send_status = safe_apic_wait_icr_idle();
689
690 /*
691 * Give the other CPU some time to accept the IPI.
692 */
693 udelay(200);
694 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
695 maxlvt = lapic_get_maxlvt();
696 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
697 apic_write(APIC_ESR, 0);
698 accept_status = (apic_read(APIC_ESR) & 0xEF);
699 }
700 pr_debug("NMI sent\n");
701
702 if (send_status)
703 pr_err("APIC never delivered???\n");
704 if (accept_status)
705 pr_err("APIC delivery error (%lx)\n", accept_status);
706
707 return (send_status | accept_status);
708}
709
710static int
711wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
712{
713 unsigned long send_status = 0, accept_status = 0;
714 int maxlvt, num_starts, j;
715
716 maxlvt = lapic_get_maxlvt();
717
718 /*
719 * Be paranoid about clearing APIC errors.
720 */
721 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
722 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
723 apic_write(APIC_ESR, 0);
724 apic_read(APIC_ESR);
725 }
726
727 pr_debug("Asserting INIT\n");
728
729 /*
730 * Turn INIT on target chip
731 */
732 /*
733 * Send IPI
734 */
735 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
736 phys_apicid);
737
738 pr_debug("Waiting for send to finish...\n");
739 send_status = safe_apic_wait_icr_idle();
740
741 udelay(init_udelay);
742
743 pr_debug("Deasserting INIT\n");
744
745 /* Target chip */
746 /* Send IPI */
747 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
748
749 pr_debug("Waiting for send to finish...\n");
750 send_status = safe_apic_wait_icr_idle();
751
752 mb();
753
754 /*
755 * Should we send STARTUP IPIs ?
756 *
757 * Determine this based on the APIC version.
758 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
759 */
760 if (APIC_INTEGRATED(boot_cpu_apic_version))
761 num_starts = 2;
762 else
763 num_starts = 0;
764
765 /*
766 * Run STARTUP IPI loop.
767 */
768 pr_debug("#startup loops: %d\n", num_starts);
769
770 for (j = 1; j <= num_starts; j++) {
771 pr_debug("Sending STARTUP #%d\n", j);
772 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
773 apic_write(APIC_ESR, 0);
774 apic_read(APIC_ESR);
775 pr_debug("After apic_write\n");
776
777 /*
778 * STARTUP IPI
779 */
780
781 /* Target chip */
782 /* Boot on the stack */
783 /* Kick the second */
784 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
785 phys_apicid);
786
787 /*
788 * Give the other CPU some time to accept the IPI.
789 */
790 if (init_udelay == 0)
791 udelay(10);
792 else
793 udelay(300);
794
795 pr_debug("Startup point 1\n");
796
797 pr_debug("Waiting for send to finish...\n");
798 send_status = safe_apic_wait_icr_idle();
799
800 /*
801 * Give the other CPU some time to accept the IPI.
802 */
803 if (init_udelay == 0)
804 udelay(10);
805 else
806 udelay(200);
807
808 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
809 apic_write(APIC_ESR, 0);
810 accept_status = (apic_read(APIC_ESR) & 0xEF);
811 if (send_status || accept_status)
812 break;
813 }
814 pr_debug("After Startup\n");
815
816 if (send_status)
817 pr_err("APIC never delivered???\n");
818 if (accept_status)
819 pr_err("APIC delivery error (%lx)\n", accept_status);
820
821 return (send_status | accept_status);
822}
823
824/* reduce the number of lines printed when booting a large cpu count system */
825static void announce_cpu(int cpu, int apicid)
826{
827 static int current_node = -1;
828 int node = early_cpu_to_node(cpu);
829 static int width, node_width;
830
831 if (!width)
832 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
833
834 if (!node_width)
835 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
836
837 if (cpu == 1)
838 printk(KERN_INFO "x86: Booting SMP configuration:\n");
839
840 if (system_state < SYSTEM_RUNNING) {
841 if (node != current_node) {
842 if (current_node > (-1))
843 pr_cont("\n");
844 current_node = node;
845
846 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
847 node_width - num_digits(node), " ", node);
848 }
849
850 /* Add padding for the BSP */
851 if (cpu == 1)
852 pr_cont("%*s", width + 1, " ");
853
854 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
855
856 } else
857 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
858 node, cpu, apicid);
859}
860
861static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
862{
863 int cpu;
864
865 cpu = smp_processor_id();
866 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
867 return NMI_HANDLED;
868
869 return NMI_DONE;
870}
871
872/*
873 * Wake up AP by INIT, INIT, STARTUP sequence.
874 *
875 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
876 * boot-strap code which is not a desired behavior for waking up BSP. To
877 * void the boot-strap code, wake up CPU0 by NMI instead.
878 *
879 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
880 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
881 * We'll change this code in the future to wake up hard offlined CPU0 if
882 * real platform and request are available.
883 */
884static int
885wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
886 int *cpu0_nmi_registered)
887{
888 int id;
889 int boot_error;
890
891 preempt_disable();
892
893 /*
894 * Wake up AP by INIT, INIT, STARTUP sequence.
895 */
896 if (cpu) {
897 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
898 goto out;
899 }
900
901 /*
902 * Wake up BSP by nmi.
903 *
904 * Register a NMI handler to help wake up CPU0.
905 */
906 boot_error = register_nmi_handler(NMI_LOCAL,
907 wakeup_cpu0_nmi, 0, "wake_cpu0");
908
909 if (!boot_error) {
910 enable_start_cpu0 = 1;
911 *cpu0_nmi_registered = 1;
912 if (apic->dest_logical == APIC_DEST_LOGICAL)
913 id = cpu0_logical_apicid;
914 else
915 id = apicid;
916 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
917 }
918
919out:
920 preempt_enable();
921
922 return boot_error;
923}
924
925void common_cpu_up(unsigned int cpu, struct task_struct *idle)
926{
927 /* Just in case we booted with a single CPU. */
928 alternatives_enable_smp();
929
930 per_cpu(current_task, cpu) = idle;
931
932#ifdef CONFIG_X86_32
933 /* Stack for startup_32 can be just as for start_secondary onwards */
934 irq_ctx_init(cpu);
935 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle);
936#else
937 initial_gs = per_cpu_offset(cpu);
938#endif
939}
940
941/*
942 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
943 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
944 * Returns zero if CPU booted OK, else error code from
945 * ->wakeup_secondary_cpu.
946 */
947static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
948 int *cpu0_nmi_registered)
949{
950 volatile u32 *trampoline_status =
951 (volatile u32 *) __va(real_mode_header->trampoline_status);
952 /* start_ip had better be page-aligned! */
953 unsigned long start_ip = real_mode_header->trampoline_start;
954
955 unsigned long boot_error = 0;
956 unsigned long timeout;
957
958 idle->thread.sp = (unsigned long)task_pt_regs(idle);
959 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
960 initial_code = (unsigned long)start_secondary;
961 initial_stack = idle->thread.sp;
962
963 /* Enable the espfix hack for this CPU */
964 init_espfix_ap(cpu);
965
966 /* So we see what's up */
967 announce_cpu(cpu, apicid);
968
969 /*
970 * This grunge runs the startup process for
971 * the targeted processor.
972 */
973
974 if (x86_platform.legacy.warm_reset) {
975
976 pr_debug("Setting warm reset code and vector.\n");
977
978 smpboot_setup_warm_reset_vector(start_ip);
979 /*
980 * Be paranoid about clearing APIC errors.
981 */
982 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
983 apic_write(APIC_ESR, 0);
984 apic_read(APIC_ESR);
985 }
986 }
987
988 /*
989 * AP might wait on cpu_callout_mask in cpu_init() with
990 * cpu_initialized_mask set if previous attempt to online
991 * it timed-out. Clear cpu_initialized_mask so that after
992 * INIT/SIPI it could start with a clean state.
993 */
994 cpumask_clear_cpu(cpu, cpu_initialized_mask);
995 smp_mb();
996
997 /*
998 * Wake up a CPU in difference cases:
999 * - Use the method in the APIC driver if it's defined
1000 * Otherwise,
1001 * - Use an INIT boot APIC message for APs or NMI for BSP.
1002 */
1003 if (apic->wakeup_secondary_cpu)
1004 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1005 else
1006 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1007 cpu0_nmi_registered);
1008
1009 if (!boot_error) {
1010 /*
1011 * Wait 10s total for first sign of life from AP
1012 */
1013 boot_error = -1;
1014 timeout = jiffies + 10*HZ;
1015 while (time_before(jiffies, timeout)) {
1016 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1017 /*
1018 * Tell AP to proceed with initialization
1019 */
1020 cpumask_set_cpu(cpu, cpu_callout_mask);
1021 boot_error = 0;
1022 break;
1023 }
1024 schedule();
1025 }
1026 }
1027
1028 if (!boot_error) {
1029 /*
1030 * Wait till AP completes initial initialization
1031 */
1032 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1033 /*
1034 * Allow other tasks to run while we wait for the
1035 * AP to come online. This also gives a chance
1036 * for the MTRR work(triggered by the AP coming online)
1037 * to be completed in the stop machine context.
1038 */
1039 schedule();
1040 }
1041 }
1042
1043 /* mark "stuck" area as not stuck */
1044 *trampoline_status = 0;
1045
1046 if (x86_platform.legacy.warm_reset) {
1047 /*
1048 * Cleanup possible dangling ends...
1049 */
1050 smpboot_restore_warm_reset_vector();
1051 }
1052
1053 return boot_error;
1054}
1055
1056int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1057{
1058 int apicid = apic->cpu_present_to_apicid(cpu);
1059 int cpu0_nmi_registered = 0;
1060 unsigned long flags;
1061 int err, ret = 0;
1062
1063 lockdep_assert_irqs_enabled();
1064
1065 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1066
1067 if (apicid == BAD_APICID ||
1068 !physid_isset(apicid, phys_cpu_present_map) ||
1069 !apic->apic_id_valid(apicid)) {
1070 pr_err("%s: bad cpu %d\n", __func__, cpu);
1071 return -EINVAL;
1072 }
1073
1074 /*
1075 * Already booted CPU?
1076 */
1077 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1078 pr_debug("do_boot_cpu %d Already started\n", cpu);
1079 return -ENOSYS;
1080 }
1081
1082 /*
1083 * Save current MTRR state in case it was changed since early boot
1084 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1085 */
1086 mtrr_save_state();
1087
1088 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1089 err = cpu_check_up_prepare(cpu);
1090 if (err && err != -EBUSY)
1091 return err;
1092
1093 /* the FPU context is blank, nobody can own it */
1094 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1095
1096 common_cpu_up(cpu, tidle);
1097
1098 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered);
1099 if (err) {
1100 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1101 ret = -EIO;
1102 goto unreg_nmi;
1103 }
1104
1105 /*
1106 * Check TSC synchronization with the AP (keep irqs disabled
1107 * while doing so):
1108 */
1109 local_irq_save(flags);
1110 check_tsc_sync_source(cpu);
1111 local_irq_restore(flags);
1112
1113 while (!cpu_online(cpu)) {
1114 cpu_relax();
1115 touch_nmi_watchdog();
1116 }
1117
1118unreg_nmi:
1119 /*
1120 * Clean up the nmi handler. Do this after the callin and callout sync
1121 * to avoid impact of possible long unregister time.
1122 */
1123 if (cpu0_nmi_registered)
1124 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1125
1126 return ret;
1127}
1128
1129/**
1130 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1131 */
1132void arch_disable_smp_support(void)
1133{
1134 disable_ioapic_support();
1135}
1136
1137/*
1138 * Fall back to non SMP mode after errors.
1139 *
1140 * RED-PEN audit/test this more. I bet there is more state messed up here.
1141 */
1142static __init void disable_smp(void)
1143{
1144 pr_info("SMP disabled\n");
1145
1146 disable_ioapic_support();
1147
1148 init_cpu_present(cpumask_of(0));
1149 init_cpu_possible(cpumask_of(0));
1150
1151 if (smp_found_config)
1152 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1153 else
1154 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1155 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1156 cpumask_set_cpu(0, topology_core_cpumask(0));
1157}
1158
1159/*
1160 * Various sanity checks.
1161 */
1162static void __init smp_sanity_check(void)
1163{
1164 preempt_disable();
1165
1166#if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1167 if (def_to_bigsmp && nr_cpu_ids > 8) {
1168 unsigned int cpu;
1169 unsigned nr;
1170
1171 pr_warn("More than 8 CPUs detected - skipping them\n"
1172 "Use CONFIG_X86_BIGSMP\n");
1173
1174 nr = 0;
1175 for_each_present_cpu(cpu) {
1176 if (nr >= 8)
1177 set_cpu_present(cpu, false);
1178 nr++;
1179 }
1180
1181 nr = 0;
1182 for_each_possible_cpu(cpu) {
1183 if (nr >= 8)
1184 set_cpu_possible(cpu, false);
1185 nr++;
1186 }
1187
1188 nr_cpu_ids = 8;
1189 }
1190#endif
1191
1192 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1193 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1194 hard_smp_processor_id());
1195
1196 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1197 }
1198
1199 /*
1200 * Should not be necessary because the MP table should list the boot
1201 * CPU too, but we do it for the sake of robustness anyway.
1202 */
1203 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1204 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1205 boot_cpu_physical_apicid);
1206 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1207 }
1208 preempt_enable();
1209}
1210
1211static void __init smp_cpu_index_default(void)
1212{
1213 int i;
1214 struct cpuinfo_x86 *c;
1215
1216 for_each_possible_cpu(i) {
1217 c = &cpu_data(i);
1218 /* mark all to hotplug */
1219 c->cpu_index = nr_cpu_ids;
1220 }
1221}
1222
1223static void __init smp_get_logical_apicid(void)
1224{
1225 if (x2apic_mode)
1226 cpu0_logical_apicid = apic_read(APIC_LDR);
1227 else
1228 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1229}
1230
1231/*
1232 * Prepare for SMP bootup.
1233 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1234 * for common interface support.
1235 */
1236void __init native_smp_prepare_cpus(unsigned int max_cpus)
1237{
1238 unsigned int i;
1239
1240 smp_cpu_index_default();
1241
1242 /*
1243 * Setup boot CPU information
1244 */
1245 smp_store_boot_cpu_info(); /* Final full version of the data */
1246 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1247 mb();
1248
1249 for_each_possible_cpu(i) {
1250 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1251 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1252 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1253 }
1254
1255 /*
1256 * Set 'default' x86 topology, this matches default_topology() in that
1257 * it has NUMA nodes as a topology level. See also
1258 * native_smp_cpus_done().
1259 *
1260 * Must be done before set_cpus_sibling_map() is ran.
1261 */
1262 set_sched_topology(x86_topology);
1263
1264 set_cpu_sibling_map(0);
1265
1266 smp_sanity_check();
1267
1268 switch (apic_intr_mode) {
1269 case APIC_PIC:
1270 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1271 disable_smp();
1272 return;
1273 case APIC_SYMMETRIC_IO_NO_ROUTING:
1274 disable_smp();
1275 /* Setup local timer */
1276 x86_init.timers.setup_percpu_clockev();
1277 return;
1278 case APIC_VIRTUAL_WIRE:
1279 case APIC_SYMMETRIC_IO:
1280 break;
1281 }
1282
1283 /* Setup local timer */
1284 x86_init.timers.setup_percpu_clockev();
1285
1286 smp_get_logical_apicid();
1287
1288 pr_info("CPU0: ");
1289 print_cpu_info(&cpu_data(0));
1290
1291 native_pv_lock_init();
1292
1293 uv_system_init();
1294
1295 set_mtrr_aps_delayed_init();
1296
1297 smp_quirk_init_udelay();
1298
1299 speculative_store_bypass_ht_init();
1300}
1301
1302void arch_enable_nonboot_cpus_begin(void)
1303{
1304 set_mtrr_aps_delayed_init();
1305}
1306
1307void arch_enable_nonboot_cpus_end(void)
1308{
1309 mtrr_aps_init();
1310}
1311
1312/*
1313 * Early setup to make printk work.
1314 */
1315void __init native_smp_prepare_boot_cpu(void)
1316{
1317 int me = smp_processor_id();
1318 switch_to_new_gdt(me);
1319 /* already set me in cpu_online_mask in boot_cpu_init() */
1320 cpumask_set_cpu(me, cpu_callout_mask);
1321 cpu_set_state_online(me);
1322}
1323
1324void __init calculate_max_logical_packages(void)
1325{
1326 int ncpus;
1327
1328 /*
1329 * Today neither Intel nor AMD support heterogenous systems so
1330 * extrapolate the boot cpu's data to all packages.
1331 */
1332 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads();
1333 __max_logical_packages = DIV_ROUND_UP(nr_cpu_ids, ncpus);
1334 pr_info("Max logical packages: %u\n", __max_logical_packages);
1335}
1336
1337void __init native_smp_cpus_done(unsigned int max_cpus)
1338{
1339 pr_debug("Boot done\n");
1340
1341 calculate_max_logical_packages();
1342
1343 if (x86_has_numa_in_package)
1344 set_sched_topology(x86_numa_in_package_topology);
1345
1346 nmi_selftest();
1347 impress_friends();
1348 mtrr_aps_init();
1349}
1350
1351static int __initdata setup_possible_cpus = -1;
1352static int __init _setup_possible_cpus(char *str)
1353{
1354 get_option(&str, &setup_possible_cpus);
1355 return 0;
1356}
1357early_param("possible_cpus", _setup_possible_cpus);
1358
1359
1360/*
1361 * cpu_possible_mask should be static, it cannot change as cpu's
1362 * are onlined, or offlined. The reason is per-cpu data-structures
1363 * are allocated by some modules at init time, and dont expect to
1364 * do this dynamically on cpu arrival/departure.
1365 * cpu_present_mask on the other hand can change dynamically.
1366 * In case when cpu_hotplug is not compiled, then we resort to current
1367 * behaviour, which is cpu_possible == cpu_present.
1368 * - Ashok Raj
1369 *
1370 * Three ways to find out the number of additional hotplug CPUs:
1371 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1372 * - The user can overwrite it with possible_cpus=NUM
1373 * - Otherwise don't reserve additional CPUs.
1374 * We do this because additional CPUs waste a lot of memory.
1375 * -AK
1376 */
1377__init void prefill_possible_map(void)
1378{
1379 int i, possible;
1380
1381 /* No boot processor was found in mptable or ACPI MADT */
1382 if (!num_processors) {
1383 if (boot_cpu_has(X86_FEATURE_APIC)) {
1384 int apicid = boot_cpu_physical_apicid;
1385 int cpu = hard_smp_processor_id();
1386
1387 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1388
1389 /* Make sure boot cpu is enumerated */
1390 if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1391 apic->apic_id_valid(apicid))
1392 generic_processor_info(apicid, boot_cpu_apic_version);
1393 }
1394
1395 if (!num_processors)
1396 num_processors = 1;
1397 }
1398
1399 i = setup_max_cpus ?: 1;
1400 if (setup_possible_cpus == -1) {
1401 possible = num_processors;
1402#ifdef CONFIG_HOTPLUG_CPU
1403 if (setup_max_cpus)
1404 possible += disabled_cpus;
1405#else
1406 if (possible > i)
1407 possible = i;
1408#endif
1409 } else
1410 possible = setup_possible_cpus;
1411
1412 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1413
1414 /* nr_cpu_ids could be reduced via nr_cpus= */
1415 if (possible > nr_cpu_ids) {
1416 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1417 possible, nr_cpu_ids);
1418 possible = nr_cpu_ids;
1419 }
1420
1421#ifdef CONFIG_HOTPLUG_CPU
1422 if (!setup_max_cpus)
1423#endif
1424 if (possible > i) {
1425 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1426 possible, setup_max_cpus);
1427 possible = i;
1428 }
1429
1430 nr_cpu_ids = possible;
1431
1432 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1433 possible, max_t(int, possible - num_processors, 0));
1434
1435 reset_cpu_possible_mask();
1436
1437 for (i = 0; i < possible; i++)
1438 set_cpu_possible(i, true);
1439}
1440
1441#ifdef CONFIG_HOTPLUG_CPU
1442
1443/* Recompute SMT state for all CPUs on offline */
1444static void recompute_smt_state(void)
1445{
1446 int max_threads, cpu;
1447
1448 max_threads = 0;
1449 for_each_online_cpu (cpu) {
1450 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1451
1452 if (threads > max_threads)
1453 max_threads = threads;
1454 }
1455 __max_smt_threads = max_threads;
1456}
1457
1458static void remove_siblinginfo(int cpu)
1459{
1460 int sibling;
1461 struct cpuinfo_x86 *c = &cpu_data(cpu);
1462
1463 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1464 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1465 /*/
1466 * last thread sibling in this cpu core going down
1467 */
1468 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1469 cpu_data(sibling).booted_cores--;
1470 }
1471
1472 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1473 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1474 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1475 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1476 cpumask_clear(cpu_llc_shared_mask(cpu));
1477 cpumask_clear(topology_sibling_cpumask(cpu));
1478 cpumask_clear(topology_core_cpumask(cpu));
1479 c->cpu_core_id = 0;
1480 c->booted_cores = 0;
1481 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1482 recompute_smt_state();
1483}
1484
1485static void remove_cpu_from_maps(int cpu)
1486{
1487 set_cpu_online(cpu, false);
1488 cpumask_clear_cpu(cpu, cpu_callout_mask);
1489 cpumask_clear_cpu(cpu, cpu_callin_mask);
1490 /* was set by cpu_init() */
1491 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1492 numa_remove_cpu(cpu);
1493}
1494
1495void cpu_disable_common(void)
1496{
1497 int cpu = smp_processor_id();
1498
1499 remove_siblinginfo(cpu);
1500
1501 /* It's now safe to remove this processor from the online map */
1502 lock_vector_lock();
1503 remove_cpu_from_maps(cpu);
1504 unlock_vector_lock();
1505 fixup_irqs();
1506 lapic_offline();
1507}
1508
1509int native_cpu_disable(void)
1510{
1511 int ret;
1512
1513 ret = lapic_can_unplug_cpu();
1514 if (ret)
1515 return ret;
1516
1517 clear_local_APIC();
1518 cpu_disable_common();
1519
1520 return 0;
1521}
1522
1523int common_cpu_die(unsigned int cpu)
1524{
1525 int ret = 0;
1526
1527 /* We don't do anything here: idle task is faking death itself. */
1528
1529 /* They ack this in play_dead() by setting CPU_DEAD */
1530 if (cpu_wait_death(cpu, 5)) {
1531 if (system_state == SYSTEM_RUNNING)
1532 pr_info("CPU %u is now offline\n", cpu);
1533 } else {
1534 pr_err("CPU %u didn't die...\n", cpu);
1535 ret = -1;
1536 }
1537
1538 return ret;
1539}
1540
1541void native_cpu_die(unsigned int cpu)
1542{
1543 common_cpu_die(cpu);
1544}
1545
1546void play_dead_common(void)
1547{
1548 idle_task_exit();
1549
1550 /* Ack it */
1551 (void)cpu_report_death();
1552
1553 /*
1554 * With physical CPU hotplug, we should halt the cpu
1555 */
1556 local_irq_disable();
1557}
1558
1559static bool wakeup_cpu0(void)
1560{
1561 if (smp_processor_id() == 0 && enable_start_cpu0)
1562 return true;
1563
1564 return false;
1565}
1566
1567/*
1568 * We need to flush the caches before going to sleep, lest we have
1569 * dirty data in our caches when we come back up.
1570 */
1571static inline void mwait_play_dead(void)
1572{
1573 unsigned int eax, ebx, ecx, edx;
1574 unsigned int highest_cstate = 0;
1575 unsigned int highest_subcstate = 0;
1576 void *mwait_ptr;
1577 int i;
1578
1579 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1580 return;
1581 if (!this_cpu_has(X86_FEATURE_MWAIT))
1582 return;
1583 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1584 return;
1585 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1586 return;
1587
1588 eax = CPUID_MWAIT_LEAF;
1589 ecx = 0;
1590 native_cpuid(&eax, &ebx, &ecx, &edx);
1591
1592 /*
1593 * eax will be 0 if EDX enumeration is not valid.
1594 * Initialized below to cstate, sub_cstate value when EDX is valid.
1595 */
1596 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1597 eax = 0;
1598 } else {
1599 edx >>= MWAIT_SUBSTATE_SIZE;
1600 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1601 if (edx & MWAIT_SUBSTATE_MASK) {
1602 highest_cstate = i;
1603 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1604 }
1605 }
1606 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1607 (highest_subcstate - 1);
1608 }
1609
1610 /*
1611 * This should be a memory location in a cache line which is
1612 * unlikely to be touched by other processors. The actual
1613 * content is immaterial as it is not actually modified in any way.
1614 */
1615 mwait_ptr = ¤t_thread_info()->flags;
1616
1617 wbinvd();
1618
1619 while (1) {
1620 /*
1621 * The CLFLUSH is a workaround for erratum AAI65 for
1622 * the Xeon 7400 series. It's not clear it is actually
1623 * needed, but it should be harmless in either case.
1624 * The WBINVD is insufficient due to the spurious-wakeup
1625 * case where we return around the loop.
1626 */
1627 mb();
1628 clflush(mwait_ptr);
1629 mb();
1630 __monitor(mwait_ptr, 0, 0);
1631 mb();
1632 __mwait(eax, 0);
1633 /*
1634 * If NMI wants to wake up CPU0, start CPU0.
1635 */
1636 if (wakeup_cpu0())
1637 start_cpu0();
1638 }
1639}
1640
1641void hlt_play_dead(void)
1642{
1643 if (__this_cpu_read(cpu_info.x86) >= 4)
1644 wbinvd();
1645
1646 while (1) {
1647 native_halt();
1648 /*
1649 * If NMI wants to wake up CPU0, start CPU0.
1650 */
1651 if (wakeup_cpu0())
1652 start_cpu0();
1653 }
1654}
1655
1656void native_play_dead(void)
1657{
1658 play_dead_common();
1659 tboot_shutdown(TB_SHUTDOWN_WFS);
1660
1661 mwait_play_dead(); /* Only returns on failure */
1662 if (cpuidle_play_dead())
1663 hlt_play_dead();
1664}
1665
1666#else /* ... !CONFIG_HOTPLUG_CPU */
1667int native_cpu_disable(void)
1668{
1669 return -ENOSYS;
1670}
1671
1672void native_cpu_die(unsigned int cpu)
1673{
1674 /* We said "no" in __cpu_disable */
1675 BUG();
1676}
1677
1678void native_play_dead(void)
1679{
1680 BUG();
1681}
1682
1683#endif
1/*
2 * x86 SMP booting functions
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
7 *
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
10 *
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
14 *
15 * This code is released under the GNU General Public License version 2 or
16 * later.
17 *
18 * Fixes
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
29 * from Jose Renau
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
40 */
41
42#include <linux/init.h>
43#include <linux/smp.h>
44#include <linux/module.h>
45#include <linux/sched.h>
46#include <linux/percpu.h>
47#include <linux/bootmem.h>
48#include <linux/err.h>
49#include <linux/nmi.h>
50#include <linux/tboot.h>
51#include <linux/stackprotector.h>
52#include <linux/gfp.h>
53
54#include <asm/acpi.h>
55#include <asm/desc.h>
56#include <asm/nmi.h>
57#include <asm/irq.h>
58#include <asm/idle.h>
59#include <asm/trampoline.h>
60#include <asm/cpu.h>
61#include <asm/numa.h>
62#include <asm/pgtable.h>
63#include <asm/tlbflush.h>
64#include <asm/mtrr.h>
65#include <asm/mwait.h>
66#include <asm/apic.h>
67#include <asm/io_apic.h>
68#include <asm/setup.h>
69#include <asm/uv/uv.h>
70#include <linux/mc146818rtc.h>
71
72#include <asm/smpboot_hooks.h>
73#include <asm/i8259.h>
74
75/* State of each CPU */
76DEFINE_PER_CPU(int, cpu_state) = { 0 };
77
78/* Store all idle threads, this can be reused instead of creating
79* a new thread. Also avoids complicated thread destroy functionality
80* for idle threads.
81*/
82#ifdef CONFIG_HOTPLUG_CPU
83/*
84 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is
85 * removed after init for !CONFIG_HOTPLUG_CPU.
86 */
87static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
88#define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x))
89#define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p))
90
91/*
92 * We need this for trampoline_base protection from concurrent accesses when
93 * off- and onlining cores wildly.
94 */
95static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex);
96
97void cpu_hotplug_driver_lock(void)
98{
99 mutex_lock(&x86_cpu_hotplug_driver_mutex);
100}
101
102void cpu_hotplug_driver_unlock(void)
103{
104 mutex_unlock(&x86_cpu_hotplug_driver_mutex);
105}
106
107ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; }
108ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; }
109#else
110static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
111#define get_idle_for_cpu(x) (idle_thread_array[(x)])
112#define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p))
113#endif
114
115/* Number of siblings per CPU package */
116int smp_num_siblings = 1;
117EXPORT_SYMBOL(smp_num_siblings);
118
119/* Last level cache ID of each logical CPU */
120DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
121
122/* representing HT siblings of each logical CPU */
123DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);
124EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
125
126/* representing HT and core siblings of each logical CPU */
127DEFINE_PER_CPU(cpumask_var_t, cpu_core_map);
128EXPORT_PER_CPU_SYMBOL(cpu_core_map);
129
130DEFINE_PER_CPU(cpumask_var_t, cpu_llc_shared_map);
131
132/* Per CPU bogomips and other parameters */
133DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
134EXPORT_PER_CPU_SYMBOL(cpu_info);
135
136atomic_t init_deasserted;
137
138/*
139 * Report back to the Boot Processor.
140 * Running on AP.
141 */
142static void __cpuinit smp_callin(void)
143{
144 int cpuid, phys_id;
145 unsigned long timeout;
146
147 /*
148 * If waken up by an INIT in an 82489DX configuration
149 * we may get here before an INIT-deassert IPI reaches
150 * our local APIC. We have to wait for the IPI or we'll
151 * lock up on an APIC access.
152 */
153 if (apic->wait_for_init_deassert)
154 apic->wait_for_init_deassert(&init_deasserted);
155
156 /*
157 * (This works even if the APIC is not enabled.)
158 */
159 phys_id = read_apic_id();
160 cpuid = smp_processor_id();
161 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
162 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
163 phys_id, cpuid);
164 }
165 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
166
167 /*
168 * STARTUP IPIs are fragile beasts as they might sometimes
169 * trigger some glue motherboard logic. Complete APIC bus
170 * silence for 1 second, this overestimates the time the
171 * boot CPU is spending to send the up to 2 STARTUP IPIs
172 * by a factor of two. This should be enough.
173 */
174
175 /*
176 * Waiting 2s total for startup (udelay is not yet working)
177 */
178 timeout = jiffies + 2*HZ;
179 while (time_before(jiffies, timeout)) {
180 /*
181 * Has the boot CPU finished it's STARTUP sequence?
182 */
183 if (cpumask_test_cpu(cpuid, cpu_callout_mask))
184 break;
185 cpu_relax();
186 }
187
188 if (!time_before(jiffies, timeout)) {
189 panic("%s: CPU%d started up but did not get a callout!\n",
190 __func__, cpuid);
191 }
192
193 /*
194 * the boot CPU has finished the init stage and is spinning
195 * on callin_map until we finish. We are free to set up this
196 * CPU, first the APIC. (this is probably redundant on most
197 * boards)
198 */
199
200 pr_debug("CALLIN, before setup_local_APIC().\n");
201 if (apic->smp_callin_clear_local_apic)
202 apic->smp_callin_clear_local_apic();
203 setup_local_APIC();
204 end_local_APIC_setup();
205
206 /*
207 * Need to setup vector mappings before we enable interrupts.
208 */
209 setup_vector_irq(smp_processor_id());
210 /*
211 * Get our bogomips.
212 *
213 * Need to enable IRQs because it can take longer and then
214 * the NMI watchdog might kill us.
215 */
216 local_irq_enable();
217 calibrate_delay();
218 local_irq_disable();
219 pr_debug("Stack at about %p\n", &cpuid);
220
221 /*
222 * Save our processor parameters
223 */
224 smp_store_cpu_info(cpuid);
225
226 /*
227 * This must be done before setting cpu_online_mask
228 * or calling notify_cpu_starting.
229 */
230 set_cpu_sibling_map(raw_smp_processor_id());
231 wmb();
232
233 notify_cpu_starting(cpuid);
234
235 /*
236 * Allow the master to continue.
237 */
238 cpumask_set_cpu(cpuid, cpu_callin_mask);
239}
240
241/*
242 * Activate a secondary processor.
243 */
244notrace static void __cpuinit start_secondary(void *unused)
245{
246 /*
247 * Don't put *anything* before cpu_init(), SMP booting is too
248 * fragile that we want to limit the things done here to the
249 * most necessary things.
250 */
251 cpu_init();
252 preempt_disable();
253 smp_callin();
254
255#ifdef CONFIG_X86_32
256 /* switch away from the initial page table */
257 load_cr3(swapper_pg_dir);
258 __flush_tlb_all();
259#endif
260
261 /* otherwise gcc will move up smp_processor_id before the cpu_init */
262 barrier();
263 /*
264 * Check TSC synchronization with the BP:
265 */
266 check_tsc_sync_target();
267
268 /*
269 * We need to hold call_lock, so there is no inconsistency
270 * between the time smp_call_function() determines number of
271 * IPI recipients, and the time when the determination is made
272 * for which cpus receive the IPI. Holding this
273 * lock helps us to not include this cpu in a currently in progress
274 * smp_call_function().
275 *
276 * We need to hold vector_lock so there the set of online cpus
277 * does not change while we are assigning vectors to cpus. Holding
278 * this lock ensures we don't half assign or remove an irq from a cpu.
279 */
280 ipi_call_lock();
281 lock_vector_lock();
282 set_cpu_online(smp_processor_id(), true);
283 unlock_vector_lock();
284 ipi_call_unlock();
285 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
286 x86_platform.nmi_init();
287
288 /*
289 * Wait until the cpu which brought this one up marked it
290 * online before enabling interrupts. If we don't do that then
291 * we can end up waking up the softirq thread before this cpu
292 * reached the active state, which makes the scheduler unhappy
293 * and schedule the softirq thread on the wrong cpu. This is
294 * only observable with forced threaded interrupts, but in
295 * theory it could also happen w/o them. It's just way harder
296 * to achieve.
297 */
298 while (!cpumask_test_cpu(smp_processor_id(), cpu_active_mask))
299 cpu_relax();
300
301 /* enable local interrupts */
302 local_irq_enable();
303
304 /* to prevent fake stack check failure in clock setup */
305 boot_init_stack_canary();
306
307 x86_cpuinit.setup_percpu_clockev();
308
309 wmb();
310 cpu_idle();
311}
312
313/*
314 * The bootstrap kernel entry code has set these up. Save them for
315 * a given CPU
316 */
317
318void __cpuinit smp_store_cpu_info(int id)
319{
320 struct cpuinfo_x86 *c = &cpu_data(id);
321
322 *c = boot_cpu_data;
323 c->cpu_index = id;
324 if (id != 0)
325 identify_secondary_cpu(c);
326}
327
328static void __cpuinit link_thread_siblings(int cpu1, int cpu2)
329{
330 cpumask_set_cpu(cpu1, cpu_sibling_mask(cpu2));
331 cpumask_set_cpu(cpu2, cpu_sibling_mask(cpu1));
332 cpumask_set_cpu(cpu1, cpu_core_mask(cpu2));
333 cpumask_set_cpu(cpu2, cpu_core_mask(cpu1));
334 cpumask_set_cpu(cpu1, cpu_llc_shared_mask(cpu2));
335 cpumask_set_cpu(cpu2, cpu_llc_shared_mask(cpu1));
336}
337
338
339void __cpuinit set_cpu_sibling_map(int cpu)
340{
341 int i;
342 struct cpuinfo_x86 *c = &cpu_data(cpu);
343
344 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
345
346 if (smp_num_siblings > 1) {
347 for_each_cpu(i, cpu_sibling_setup_mask) {
348 struct cpuinfo_x86 *o = &cpu_data(i);
349
350 if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
351 if (c->phys_proc_id == o->phys_proc_id &&
352 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i) &&
353 c->compute_unit_id == o->compute_unit_id)
354 link_thread_siblings(cpu, i);
355 } else if (c->phys_proc_id == o->phys_proc_id &&
356 c->cpu_core_id == o->cpu_core_id) {
357 link_thread_siblings(cpu, i);
358 }
359 }
360 } else {
361 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
362 }
363
364 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
365
366 if (__this_cpu_read(cpu_info.x86_max_cores) == 1) {
367 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu));
368 c->booted_cores = 1;
369 return;
370 }
371
372 for_each_cpu(i, cpu_sibling_setup_mask) {
373 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID &&
374 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) {
375 cpumask_set_cpu(i, cpu_llc_shared_mask(cpu));
376 cpumask_set_cpu(cpu, cpu_llc_shared_mask(i));
377 }
378 if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
379 cpumask_set_cpu(i, cpu_core_mask(cpu));
380 cpumask_set_cpu(cpu, cpu_core_mask(i));
381 /*
382 * Does this new cpu bringup a new core?
383 */
384 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
385 /*
386 * for each core in package, increment
387 * the booted_cores for this new cpu
388 */
389 if (cpumask_first(cpu_sibling_mask(i)) == i)
390 c->booted_cores++;
391 /*
392 * increment the core count for all
393 * the other cpus in this package
394 */
395 if (i != cpu)
396 cpu_data(i).booted_cores++;
397 } else if (i != cpu && !c->booted_cores)
398 c->booted_cores = cpu_data(i).booted_cores;
399 }
400 }
401}
402
403/* maps the cpu to the sched domain representing multi-core */
404const struct cpumask *cpu_coregroup_mask(int cpu)
405{
406 struct cpuinfo_x86 *c = &cpu_data(cpu);
407 /*
408 * For perf, we return last level cache shared map.
409 * And for power savings, we return cpu_core_map
410 */
411 if ((sched_mc_power_savings || sched_smt_power_savings) &&
412 !(cpu_has(c, X86_FEATURE_AMD_DCM)))
413 return cpu_core_mask(cpu);
414 else
415 return cpu_llc_shared_mask(cpu);
416}
417
418static void impress_friends(void)
419{
420 int cpu;
421 unsigned long bogosum = 0;
422 /*
423 * Allow the user to impress friends.
424 */
425 pr_debug("Before bogomips.\n");
426 for_each_possible_cpu(cpu)
427 if (cpumask_test_cpu(cpu, cpu_callout_mask))
428 bogosum += cpu_data(cpu).loops_per_jiffy;
429 printk(KERN_INFO
430 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
431 num_online_cpus(),
432 bogosum/(500000/HZ),
433 (bogosum/(5000/HZ))%100);
434
435 pr_debug("Before bogocount - setting activated=1.\n");
436}
437
438void __inquire_remote_apic(int apicid)
439{
440 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
441 const char * const names[] = { "ID", "VERSION", "SPIV" };
442 int timeout;
443 u32 status;
444
445 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid);
446
447 for (i = 0; i < ARRAY_SIZE(regs); i++) {
448 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]);
449
450 /*
451 * Wait for idle.
452 */
453 status = safe_apic_wait_icr_idle();
454 if (status)
455 printk(KERN_CONT
456 "a previous APIC delivery may have failed\n");
457
458 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
459
460 timeout = 0;
461 do {
462 udelay(100);
463 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
464 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
465
466 switch (status) {
467 case APIC_ICR_RR_VALID:
468 status = apic_read(APIC_RRR);
469 printk(KERN_CONT "%08x\n", status);
470 break;
471 default:
472 printk(KERN_CONT "failed\n");
473 }
474 }
475}
476
477/*
478 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
479 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
480 * won't ... remember to clear down the APIC, etc later.
481 */
482int __cpuinit
483wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip)
484{
485 unsigned long send_status, accept_status = 0;
486 int maxlvt;
487
488 /* Target chip */
489 /* Boot on the stack */
490 /* Kick the second */
491 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid);
492
493 pr_debug("Waiting for send to finish...\n");
494 send_status = safe_apic_wait_icr_idle();
495
496 /*
497 * Give the other CPU some time to accept the IPI.
498 */
499 udelay(200);
500 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
501 maxlvt = lapic_get_maxlvt();
502 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
503 apic_write(APIC_ESR, 0);
504 accept_status = (apic_read(APIC_ESR) & 0xEF);
505 }
506 pr_debug("NMI sent.\n");
507
508 if (send_status)
509 printk(KERN_ERR "APIC never delivered???\n");
510 if (accept_status)
511 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
512
513 return (send_status | accept_status);
514}
515
516static int __cpuinit
517wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
518{
519 unsigned long send_status, accept_status = 0;
520 int maxlvt, num_starts, j;
521
522 maxlvt = lapic_get_maxlvt();
523
524 /*
525 * Be paranoid about clearing APIC errors.
526 */
527 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
528 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
529 apic_write(APIC_ESR, 0);
530 apic_read(APIC_ESR);
531 }
532
533 pr_debug("Asserting INIT.\n");
534
535 /*
536 * Turn INIT on target chip
537 */
538 /*
539 * Send IPI
540 */
541 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
542 phys_apicid);
543
544 pr_debug("Waiting for send to finish...\n");
545 send_status = safe_apic_wait_icr_idle();
546
547 mdelay(10);
548
549 pr_debug("Deasserting INIT.\n");
550
551 /* Target chip */
552 /* Send IPI */
553 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
554
555 pr_debug("Waiting for send to finish...\n");
556 send_status = safe_apic_wait_icr_idle();
557
558 mb();
559 atomic_set(&init_deasserted, 1);
560
561 /*
562 * Should we send STARTUP IPIs ?
563 *
564 * Determine this based on the APIC version.
565 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
566 */
567 if (APIC_INTEGRATED(apic_version[phys_apicid]))
568 num_starts = 2;
569 else
570 num_starts = 0;
571
572 /*
573 * Paravirt / VMI wants a startup IPI hook here to set up the
574 * target processor state.
575 */
576 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
577 stack_start);
578
579 /*
580 * Run STARTUP IPI loop.
581 */
582 pr_debug("#startup loops: %d.\n", num_starts);
583
584 for (j = 1; j <= num_starts; j++) {
585 pr_debug("Sending STARTUP #%d.\n", j);
586 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
587 apic_write(APIC_ESR, 0);
588 apic_read(APIC_ESR);
589 pr_debug("After apic_write.\n");
590
591 /*
592 * STARTUP IPI
593 */
594
595 /* Target chip */
596 /* Boot on the stack */
597 /* Kick the second */
598 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
599 phys_apicid);
600
601 /*
602 * Give the other CPU some time to accept the IPI.
603 */
604 udelay(300);
605
606 pr_debug("Startup point 1.\n");
607
608 pr_debug("Waiting for send to finish...\n");
609 send_status = safe_apic_wait_icr_idle();
610
611 /*
612 * Give the other CPU some time to accept the IPI.
613 */
614 udelay(200);
615 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
616 apic_write(APIC_ESR, 0);
617 accept_status = (apic_read(APIC_ESR) & 0xEF);
618 if (send_status || accept_status)
619 break;
620 }
621 pr_debug("After Startup.\n");
622
623 if (send_status)
624 printk(KERN_ERR "APIC never delivered???\n");
625 if (accept_status)
626 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
627
628 return (send_status | accept_status);
629}
630
631struct create_idle {
632 struct work_struct work;
633 struct task_struct *idle;
634 struct completion done;
635 int cpu;
636};
637
638static void __cpuinit do_fork_idle(struct work_struct *work)
639{
640 struct create_idle *c_idle =
641 container_of(work, struct create_idle, work);
642
643 c_idle->idle = fork_idle(c_idle->cpu);
644 complete(&c_idle->done);
645}
646
647/* reduce the number of lines printed when booting a large cpu count system */
648static void __cpuinit announce_cpu(int cpu, int apicid)
649{
650 static int current_node = -1;
651 int node = early_cpu_to_node(cpu);
652
653 if (system_state == SYSTEM_BOOTING) {
654 if (node != current_node) {
655 if (current_node > (-1))
656 pr_cont(" Ok.\n");
657 current_node = node;
658 pr_info("Booting Node %3d, Processors ", node);
659 }
660 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : "");
661 return;
662 } else
663 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
664 node, cpu, apicid);
665}
666
667/*
668 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
669 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
670 * Returns zero if CPU booted OK, else error code from
671 * ->wakeup_secondary_cpu.
672 */
673static int __cpuinit do_boot_cpu(int apicid, int cpu)
674{
675 unsigned long boot_error = 0;
676 unsigned long start_ip;
677 int timeout;
678 struct create_idle c_idle = {
679 .cpu = cpu,
680 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
681 };
682
683 INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle);
684
685 alternatives_smp_switch(1);
686
687 c_idle.idle = get_idle_for_cpu(cpu);
688
689 /*
690 * We can't use kernel_thread since we must avoid to
691 * reschedule the child.
692 */
693 if (c_idle.idle) {
694 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *)
695 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1);
696 init_idle(c_idle.idle, cpu);
697 goto do_rest;
698 }
699
700 schedule_work(&c_idle.work);
701 wait_for_completion(&c_idle.done);
702
703 if (IS_ERR(c_idle.idle)) {
704 printk("failed fork for CPU %d\n", cpu);
705 destroy_work_on_stack(&c_idle.work);
706 return PTR_ERR(c_idle.idle);
707 }
708
709 set_idle_for_cpu(cpu, c_idle.idle);
710do_rest:
711 per_cpu(current_task, cpu) = c_idle.idle;
712#ifdef CONFIG_X86_32
713 /* Stack for startup_32 can be just as for start_secondary onwards */
714 irq_ctx_init(cpu);
715#else
716 clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
717 initial_gs = per_cpu_offset(cpu);
718 per_cpu(kernel_stack, cpu) =
719 (unsigned long)task_stack_page(c_idle.idle) -
720 KERNEL_STACK_OFFSET + THREAD_SIZE;
721#endif
722 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
723 initial_code = (unsigned long)start_secondary;
724 stack_start = c_idle.idle->thread.sp;
725
726 /* start_ip had better be page-aligned! */
727 start_ip = trampoline_address();
728
729 /* So we see what's up */
730 announce_cpu(cpu, apicid);
731
732 /*
733 * This grunge runs the startup process for
734 * the targeted processor.
735 */
736
737 printk(KERN_DEBUG "smpboot cpu %d: start_ip = %lx\n", cpu, start_ip);
738
739 atomic_set(&init_deasserted, 0);
740
741 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
742
743 pr_debug("Setting warm reset code and vector.\n");
744
745 smpboot_setup_warm_reset_vector(start_ip);
746 /*
747 * Be paranoid about clearing APIC errors.
748 */
749 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
750 apic_write(APIC_ESR, 0);
751 apic_read(APIC_ESR);
752 }
753 }
754
755 /*
756 * Kick the secondary CPU. Use the method in the APIC driver
757 * if it's defined - or use an INIT boot APIC message otherwise:
758 */
759 if (apic->wakeup_secondary_cpu)
760 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
761 else
762 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
763
764 if (!boot_error) {
765 /*
766 * allow APs to start initializing.
767 */
768 pr_debug("Before Callout %d.\n", cpu);
769 cpumask_set_cpu(cpu, cpu_callout_mask);
770 pr_debug("After Callout %d.\n", cpu);
771
772 /*
773 * Wait 5s total for a response
774 */
775 for (timeout = 0; timeout < 50000; timeout++) {
776 if (cpumask_test_cpu(cpu, cpu_callin_mask))
777 break; /* It has booted */
778 udelay(100);
779 /*
780 * Allow other tasks to run while we wait for the
781 * AP to come online. This also gives a chance
782 * for the MTRR work(triggered by the AP coming online)
783 * to be completed in the stop machine context.
784 */
785 schedule();
786 }
787
788 if (cpumask_test_cpu(cpu, cpu_callin_mask))
789 pr_debug("CPU%d: has booted.\n", cpu);
790 else {
791 boot_error = 1;
792 if (*(volatile u32 *)TRAMPOLINE_SYM(trampoline_status)
793 == 0xA5A5A5A5)
794 /* trampoline started but...? */
795 pr_err("CPU%d: Stuck ??\n", cpu);
796 else
797 /* trampoline code not run */
798 pr_err("CPU%d: Not responding.\n", cpu);
799 if (apic->inquire_remote_apic)
800 apic->inquire_remote_apic(apicid);
801 }
802 }
803
804 if (boot_error) {
805 /* Try to put things back the way they were before ... */
806 numa_remove_cpu(cpu); /* was set by numa_add_cpu */
807
808 /* was set by do_boot_cpu() */
809 cpumask_clear_cpu(cpu, cpu_callout_mask);
810
811 /* was set by cpu_init() */
812 cpumask_clear_cpu(cpu, cpu_initialized_mask);
813
814 set_cpu_present(cpu, false);
815 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
816 }
817
818 /* mark "stuck" area as not stuck */
819 *(volatile u32 *)TRAMPOLINE_SYM(trampoline_status) = 0;
820
821 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
822 /*
823 * Cleanup possible dangling ends...
824 */
825 smpboot_restore_warm_reset_vector();
826 }
827
828 destroy_work_on_stack(&c_idle.work);
829 return boot_error;
830}
831
832int __cpuinit native_cpu_up(unsigned int cpu)
833{
834 int apicid = apic->cpu_present_to_apicid(cpu);
835 unsigned long flags;
836 int err;
837
838 WARN_ON(irqs_disabled());
839
840 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
841
842 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid ||
843 !physid_isset(apicid, phys_cpu_present_map)) {
844 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu);
845 return -EINVAL;
846 }
847
848 /*
849 * Already booted CPU?
850 */
851 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
852 pr_debug("do_boot_cpu %d Already started\n", cpu);
853 return -ENOSYS;
854 }
855
856 /*
857 * Save current MTRR state in case it was changed since early boot
858 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
859 */
860 mtrr_save_state();
861
862 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
863
864 err = do_boot_cpu(apicid, cpu);
865 if (err) {
866 pr_debug("do_boot_cpu failed %d\n", err);
867 return -EIO;
868 }
869
870 /*
871 * Check TSC synchronization with the AP (keep irqs disabled
872 * while doing so):
873 */
874 local_irq_save(flags);
875 check_tsc_sync_source(cpu);
876 local_irq_restore(flags);
877
878 while (!cpu_online(cpu)) {
879 cpu_relax();
880 touch_nmi_watchdog();
881 }
882
883 return 0;
884}
885
886/**
887 * arch_disable_smp_support() - disables SMP support for x86 at runtime
888 */
889void arch_disable_smp_support(void)
890{
891 disable_ioapic_support();
892}
893
894/*
895 * Fall back to non SMP mode after errors.
896 *
897 * RED-PEN audit/test this more. I bet there is more state messed up here.
898 */
899static __init void disable_smp(void)
900{
901 init_cpu_present(cpumask_of(0));
902 init_cpu_possible(cpumask_of(0));
903 smpboot_clear_io_apic_irqs();
904
905 if (smp_found_config)
906 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
907 else
908 physid_set_mask_of_physid(0, &phys_cpu_present_map);
909 cpumask_set_cpu(0, cpu_sibling_mask(0));
910 cpumask_set_cpu(0, cpu_core_mask(0));
911}
912
913/*
914 * Various sanity checks.
915 */
916static int __init smp_sanity_check(unsigned max_cpus)
917{
918 preempt_disable();
919
920#if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
921 if (def_to_bigsmp && nr_cpu_ids > 8) {
922 unsigned int cpu;
923 unsigned nr;
924
925 printk(KERN_WARNING
926 "More than 8 CPUs detected - skipping them.\n"
927 "Use CONFIG_X86_BIGSMP.\n");
928
929 nr = 0;
930 for_each_present_cpu(cpu) {
931 if (nr >= 8)
932 set_cpu_present(cpu, false);
933 nr++;
934 }
935
936 nr = 0;
937 for_each_possible_cpu(cpu) {
938 if (nr >= 8)
939 set_cpu_possible(cpu, false);
940 nr++;
941 }
942
943 nr_cpu_ids = 8;
944 }
945#endif
946
947 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
948 printk(KERN_WARNING
949 "weird, boot CPU (#%d) not listed by the BIOS.\n",
950 hard_smp_processor_id());
951
952 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
953 }
954
955 /*
956 * If we couldn't find an SMP configuration at boot time,
957 * get out of here now!
958 */
959 if (!smp_found_config && !acpi_lapic) {
960 preempt_enable();
961 printk(KERN_NOTICE "SMP motherboard not detected.\n");
962 disable_smp();
963 if (APIC_init_uniprocessor())
964 printk(KERN_NOTICE "Local APIC not detected."
965 " Using dummy APIC emulation.\n");
966 return -1;
967 }
968
969 /*
970 * Should not be necessary because the MP table should list the boot
971 * CPU too, but we do it for the sake of robustness anyway.
972 */
973 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
974 printk(KERN_NOTICE
975 "weird, boot CPU (#%d) not listed by the BIOS.\n",
976 boot_cpu_physical_apicid);
977 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
978 }
979 preempt_enable();
980
981 /*
982 * If we couldn't find a local APIC, then get out of here now!
983 */
984 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
985 !cpu_has_apic) {
986 if (!disable_apic) {
987 pr_err("BIOS bug, local APIC #%d not detected!...\n",
988 boot_cpu_physical_apicid);
989 pr_err("... forcing use of dummy APIC emulation."
990 "(tell your hw vendor)\n");
991 }
992 smpboot_clear_io_apic();
993 disable_ioapic_support();
994 return -1;
995 }
996
997 verify_local_APIC();
998
999 /*
1000 * If SMP should be disabled, then really disable it!
1001 */
1002 if (!max_cpus) {
1003 printk(KERN_INFO "SMP mode deactivated.\n");
1004 smpboot_clear_io_apic();
1005
1006 connect_bsp_APIC();
1007 setup_local_APIC();
1008 bsp_end_local_APIC_setup();
1009 return -1;
1010 }
1011
1012 return 0;
1013}
1014
1015static void __init smp_cpu_index_default(void)
1016{
1017 int i;
1018 struct cpuinfo_x86 *c;
1019
1020 for_each_possible_cpu(i) {
1021 c = &cpu_data(i);
1022 /* mark all to hotplug */
1023 c->cpu_index = nr_cpu_ids;
1024 }
1025}
1026
1027/*
1028 * Prepare for SMP bootup. The MP table or ACPI has been read
1029 * earlier. Just do some sanity checking here and enable APIC mode.
1030 */
1031void __init native_smp_prepare_cpus(unsigned int max_cpus)
1032{
1033 unsigned int i;
1034
1035 preempt_disable();
1036 smp_cpu_index_default();
1037
1038 /*
1039 * Setup boot CPU information
1040 */
1041 smp_store_cpu_info(0); /* Final full version of the data */
1042 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1043 mb();
1044
1045 current_thread_info()->cpu = 0; /* needed? */
1046 for_each_possible_cpu(i) {
1047 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1048 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1049 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1050 }
1051 set_cpu_sibling_map(0);
1052
1053
1054 if (smp_sanity_check(max_cpus) < 0) {
1055 printk(KERN_INFO "SMP disabled\n");
1056 disable_smp();
1057 goto out;
1058 }
1059
1060 default_setup_apic_routing();
1061
1062 preempt_disable();
1063 if (read_apic_id() != boot_cpu_physical_apicid) {
1064 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1065 read_apic_id(), boot_cpu_physical_apicid);
1066 /* Or can we switch back to PIC here? */
1067 }
1068 preempt_enable();
1069
1070 connect_bsp_APIC();
1071
1072 /*
1073 * Switch from PIC to APIC mode.
1074 */
1075 setup_local_APIC();
1076
1077 /*
1078 * Enable IO APIC before setting up error vector
1079 */
1080 if (!skip_ioapic_setup && nr_ioapics)
1081 enable_IO_APIC();
1082
1083 bsp_end_local_APIC_setup();
1084
1085 if (apic->setup_portio_remap)
1086 apic->setup_portio_remap();
1087
1088 smpboot_setup_io_apic();
1089 /*
1090 * Set up local APIC timer on boot CPU.
1091 */
1092
1093 printk(KERN_INFO "CPU%d: ", 0);
1094 print_cpu_info(&cpu_data(0));
1095 x86_init.timers.setup_percpu_clockev();
1096
1097 if (is_uv_system())
1098 uv_system_init();
1099
1100 set_mtrr_aps_delayed_init();
1101out:
1102 preempt_enable();
1103}
1104
1105void arch_disable_nonboot_cpus_begin(void)
1106{
1107 /*
1108 * Avoid the smp alternatives switch during the disable_nonboot_cpus().
1109 * In the suspend path, we will be back in the SMP mode shortly anyways.
1110 */
1111 skip_smp_alternatives = true;
1112}
1113
1114void arch_disable_nonboot_cpus_end(void)
1115{
1116 skip_smp_alternatives = false;
1117}
1118
1119void arch_enable_nonboot_cpus_begin(void)
1120{
1121 set_mtrr_aps_delayed_init();
1122}
1123
1124void arch_enable_nonboot_cpus_end(void)
1125{
1126 mtrr_aps_init();
1127}
1128
1129/*
1130 * Early setup to make printk work.
1131 */
1132void __init native_smp_prepare_boot_cpu(void)
1133{
1134 int me = smp_processor_id();
1135 switch_to_new_gdt(me);
1136 /* already set me in cpu_online_mask in boot_cpu_init() */
1137 cpumask_set_cpu(me, cpu_callout_mask);
1138 per_cpu(cpu_state, me) = CPU_ONLINE;
1139}
1140
1141void __init native_smp_cpus_done(unsigned int max_cpus)
1142{
1143 pr_debug("Boot done.\n");
1144
1145 impress_friends();
1146#ifdef CONFIG_X86_IO_APIC
1147 setup_ioapic_dest();
1148#endif
1149 mtrr_aps_init();
1150}
1151
1152static int __initdata setup_possible_cpus = -1;
1153static int __init _setup_possible_cpus(char *str)
1154{
1155 get_option(&str, &setup_possible_cpus);
1156 return 0;
1157}
1158early_param("possible_cpus", _setup_possible_cpus);
1159
1160
1161/*
1162 * cpu_possible_mask should be static, it cannot change as cpu's
1163 * are onlined, or offlined. The reason is per-cpu data-structures
1164 * are allocated by some modules at init time, and dont expect to
1165 * do this dynamically on cpu arrival/departure.
1166 * cpu_present_mask on the other hand can change dynamically.
1167 * In case when cpu_hotplug is not compiled, then we resort to current
1168 * behaviour, which is cpu_possible == cpu_present.
1169 * - Ashok Raj
1170 *
1171 * Three ways to find out the number of additional hotplug CPUs:
1172 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1173 * - The user can overwrite it with possible_cpus=NUM
1174 * - Otherwise don't reserve additional CPUs.
1175 * We do this because additional CPUs waste a lot of memory.
1176 * -AK
1177 */
1178__init void prefill_possible_map(void)
1179{
1180 int i, possible;
1181
1182 /* no processor from mptable or madt */
1183 if (!num_processors)
1184 num_processors = 1;
1185
1186 i = setup_max_cpus ?: 1;
1187 if (setup_possible_cpus == -1) {
1188 possible = num_processors;
1189#ifdef CONFIG_HOTPLUG_CPU
1190 if (setup_max_cpus)
1191 possible += disabled_cpus;
1192#else
1193 if (possible > i)
1194 possible = i;
1195#endif
1196 } else
1197 possible = setup_possible_cpus;
1198
1199 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1200
1201 /* nr_cpu_ids could be reduced via nr_cpus= */
1202 if (possible > nr_cpu_ids) {
1203 printk(KERN_WARNING
1204 "%d Processors exceeds NR_CPUS limit of %d\n",
1205 possible, nr_cpu_ids);
1206 possible = nr_cpu_ids;
1207 }
1208
1209#ifdef CONFIG_HOTPLUG_CPU
1210 if (!setup_max_cpus)
1211#endif
1212 if (possible > i) {
1213 printk(KERN_WARNING
1214 "%d Processors exceeds max_cpus limit of %u\n",
1215 possible, setup_max_cpus);
1216 possible = i;
1217 }
1218
1219 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
1220 possible, max_t(int, possible - num_processors, 0));
1221
1222 for (i = 0; i < possible; i++)
1223 set_cpu_possible(i, true);
1224 for (; i < NR_CPUS; i++)
1225 set_cpu_possible(i, false);
1226
1227 nr_cpu_ids = possible;
1228}
1229
1230#ifdef CONFIG_HOTPLUG_CPU
1231
1232static void remove_siblinginfo(int cpu)
1233{
1234 int sibling;
1235 struct cpuinfo_x86 *c = &cpu_data(cpu);
1236
1237 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1238 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1239 /*/
1240 * last thread sibling in this cpu core going down
1241 */
1242 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1243 cpu_data(sibling).booted_cores--;
1244 }
1245
1246 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1247 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1248 cpumask_clear(cpu_sibling_mask(cpu));
1249 cpumask_clear(cpu_core_mask(cpu));
1250 c->phys_proc_id = 0;
1251 c->cpu_core_id = 0;
1252 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1253}
1254
1255static void __ref remove_cpu_from_maps(int cpu)
1256{
1257 set_cpu_online(cpu, false);
1258 cpumask_clear_cpu(cpu, cpu_callout_mask);
1259 cpumask_clear_cpu(cpu, cpu_callin_mask);
1260 /* was set by cpu_init() */
1261 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1262 numa_remove_cpu(cpu);
1263}
1264
1265void cpu_disable_common(void)
1266{
1267 int cpu = smp_processor_id();
1268
1269 remove_siblinginfo(cpu);
1270
1271 /* It's now safe to remove this processor from the online map */
1272 lock_vector_lock();
1273 remove_cpu_from_maps(cpu);
1274 unlock_vector_lock();
1275 fixup_irqs();
1276}
1277
1278int native_cpu_disable(void)
1279{
1280 int cpu = smp_processor_id();
1281
1282 /*
1283 * Perhaps use cpufreq to drop frequency, but that could go
1284 * into generic code.
1285 *
1286 * We won't take down the boot processor on i386 due to some
1287 * interrupts only being able to be serviced by the BSP.
1288 * Especially so if we're not using an IOAPIC -zwane
1289 */
1290 if (cpu == 0)
1291 return -EBUSY;
1292
1293 clear_local_APIC();
1294
1295 cpu_disable_common();
1296 return 0;
1297}
1298
1299void native_cpu_die(unsigned int cpu)
1300{
1301 /* We don't do anything here: idle task is faking death itself. */
1302 unsigned int i;
1303
1304 for (i = 0; i < 10; i++) {
1305 /* They ack this in play_dead by setting CPU_DEAD */
1306 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1307 if (system_state == SYSTEM_RUNNING)
1308 pr_info("CPU %u is now offline\n", cpu);
1309
1310 if (1 == num_online_cpus())
1311 alternatives_smp_switch(0);
1312 return;
1313 }
1314 msleep(100);
1315 }
1316 pr_err("CPU %u didn't die...\n", cpu);
1317}
1318
1319void play_dead_common(void)
1320{
1321 idle_task_exit();
1322 reset_lazy_tlbstate();
1323 amd_e400_remove_cpu(raw_smp_processor_id());
1324
1325 mb();
1326 /* Ack it */
1327 __this_cpu_write(cpu_state, CPU_DEAD);
1328
1329 /*
1330 * With physical CPU hotplug, we should halt the cpu
1331 */
1332 local_irq_disable();
1333}
1334
1335/*
1336 * We need to flush the caches before going to sleep, lest we have
1337 * dirty data in our caches when we come back up.
1338 */
1339static inline void mwait_play_dead(void)
1340{
1341 unsigned int eax, ebx, ecx, edx;
1342 unsigned int highest_cstate = 0;
1343 unsigned int highest_subcstate = 0;
1344 int i;
1345 void *mwait_ptr;
1346 struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info);
1347
1348 if (!(this_cpu_has(X86_FEATURE_MWAIT) && mwait_usable(c)))
1349 return;
1350 if (!this_cpu_has(X86_FEATURE_CLFLSH))
1351 return;
1352 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1353 return;
1354
1355 eax = CPUID_MWAIT_LEAF;
1356 ecx = 0;
1357 native_cpuid(&eax, &ebx, &ecx, &edx);
1358
1359 /*
1360 * eax will be 0 if EDX enumeration is not valid.
1361 * Initialized below to cstate, sub_cstate value when EDX is valid.
1362 */
1363 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1364 eax = 0;
1365 } else {
1366 edx >>= MWAIT_SUBSTATE_SIZE;
1367 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1368 if (edx & MWAIT_SUBSTATE_MASK) {
1369 highest_cstate = i;
1370 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1371 }
1372 }
1373 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1374 (highest_subcstate - 1);
1375 }
1376
1377 /*
1378 * This should be a memory location in a cache line which is
1379 * unlikely to be touched by other processors. The actual
1380 * content is immaterial as it is not actually modified in any way.
1381 */
1382 mwait_ptr = ¤t_thread_info()->flags;
1383
1384 wbinvd();
1385
1386 while (1) {
1387 /*
1388 * The CLFLUSH is a workaround for erratum AAI65 for
1389 * the Xeon 7400 series. It's not clear it is actually
1390 * needed, but it should be harmless in either case.
1391 * The WBINVD is insufficient due to the spurious-wakeup
1392 * case where we return around the loop.
1393 */
1394 clflush(mwait_ptr);
1395 __monitor(mwait_ptr, 0, 0);
1396 mb();
1397 __mwait(eax, 0);
1398 }
1399}
1400
1401static inline void hlt_play_dead(void)
1402{
1403 if (__this_cpu_read(cpu_info.x86) >= 4)
1404 wbinvd();
1405
1406 while (1) {
1407 native_halt();
1408 }
1409}
1410
1411void native_play_dead(void)
1412{
1413 play_dead_common();
1414 tboot_shutdown(TB_SHUTDOWN_WFS);
1415
1416 mwait_play_dead(); /* Only returns on failure */
1417 hlt_play_dead();
1418}
1419
1420#else /* ... !CONFIG_HOTPLUG_CPU */
1421int native_cpu_disable(void)
1422{
1423 return -ENOSYS;
1424}
1425
1426void native_cpu_die(unsigned int cpu)
1427{
1428 /* We said "no" in __cpu_disable */
1429 BUG();
1430}
1431
1432void native_play_dead(void)
1433{
1434 BUG();
1435}
1436
1437#endif