1/*
  2 * P4080DS Device Tree Source
  3 *
  4 * Copyright 2009-2011 Freescale Semiconductor Inc.
  5 *
  6 * Redistribution and use in source and binary forms, with or without
  7 * modification, are permitted provided that the following conditions are met:
  8 *     * Redistributions of source code must retain the above copyright
  9 *       notice, this list of conditions and the following disclaimer.
 10 *     * Redistributions in binary form must reproduce the above copyright
 11 *       notice, this list of conditions and the following disclaimer in the
 12 *       documentation and/or other materials provided with the distribution.
 13 *     * Neither the name of Freescale Semiconductor nor the
 14 *       names of its contributors may be used to endorse or promote products
 15 *       derived from this software without specific prior written permission.
 16 *
 17 *
 18 * ALTERNATIVELY, this software may be distributed under the terms of the
 19 * GNU General Public License ("GPL") as published by the Free Software
 20 * Foundation, either version 2 of that License or (at your option) any
 21 * later version.
 22 *
 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 33 */
 34
 35/include/ "p4080si.dtsi"
 36
 37/ {
 38	model = "fsl,P4080DS";
 39	compatible = "fsl,P4080DS";
 40	#address-cells = <2>;
 41	#size-cells = <2>;
 42	interrupt-parent = <&mpic>;
 43
 44	memory {
 45		device_type = "memory";
 46	};
 47
 48	soc: soc@ffe000000 {
 49		spi@110000 {
 50			flash@0 {
 51				#address-cells = <1>;
 52				#size-cells = <1>;
 53				compatible = "spansion,s25sl12801";
 54				reg = <0>;
 55				spi-max-frequency = <40000000>; /* input clock */
 56				partition@u-boot {
 57					label = "u-boot";
 58					reg = <0x00000000 0x00100000>;
 59					read-only;
 60				};
 61				partition@kernel {
 62					label = "kernel";
 63					reg = <0x00100000 0x00500000>;
 64					read-only;
 65				};
 66				partition@dtb {
 67					label = "dtb";
 68					reg = <0x00600000 0x00100000>;
 69					read-only;
 70				};
 71				partition@fs {
 72					label = "file system";
 73					reg = <0x00700000 0x00900000>;
 74				};
 75			};
 76		};
 77
 78		i2c@118100 {
 79			eeprom@51 {
 80				compatible = "at24,24c256";
 81				reg = <0x51>;
 82			};
 83			eeprom@52 {
 84				compatible = "at24,24c256";
 85				reg = <0x52>;
 86			};
 87			rtc@68 {
 88				compatible = "dallas,ds3232";
 89				reg = <0x68>;
 90				interrupts = <0x1 0x1 0 0>;
 91			};
 92		};
 93
 94		usb0: usb@210000 {
 95			phy_type = "ulpi";
 96		};
 97
 98		usb1: usb@211000 {
 99			dr_mode = "host";
100			phy_type = "ulpi";
101		};
102	};
103
104	rapidio0: rapidio@ffe0c0000 {
105		reg = <0xf 0xfe0c0000 0 0x20000>;
106		ranges = <0 0 0xc 0x20000000 0 0x01000000>;
107	};
108
109	localbus@ffe124000 {
110		reg = <0xf 0xfe124000 0 0x1000>;
111		ranges = <0 0 0xf 0xe8000000 0x08000000>;
112
113		flash@0,0 {
114			compatible = "cfi-flash";
115			reg = <0 0 0x08000000>;
116			bank-width = <2>;
117			device-width = <2>;
118		};
119	};
120
121	pci0: pcie@ffe200000 {
122		reg = <0xf 0xfe200000 0 0x1000>;
123		ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
124			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
125		pcie@0 {
126			ranges = <0x02000000 0 0xe0000000
127				  0x02000000 0 0xe0000000
128				  0 0x20000000
129
130				  0x01000000 0 0x00000000
131				  0x01000000 0 0x00000000
132				  0 0x00010000>;
133		};
134	};
135
136	pci1: pcie@ffe201000 {
137		reg = <0xf 0xfe201000 0 0x1000>;
138		ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
139			  0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
140		pcie@0 {
141			ranges = <0x02000000 0 0xe0000000
142				  0x02000000 0 0xe0000000
143				  0 0x20000000
144
145				  0x01000000 0 0x00000000
146				  0x01000000 0 0x00000000
147				  0 0x00010000>;
148		};
149	};
150
151	pci2: pcie@ffe202000 {
152		reg = <0xf 0xfe202000 0 0x1000>;
153		ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
154			  0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
155		pcie@0 {
156			ranges = <0x02000000 0 0xe0000000
157				  0x02000000 0 0xe0000000
158				  0 0x20000000
159
160				  0x01000000 0 0x00000000
161				  0x01000000 0 0x00000000
162				  0 0x00010000>;
163		};
164	};
165
166};