1/*
  2 * Copyright (C) 2013 Imagination Technologies
  3 * Author: Paul Burton <paul.burton@mips.com>
  4 *
  5 * This program is free software; you can redistribute it and/or modify it
  6 * under the terms of the GNU General Public License as published by the
  7 * Free Software Foundation;  either version 2 of the  License, or (at your
  8 * option) any later version.
  9 */
 10
 11#ifndef __MIPS_ASM_MIPS_CPS_H__
 12# error Please include asm/mips-cps.h rather than asm/mips-cpc.h
 13#endif
 14
 15#ifndef __MIPS_ASM_MIPS_CPC_H__
 16#define __MIPS_ASM_MIPS_CPC_H__
 17
 18#include <linux/bitops.h>
 19#include <linux/errno.h>
 20
 21/* The base address of the CPC registers */
 22extern void __iomem *mips_cpc_base;
 23
 24/**
 25 * mips_cpc_default_phys_base - retrieve the default physical base address of
 26 *                              the CPC
 27 *
 28 * Returns the default physical base address of the Cluster Power Controller
 29 * memory mapped registers. This is platform dependant & must therefore be
 30 * implemented per-platform.
 31 */
 32extern phys_addr_t mips_cpc_default_phys_base(void);
 33
 34/**
 35 * mips_cpc_probe - probe for a Cluster Power Controller
 36 *
 37 * Attempt to detect the presence of a Cluster Power Controller. Returns 0 if
 38 * a CPC is successfully detected, else -errno.
 39 */
 40#ifdef CONFIG_MIPS_CPC
 41extern int mips_cpc_probe(void);
 42#else
 43static inline int mips_cpc_probe(void)
 44{
 45	return -ENODEV;
 46}
 47#endif
 48
 49/**
 50 * mips_cpc_present - determine whether a Cluster Power Controller is present
 51 *
 52 * Returns true if a CPC is present in the system, else false.
 53 */
 54static inline bool mips_cpc_present(void)
 55{
 56#ifdef CONFIG_MIPS_CPC
 57	return mips_cpc_base != NULL;
 58#else
 59	return false;
 60#endif
 61}
 62
 63/* Offsets from the CPC base address to various control blocks */
 64#define MIPS_CPC_GCB_OFS	0x0000
 65#define MIPS_CPC_CLCB_OFS	0x2000
 66#define MIPS_CPC_COCB_OFS	0x4000
 67
 68#define CPC_ACCESSOR_RO(sz, off, name)					\
 69	CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_GCB_OFS + off, name)		\
 70	CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_COCB_OFS + off, redir_##name)
 71
 72#define CPC_ACCESSOR_RW(sz, off, name)					\
 73	CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_GCB_OFS + off, name)		\
 74	CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_COCB_OFS + off, redir_##name)
 75
 76#define CPC_CX_ACCESSOR_RO(sz, off, name)				\
 77	CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_CLCB_OFS + off, cl_##name)	\
 78	CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_COCB_OFS + off, co_##name)
 79
 80#define CPC_CX_ACCESSOR_RW(sz, off, name)				\
 81	CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_CLCB_OFS + off, cl_##name)	\
 82	CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_COCB_OFS + off, co_##name)
 83
 84/* CPC_ACCESS - Control core/IOCU access to CPC registers prior to CM 3 */
 85CPC_ACCESSOR_RW(32, 0x000, access)
 86
 87/* CPC_SEQDEL - Configure delays between command sequencer steps */
 88CPC_ACCESSOR_RW(32, 0x008, seqdel)
 89
 90/* CPC_RAIL - Configure the delay from rail power-up to stability */
 91CPC_ACCESSOR_RW(32, 0x010, rail)
 92
 93/* CPC_RESETLEN - Configure the length of reset sequences */
 94CPC_ACCESSOR_RW(32, 0x018, resetlen)
 95
 96/* CPC_REVISION - Indicates the revisison of the CPC */
 97CPC_ACCESSOR_RO(32, 0x020, revision)
 98
 99/* CPC_PWRUP_CTL - Control power to the Coherence Manager (CM) */
100CPC_ACCESSOR_RW(32, 0x030, pwrup_ctl)
101#define CPC_PWRUP_CTL_CM_PWRUP			BIT(0)
102
103/* CPC_CONFIG - Mirrors GCR_CONFIG */
104CPC_ACCESSOR_RW(64, 0x138, config)
105
106/* CPC_SYS_CONFIG - Control cluster endianness */
107CPC_ACCESSOR_RW(32, 0x140, sys_config)
108#define CPC_SYS_CONFIG_BE_IMMEDIATE		BIT(2)
109#define CPC_SYS_CONFIG_BE_STATUS		BIT(1)
110#define CPC_SYS_CONFIG_BE			BIT(0)
111
112/* CPC_Cx_CMD - Instruct the CPC to take action on a core */
113CPC_CX_ACCESSOR_RW(32, 0x000, cmd)
114#define CPC_Cx_CMD				GENMASK(3, 0)
115#define  CPC_Cx_CMD_CLOCKOFF			0x1
116#define  CPC_Cx_CMD_PWRDOWN			0x2
117#define  CPC_Cx_CMD_PWRUP			0x3
118#define  CPC_Cx_CMD_RESET			0x4
119
120/* CPC_Cx_STAT_CONF - Indicates core configuration & state */
121CPC_CX_ACCESSOR_RW(32, 0x008, stat_conf)
122#define CPC_Cx_STAT_CONF_PWRUPE			BIT(23)
123#define CPC_Cx_STAT_CONF_SEQSTATE		GENMASK(22, 19)
124#define  CPC_Cx_STAT_CONF_SEQSTATE_D0		0x0
125#define  CPC_Cx_STAT_CONF_SEQSTATE_U0		0x1
126#define  CPC_Cx_STAT_CONF_SEQSTATE_U1		0x2
127#define  CPC_Cx_STAT_CONF_SEQSTATE_U2		0x3
128#define  CPC_Cx_STAT_CONF_SEQSTATE_U3		0x4
129#define  CPC_Cx_STAT_CONF_SEQSTATE_U4		0x5
130#define  CPC_Cx_STAT_CONF_SEQSTATE_U5		0x6
131#define  CPC_Cx_STAT_CONF_SEQSTATE_U6		0x7
132#define  CPC_Cx_STAT_CONF_SEQSTATE_D1		0x8
133#define  CPC_Cx_STAT_CONF_SEQSTATE_D3		0x9
134#define  CPC_Cx_STAT_CONF_SEQSTATE_D2		0xa
135#define CPC_Cx_STAT_CONF_CLKGAT_IMPL		BIT(17)
136#define CPC_Cx_STAT_CONF_PWRDN_IMPL		BIT(16)
137#define CPC_Cx_STAT_CONF_EJTAG_PROBE		BIT(15)
138
139/* CPC_Cx_OTHER - Configure the core-other register block prior to CM 3 */
140CPC_CX_ACCESSOR_RW(32, 0x010, other)
141#define CPC_Cx_OTHER_CORENUM			GENMASK(23, 16)
142
143/* CPC_Cx_VP_STOP - Stop Virtual Processors (VPs) within a core from running */
144CPC_CX_ACCESSOR_RW(32, 0x020, vp_stop)
145
146/* CPC_Cx_VP_START - Start Virtual Processors (VPs) within a core running */
147CPC_CX_ACCESSOR_RW(32, 0x028, vp_run)
148
149/* CPC_Cx_VP_RUNNING - Indicate which Virtual Processors (VPs) are running */
150CPC_CX_ACCESSOR_RW(32, 0x030, vp_running)
151
152/* CPC_Cx_CONFIG - Mirrors GCR_Cx_CONFIG */
153CPC_CX_ACCESSOR_RW(32, 0x090, config)
154
155#ifdef CONFIG_MIPS_CPC
156
157/**
158 * mips_cpc_lock_other - lock access to another core
159 * core: the other core to be accessed
160 *
161 * Call before operating upon a core via the 'other' register region in
162 * order to prevent the region being moved during access. Must be called
163 * within the bounds of a mips_cm_{lock,unlock}_other pair, and followed
164 * by a call to mips_cpc_unlock_other.
165 */
166extern void mips_cpc_lock_other(unsigned int core);
167
168/**
169 * mips_cpc_unlock_other - unlock access to another core
170 *
171 * Call after operating upon another core via the 'other' register region.
172 * Must be called after mips_cpc_lock_other.
173 */
174extern void mips_cpc_unlock_other(void);
175
176#else /* !CONFIG_MIPS_CPC */
177
178static inline void mips_cpc_lock_other(unsigned int core) { }
179static inline void mips_cpc_unlock_other(void) { }
180
181#endif /* !CONFIG_MIPS_CPC */
182
183#endif /* __MIPS_ASM_MIPS_CPC_H__ */