1/*
  2 *  DaVinci Power & Sleep Controller (PSC) defines
  3 *
  4 *  Copyright (C) 2006 Texas Instruments.
  5 *
  6 *  This program is free software; you can redistribute  it and/or modify it
  7 *  under  the terms of  the GNU General  Public License as published by the
  8 *  Free Software Foundation;  either version 2 of the  License, or (at your
  9 *  option) any later version.
 10 *
 11 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 12 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 13 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 14 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 15 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 16 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 17 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 18 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 19 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 20 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 21 *
 22 *  You should have received a copy of the  GNU General Public License along
 23 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 24 *  675 Mass Ave, Cambridge, MA 02139, USA.
 25 *
 26 */
 27#ifndef __ASM_ARCH_PSC_H
 28#define __ASM_ARCH_PSC_H
 29
 30#define	DAVINCI_PWR_SLEEP_CNTRL_BASE	0x01C41000
 31
 32/* Power and Sleep Controller (PSC) Domains */
 33#define DAVINCI_GPSC_ARMDOMAIN		0
 34#define DAVINCI_GPSC_DSPDOMAIN		1
 35
 36#define DAVINCI_LPSC_VPSSMSTR		0
 37#define DAVINCI_LPSC_VPSSSLV		1
 38#define DAVINCI_LPSC_TPCC		2
 39#define DAVINCI_LPSC_TPTC0		3
 40#define DAVINCI_LPSC_TPTC1		4
 41#define DAVINCI_LPSC_EMAC		5
 42#define DAVINCI_LPSC_EMAC_WRAPPER	6
 43#define DAVINCI_LPSC_USB		9
 44#define DAVINCI_LPSC_ATA		10
 45#define DAVINCI_LPSC_VLYNQ		11
 46#define DAVINCI_LPSC_UHPI		12
 47#define DAVINCI_LPSC_DDR_EMIF		13
 48#define DAVINCI_LPSC_AEMIF		14
 49#define DAVINCI_LPSC_MMC_SD		15
 50#define DAVINCI_LPSC_McBSP		17
 51#define DAVINCI_LPSC_I2C		18
 52#define DAVINCI_LPSC_UART0		19
 53#define DAVINCI_LPSC_UART1		20
 54#define DAVINCI_LPSC_UART2		21
 55#define DAVINCI_LPSC_SPI		22
 56#define DAVINCI_LPSC_PWM0		23
 57#define DAVINCI_LPSC_PWM1		24
 58#define DAVINCI_LPSC_PWM2		25
 59#define DAVINCI_LPSC_GPIO		26
 60#define DAVINCI_LPSC_TIMER0		27
 61#define DAVINCI_LPSC_TIMER1		28
 62#define DAVINCI_LPSC_TIMER2		29
 63#define DAVINCI_LPSC_SYSTEM_SUBSYS	30
 64#define DAVINCI_LPSC_ARM		31
 65#define DAVINCI_LPSC_SCR2		32
 66#define DAVINCI_LPSC_SCR3		33
 67#define DAVINCI_LPSC_SCR4		34
 68#define DAVINCI_LPSC_CROSSBAR		35
 69#define DAVINCI_LPSC_CFG27		36
 70#define DAVINCI_LPSC_CFG3		37
 71#define DAVINCI_LPSC_CFG5		38
 72#define DAVINCI_LPSC_GEM		39
 73#define DAVINCI_LPSC_IMCOP		40
 74
 75#define DM355_LPSC_TIMER3		5
 76#define DM355_LPSC_SPI1			6
 77#define DM355_LPSC_MMC_SD1		7
 78#define DM355_LPSC_McBSP1		8
 79#define DM355_LPSC_PWM3			10
 80#define DM355_LPSC_SPI2			11
 81#define DM355_LPSC_RTO			12
 82#define DM355_LPSC_VPSS_DAC		41
 83
 84/* DM365 */
 85#define DM365_LPSC_TIMER3	5
 86#define DM365_LPSC_SPI1		6
 87#define DM365_LPSC_MMC_SD1	7
 88#define DM365_LPSC_McBSP1	8
 89#define DM365_LPSC_PWM3		10
 90#define DM365_LPSC_SPI2		11
 91#define DM365_LPSC_RTO		12
 92#define DM365_LPSC_TIMER4	17
 93#define DM365_LPSC_SPI0		22
 94#define DM365_LPSC_SPI3		38
 95#define DM365_LPSC_SPI4		39
 96#define DM365_LPSC_EMAC		40
 97#define DM365_LPSC_VOICE_CODEC	44
 98#define DM365_LPSC_DAC_CLK	46
 99#define DM365_LPSC_VPSSMSTR	47
100#define DM365_LPSC_MJCP		50
101
102/*
103 * LPSC Assignments
104 */
105#define DM646X_LPSC_ARM		0
106#define DM646X_LPSC_C64X_CPU	1
107#define DM646X_LPSC_HDVICP0	2
108#define DM646X_LPSC_HDVICP1	3
109#define DM646X_LPSC_TPCC	4
110#define DM646X_LPSC_TPTC0	5
111#define DM646X_LPSC_TPTC1	6
112#define DM646X_LPSC_TPTC2	7
113#define DM646X_LPSC_TPTC3	8
114#define DM646X_LPSC_PCI		13
115#define DM646X_LPSC_EMAC	14
116#define DM646X_LPSC_VDCE	15
117#define DM646X_LPSC_VPSSMSTR	16
118#define DM646X_LPSC_VPSSSLV	17
119#define DM646X_LPSC_TSIF0	18
120#define DM646X_LPSC_TSIF1	19
121#define DM646X_LPSC_DDR_EMIF	20
122#define DM646X_LPSC_AEMIF	21
123#define DM646X_LPSC_McASP0	22
124#define DM646X_LPSC_McASP1	23
125#define DM646X_LPSC_CRGEN0	24
126#define DM646X_LPSC_CRGEN1	25
127#define DM646X_LPSC_UART0	26
128#define DM646X_LPSC_UART1	27
129#define DM646X_LPSC_UART2	28
130#define DM646X_LPSC_PWM0	29
131#define DM646X_LPSC_PWM1	30
132#define DM646X_LPSC_I2C		31
133#define DM646X_LPSC_SPI		32
134#define DM646X_LPSC_GPIO	33
135#define DM646X_LPSC_TIMER0	34
136#define DM646X_LPSC_TIMER1	35
137#define DM646X_LPSC_ARM_INTC	45
138
139/* PSC0 defines */
140#define DA8XX_LPSC0_TPCC		0
141#define DA8XX_LPSC0_TPTC0		1
142#define DA8XX_LPSC0_TPTC1		2
143#define DA8XX_LPSC0_EMIF25		3
144#define DA8XX_LPSC0_SPI0		4
145#define DA8XX_LPSC0_MMC_SD		5
146#define DA8XX_LPSC0_AINTC		6
147#define DA8XX_LPSC0_ARM_RAM_ROM		7
148#define DA8XX_LPSC0_SECU_MGR		8
149#define DA8XX_LPSC0_UART0		9
150#define DA8XX_LPSC0_SCR0_SS		10
151#define DA8XX_LPSC0_SCR1_SS		11
152#define DA8XX_LPSC0_SCR2_SS		12
153#define DA8XX_LPSC0_PRUSS		13
154#define DA8XX_LPSC0_ARM			14
155#define DA8XX_LPSC0_GEM			15
156
157/* PSC1 defines */
158#define DA850_LPSC1_TPCC1		0
159#define DA8XX_LPSC1_USB20		1
160#define DA8XX_LPSC1_USB11		2
161#define DA8XX_LPSC1_GPIO		3
162#define DA8XX_LPSC1_UHPI		4
163#define DA8XX_LPSC1_CPGMAC		5
164#define DA8XX_LPSC1_EMIF3C		6
165#define DA8XX_LPSC1_McASP0		7
166#define DA830_LPSC1_McASP1		8
167#define DA850_LPSC1_SATA		8
168#define DA830_LPSC1_McASP2		9
169#define DA850_LPSC1_VPIF		9
170#define DA8XX_LPSC1_SPI1		10
171#define DA8XX_LPSC1_I2C			11
172#define DA8XX_LPSC1_UART1		12
173#define DA8XX_LPSC1_UART2		13
174#define DA850_LPSC1_McBSP0		14
175#define DA850_LPSC1_McBSP1		15
176#define DA8XX_LPSC1_LCDC		16
177#define DA8XX_LPSC1_PWM			17
178#define DA850_LPSC1_MMC_SD1		18
179#define DA8XX_LPSC1_ECAP		20
180#define DA830_LPSC1_EQEP		21
181#define DA850_LPSC1_TPTC2		21
182#define DA8XX_LPSC1_SCR_P0_SS		24
183#define DA8XX_LPSC1_SCR_P1_SS		25
184#define DA8XX_LPSC1_CR_P3_SS		26
185#define DA8XX_LPSC1_L3_CBA_RAM		31
186
187/* PSC register offsets */
188#define EPCPR		0x070
189#define PTCMD		0x120
190#define PTSTAT		0x128
191#define PDSTAT		0x200
192#define PDCTL		0x300
193#define MDSTAT		0x800
194#define MDCTL		0xA00
195
196/* PSC module states */
197#define PSC_STATE_SWRSTDISABLE	0
198#define PSC_STATE_SYNCRST	1
199#define PSC_STATE_DISABLE	2
200#define PSC_STATE_ENABLE	3
201
202#define MDSTAT_STATE_MASK	0x3f
203#define PDSTAT_STATE_MASK	0x1f
204#define MDCTL_LRST		BIT(8)
205#define MDCTL_FORCE		BIT(31)
206#define PDCTL_NEXT		BIT(0)
207#define PDCTL_EPCGOOD		BIT(8)
208
209#ifndef __ASSEMBLER__
210
211extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
212extern void davinci_psc_reset(unsigned int ctlr, unsigned int id,
213		bool reset);
214extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
215		unsigned int id, bool enable, u32 flags);
216
217#endif
218
219#endif /* __ASM_ARCH_PSC_H */