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1/*
2 * TI DaVinci clock definitions
3 *
4 * Copyright (C) 2006-2007 Texas Instruments.
5 * Copyright (C) 2008-2009 Deep Root Systems, LLC
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __ARCH_ARM_DAVINCI_CLOCK_H
13#define __ARCH_ARM_DAVINCI_CLOCK_H
14
15#define DAVINCI_PLL1_BASE 0x01c40800
16#define DAVINCI_PLL2_BASE 0x01c40c00
17#define MAX_PLL 2
18
19/* PLL/Reset register offsets */
20#define PLLCTL 0x100
21#define PLLCTL_PLLEN BIT(0)
22#define PLLCTL_PLLPWRDN BIT(1)
23#define PLLCTL_PLLRST BIT(3)
24#define PLLCTL_PLLDIS BIT(4)
25#define PLLCTL_PLLENSRC BIT(5)
26#define PLLCTL_CLKMODE BIT(8)
27
28#define PLLM 0x110
29#define PLLM_PLLM_MASK 0xff
30
31#define PREDIV 0x114
32#define PLLDIV1 0x118
33#define PLLDIV2 0x11c
34#define PLLDIV3 0x120
35#define POSTDIV 0x128
36#define BPDIV 0x12c
37#define PLLCMD 0x138
38#define PLLSTAT 0x13c
39#define PLLALNCTL 0x140
40#define PLLDCHANGE 0x144
41#define PLLCKEN 0x148
42#define PLLCKSTAT 0x14c
43#define PLLSYSTAT 0x150
44#define PLLDIV4 0x160
45#define PLLDIV5 0x164
46#define PLLDIV6 0x168
47#define PLLDIV7 0x16c
48#define PLLDIV8 0x170
49#define PLLDIV9 0x174
50#define PLLDIV_EN BIT(15)
51#define PLLDIV_RATIO_MASK 0x1f
52
53/*
54 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
55 * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
56 * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input
57 * is ~25MHz. Units are micro seconds.
58 */
59#define PLL_BYPASS_TIME 1
60/* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
61#define PLL_RESET_TIME 1
62/*
63 * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
64 * Units are micro seconds.
65 */
66#define PLL_LOCK_TIME 20
67
68#ifndef __ASSEMBLER__
69
70#include <linux/list.h>
71#include <linux/clkdev.h>
72
73#define PLLSTAT_GOSTAT BIT(0)
74#define PLLCMD_GOSET BIT(0)
75
76struct pll_data {
77 u32 phys_base;
78 void __iomem *base;
79 u32 num;
80 u32 flags;
81 u32 input_rate;
82 u32 div_ratio_mask;
83};
84#define PLL_HAS_PREDIV 0x01
85#define PLL_HAS_POSTDIV 0x02
86
87struct clk {
88 struct list_head node;
89 struct module *owner;
90 const char *name;
91 unsigned long rate;
92 unsigned long maxrate; /* H/W supported max rate */
93 u8 usecount;
94 u8 lpsc;
95 u8 gpsc;
96 u8 domain;
97 u32 flags;
98 struct clk *parent;
99 struct list_head children; /* list of children */
100 struct list_head childnode; /* parent's child list node */
101 struct pll_data *pll_data;
102 u32 div_reg;
103 unsigned long (*recalc) (struct clk *);
104 int (*set_rate) (struct clk *clk, unsigned long rate);
105 int (*round_rate) (struct clk *clk, unsigned long rate);
106 int (*reset) (struct clk *clk, bool reset);
107 void (*clk_enable) (struct clk *clk);
108 void (*clk_disable) (struct clk *clk);
109 int (*set_parent) (struct clk *clk, struct clk *parent);
110};
111
112/* Clock flags: SoC-specific flags start at BIT(16) */
113#define ALWAYS_ENABLED BIT(1)
114#define CLK_PSC BIT(2)
115#define CLK_PLL BIT(3) /* PLL-derived clock */
116#define PRE_PLL BIT(4) /* source is before PLL mult/div */
117#define PSC_SWRSTDISABLE BIT(5) /* Disable state is SwRstDisable */
118#define PSC_FORCE BIT(6) /* Force module state transtition */
119#define PSC_LRST BIT(8) /* Use local reset on enable/disable */
120
121#define CLK(dev, con, ck) \
122 { \
123 .dev_id = dev, \
124 .con_id = con, \
125 .clk = ck, \
126 } \
127
128int davinci_clk_init(struct clk_lookup *clocks);
129int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
130 unsigned int mult, unsigned int postdiv);
131int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate);
132int davinci_set_refclk_rate(unsigned long rate);
133int davinci_simple_set_rate(struct clk *clk, unsigned long rate);
134int davinci_clk_reset(struct clk *clk, bool reset);
135void davinci_clk_enable(struct clk *clk);
136void davinci_clk_disable(struct clk *clk);
137
138#endif
139
140#endif
1/*
2 * TI DaVinci clock definitions
3 *
4 * Copyright (C) 2006-2007 Texas Instruments.
5 * Copyright (C) 2008-2009 Deep Root Systems, LLC
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __ARCH_ARM_DAVINCI_CLOCK_H
13#define __ARCH_ARM_DAVINCI_CLOCK_H
14
15#define DAVINCI_PLL1_BASE 0x01c40800
16#define DAVINCI_PLL2_BASE 0x01c40c00
17#define MAX_PLL 2
18
19/* PLL/Reset register offsets */
20#define PLLCTL 0x100
21#define PLLCTL_PLLEN BIT(0)
22#define PLLCTL_PLLPWRDN BIT(1)
23#define PLLCTL_PLLRST BIT(3)
24#define PLLCTL_PLLDIS BIT(4)
25#define PLLCTL_PLLENSRC BIT(5)
26#define PLLCTL_CLKMODE BIT(8)
27
28#define PLLM 0x110
29#define PLLM_PLLM_MASK 0xff
30
31#define PREDIV 0x114
32#define PLLDIV1 0x118
33#define PLLDIV2 0x11c
34#define PLLDIV3 0x120
35#define POSTDIV 0x128
36#define BPDIV 0x12c
37#define PLLCMD 0x138
38#define PLLSTAT 0x13c
39#define PLLALNCTL 0x140
40#define PLLDCHANGE 0x144
41#define PLLCKEN 0x148
42#define PLLCKSTAT 0x14c
43#define PLLSYSTAT 0x150
44#define PLLDIV4 0x160
45#define PLLDIV5 0x164
46#define PLLDIV6 0x168
47#define PLLDIV7 0x16c
48#define PLLDIV8 0x170
49#define PLLDIV9 0x174
50#define PLLDIV_EN BIT(15)
51#define PLLDIV_RATIO_MASK 0x1f
52
53/*
54 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
55 * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
56 * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input
57 * is ~25MHz. Units are micro seconds.
58 */
59#define PLL_BYPASS_TIME 1
60/* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
61#define PLL_RESET_TIME 1
62/*
63 * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
64 * Units are micro seconds.
65 */
66#define PLL_LOCK_TIME 20
67
68#ifndef __ASSEMBLER__
69
70#include <linux/list.h>
71#include <linux/clkdev.h>
72
73#define PLLSTAT_GOSTAT BIT(0)
74#define PLLCMD_GOSET BIT(0)
75
76struct pll_data {
77 u32 phys_base;
78 void __iomem *base;
79 u32 num;
80 u32 flags;
81 u32 input_rate;
82 u32 div_ratio_mask;
83};
84#define PLL_HAS_PREDIV 0x01
85#define PLL_HAS_POSTDIV 0x02
86
87struct clk {
88 struct list_head node;
89 struct module *owner;
90 const char *name;
91 unsigned long rate;
92 unsigned long maxrate; /* H/W supported max rate */
93 u8 usecount;
94 u8 lpsc;
95 u8 gpsc;
96 u32 flags;
97 struct clk *parent;
98 struct list_head children; /* list of children */
99 struct list_head childnode; /* parent's child list node */
100 struct pll_data *pll_data;
101 u32 div_reg;
102 unsigned long (*recalc) (struct clk *);
103 int (*set_rate) (struct clk *clk, unsigned long rate);
104 int (*round_rate) (struct clk *clk, unsigned long rate);
105};
106
107/* Clock flags: SoC-specific flags start at BIT(16) */
108#define ALWAYS_ENABLED BIT(1)
109#define CLK_PSC BIT(2)
110#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */
111#define CLK_PLL BIT(4) /* PLL-derived clock */
112#define PRE_PLL BIT(5) /* source is before PLL mult/div */
113#define PSC_SWRSTDISABLE BIT(6) /* Disable state is SwRstDisable */
114#define PSC_FORCE BIT(7) /* Force module state transtition */
115
116#define CLK(dev, con, ck) \
117 { \
118 .dev_id = dev, \
119 .con_id = con, \
120 .clk = ck, \
121 } \
122
123int davinci_clk_init(struct clk_lookup *clocks);
124int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
125 unsigned int mult, unsigned int postdiv);
126int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate);
127int davinci_set_refclk_rate(unsigned long rate);
128int davinci_simple_set_rate(struct clk *clk, unsigned long rate);
129
130extern struct platform_device davinci_wdt_device;
131extern void davinci_watchdog_reset(struct platform_device *);
132
133#endif
134
135#endif