Loading...
1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3/include/ "skeleton.dtsi"
4
5/ {
6 model = "ARM Versatile AB";
7 compatible = "arm,versatile-ab";
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&vic>;
11
12 aliases {
13 serial0 = &uart0;
14 serial1 = &uart1;
15 serial2 = &uart2;
16 i2c0 = &i2c0;
17 };
18
19 chosen {
20 stdout-path = &uart0;
21 };
22
23 memory {
24 reg = <0x0 0x08000000>;
25 };
26
27 xtal24mhz: xtal24mhz@24M {
28 #clock-cells = <0>;
29 compatible = "fixed-clock";
30 clock-frequency = <24000000>;
31 };
32
33 bridge {
34 compatible = "ti,ths8134b", "ti,ths8134";
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 ports {
39 #address-cells = <1>;
40 #size-cells = <0>;
41
42 port@0 {
43 reg = <0>;
44
45 vga_bridge_in: endpoint {
46 remote-endpoint = <&clcd_pads_vga_dac>;
47 };
48 };
49
50 port@1 {
51 reg = <1>;
52
53 vga_bridge_out: endpoint {
54 remote-endpoint = <&vga_con_in>;
55 };
56 };
57 };
58 };
59
60 vga {
61 compatible = "vga-connector";
62
63 port {
64 vga_con_in: endpoint {
65 remote-endpoint = <&vga_bridge_out>;
66 };
67 };
68 };
69
70 core-module@10000000 {
71 compatible = "arm,core-module-versatile", "syscon", "simple-mfd";
72 reg = <0x10000000 0x200>;
73
74 led@08.0 {
75 compatible = "register-bit-led";
76 offset = <0x08>;
77 mask = <0x01>;
78 label = "versatile:0";
79 linux,default-trigger = "heartbeat";
80 default-state = "on";
81 };
82 led@08.1 {
83 compatible = "register-bit-led";
84 offset = <0x08>;
85 mask = <0x02>;
86 label = "versatile:1";
87 linux,default-trigger = "mmc0";
88 default-state = "off";
89 };
90 led@08.2 {
91 compatible = "register-bit-led";
92 offset = <0x08>;
93 mask = <0x04>;
94 label = "versatile:2";
95 linux,default-trigger = "cpu0";
96 default-state = "off";
97 };
98 led@08.3 {
99 compatible = "register-bit-led";
100 offset = <0x08>;
101 mask = <0x08>;
102 label = "versatile:3";
103 default-state = "off";
104 };
105 led@08.4 {
106 compatible = "register-bit-led";
107 offset = <0x08>;
108 mask = <0x10>;
109 label = "versatile:4";
110 default-state = "off";
111 };
112 led@08.5 {
113 compatible = "register-bit-led";
114 offset = <0x08>;
115 mask = <0x20>;
116 label = "versatile:5";
117 default-state = "off";
118 };
119 led@08.6 {
120 compatible = "register-bit-led";
121 offset = <0x08>;
122 mask = <0x40>;
123 label = "versatile:6";
124 default-state = "off";
125 };
126 led@08.7 {
127 compatible = "register-bit-led";
128 offset = <0x08>;
129 mask = <0x80>;
130 label = "versatile:7";
131 default-state = "off";
132 };
133
134 /* OSC1 on AB, OSC4 on PB */
135 osc1: cm_aux_osc@24M {
136 #clock-cells = <0>;
137 compatible = "arm,versatile-cm-auxosc";
138 clocks = <&xtal24mhz>;
139 };
140
141 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
142 timclk: timclk@1M {
143 #clock-cells = <0>;
144 compatible = "fixed-factor-clock";
145 clock-div = <24>;
146 clock-mult = <1>;
147 clocks = <&xtal24mhz>;
148 };
149
150 pclk: pclk@24M {
151 #clock-cells = <0>;
152 compatible = "fixed-factor-clock";
153 clock-div = <1>;
154 clock-mult = <1>;
155 clocks = <&xtal24mhz>;
156 };
157 };
158
159 flash@34000000 {
160 /* 64 MiB NOR flash in non-interleaved chips */
161 compatible = "arm,versatile-flash", "cfi-flash";
162 reg = <0x34000000 0x04000000>;
163 bank-width = <4>;
164 };
165
166 i2c0: i2c@10002000 {
167 #address-cells = <1>;
168 #size-cells = <0>;
169 compatible = "arm,versatile-i2c";
170 reg = <0x10002000 0x1000>;
171
172 rtc@68 {
173 compatible = "dallas,ds1338";
174 reg = <0x68>;
175 };
176 };
177
178 net@10010000 {
179 compatible = "smsc,lan91c111";
180 reg = <0x10010000 0x10000>;
181 interrupts = <25>;
182 };
183
184 lcd@10008000 {
185 compatible = "arm,versatile-lcd";
186 reg = <0x10008000 0x1000>;
187 };
188
189 amba {
190 compatible = "simple-bus";
191 #address-cells = <1>;
192 #size-cells = <1>;
193 ranges;
194
195 vic: intc@10140000 {
196 compatible = "arm,versatile-vic";
197 interrupt-controller;
198 #interrupt-cells = <1>;
199 reg = <0x10140000 0x1000>;
200 clear-mask = <0xffffffff>;
201 valid-mask = <0xffffffff>;
202 };
203
204 sic: intc@10003000 {
205 compatible = "arm,versatile-sic";
206 interrupt-controller;
207 #interrupt-cells = <1>;
208 reg = <0x10003000 0x1000>;
209 interrupt-parent = <&vic>;
210 interrupts = <31>; /* Cascaded to vic */
211 clear-mask = <0xffffffff>;
212 /*
213 * Valid interrupt lines mask according to
214 * table 4-36 page 4-50 of ARM DUI 0225D
215 */
216 valid-mask = <0x0760031b>;
217 };
218
219 dma@10130000 {
220 compatible = "arm,pl081", "arm,primecell";
221 reg = <0x10130000 0x1000>;
222 interrupts = <17>;
223 clocks = <&pclk>;
224 clock-names = "apb_pclk";
225 };
226
227 uart0: uart@101f1000 {
228 compatible = "arm,pl011", "arm,primecell";
229 reg = <0x101f1000 0x1000>;
230 interrupts = <12>;
231 clocks = <&xtal24mhz>, <&pclk>;
232 clock-names = "uartclk", "apb_pclk";
233 };
234
235 uart1: uart@101f2000 {
236 compatible = "arm,pl011", "arm,primecell";
237 reg = <0x101f2000 0x1000>;
238 interrupts = <13>;
239 clocks = <&xtal24mhz>, <&pclk>;
240 clock-names = "uartclk", "apb_pclk";
241 };
242
243 uart2: uart@101f3000 {
244 compatible = "arm,pl011", "arm,primecell";
245 reg = <0x101f3000 0x1000>;
246 interrupts = <14>;
247 clocks = <&xtal24mhz>, <&pclk>;
248 clock-names = "uartclk", "apb_pclk";
249 };
250
251 smc@10100000 {
252 compatible = "arm,primecell";
253 reg = <0x10100000 0x1000>;
254 clocks = <&pclk>;
255 clock-names = "apb_pclk";
256 };
257
258 mpmc@10110000 {
259 compatible = "arm,primecell";
260 reg = <0x10110000 0x1000>;
261 clocks = <&pclk>;
262 clock-names = "apb_pclk";
263 };
264
265 display@10120000 {
266 compatible = "arm,pl110", "arm,primecell";
267 reg = <0x10120000 0x1000>;
268 interrupts = <16>;
269 clocks = <&osc1>, <&pclk>;
270 clock-names = "clcdclk", "apb_pclk";
271 /* 800x600 16bpp @ 36MHz works fine */
272 max-memory-bandwidth = <54000000>;
273
274 /*
275 * This port is routed through a PLD (Programmable
276 * Logic Device) that routes the output from the CLCD
277 * (after transformations) to the VGA DAC and also an
278 * external panel connector. The PLD is essential for
279 * supporting RGB565/BGR565.
280 *
281 * The signals from the port thus reaches two endpoints.
282 * The PLD is managed through a few special bits in the
283 * FPGA "sysreg".
284 *
285 * This arrangement can be clearly seen in
286 * ARM DUI 0225D, page 3-41, figure 3-19.
287 */
288 port@0 {
289 #address-cells = <1>;
290 #size-cells = <0>;
291
292 clcd_pads_panel: endpoint@0 {
293 reg = <0>;
294 remote-endpoint = <&panel_in>;
295 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
296 };
297 clcd_pads_vga_dac: endpoint@1 {
298 reg = <1>;
299 remote-endpoint = <&vga_bridge_in>;
300 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
301 };
302 };
303 };
304
305 sctl@101e0000 {
306 compatible = "arm,primecell";
307 reg = <0x101e0000 0x1000>;
308 clocks = <&pclk>;
309 clock-names = "apb_pclk";
310 };
311
312 watchdog@101e1000 {
313 compatible = "arm,primecell";
314 reg = <0x101e1000 0x1000>;
315 interrupts = <0>;
316 clocks = <&pclk>;
317 clock-names = "apb_pclk";
318 };
319
320 timer@101e2000 {
321 compatible = "arm,sp804", "arm,primecell";
322 reg = <0x101e2000 0x1000>;
323 interrupts = <4>;
324 clocks = <&timclk>, <&timclk>, <&pclk>;
325 clock-names = "timer0", "timer1", "apb_pclk";
326 };
327
328 timer@101e3000 {
329 compatible = "arm,sp804", "arm,primecell";
330 reg = <0x101e3000 0x1000>;
331 interrupts = <5>;
332 clocks = <&timclk>, <&timclk>, <&pclk>;
333 clock-names = "timer0", "timer1", "apb_pclk";
334 };
335
336 gpio0: gpio@101e4000 {
337 compatible = "arm,pl061", "arm,primecell";
338 reg = <0x101e4000 0x1000>;
339 gpio-controller;
340 interrupts = <6>;
341 #gpio-cells = <2>;
342 interrupt-controller;
343 #interrupt-cells = <2>;
344 clocks = <&pclk>;
345 clock-names = "apb_pclk";
346 };
347
348 gpio1: gpio@101e5000 {
349 compatible = "arm,pl061", "arm,primecell";
350 reg = <0x101e5000 0x1000>;
351 interrupts = <7>;
352 gpio-controller;
353 #gpio-cells = <2>;
354 interrupt-controller;
355 #interrupt-cells = <2>;
356 clocks = <&pclk>;
357 clock-names = "apb_pclk";
358 };
359
360 rtc@101e8000 {
361 compatible = "arm,pl030", "arm,primecell";
362 reg = <0x101e8000 0x1000>;
363 interrupts = <10>;
364 clocks = <&pclk>;
365 clock-names = "apb_pclk";
366 };
367
368 sci@101f0000 {
369 compatible = "arm,primecell";
370 reg = <0x101f0000 0x1000>;
371 interrupts = <15>;
372 clocks = <&pclk>;
373 clock-names = "apb_pclk";
374 };
375
376 ssp@101f4000 {
377 compatible = "arm,pl022", "arm,primecell";
378 reg = <0x101f4000 0x1000>;
379 interrupts = <11>;
380 clocks = <&xtal24mhz>, <&pclk>;
381 clock-names = "SSPCLK", "apb_pclk";
382 };
383
384 fpga {
385 compatible = "arm,versatile-fpga", "simple-bus";
386 #address-cells = <1>;
387 #size-cells = <1>;
388 ranges = <0 0x10000000 0x10000>;
389
390 sysreg@0 {
391 compatible = "arm,versatile-sysreg", "syscon", "simple-mfd";
392 reg = <0x00000 0x1000>;
393
394 panel: display@0 {
395 compatible = "arm,versatile-tft-panel";
396
397 port {
398 panel_in: endpoint {
399 remote-endpoint = <&clcd_pads_panel>;
400 };
401 };
402 };
403 };
404
405 aaci@4000 {
406 compatible = "arm,primecell";
407 reg = <0x4000 0x1000>;
408 interrupts = <24>;
409 clocks = <&pclk>;
410 clock-names = "apb_pclk";
411 };
412 mmc@5000 {
413 compatible = "arm,pl180", "arm,primecell";
414 reg = <0x5000 0x1000>;
415 interrupts-extended = <&vic 22 &sic 1>;
416 clocks = <&xtal24mhz>, <&pclk>;
417 clock-names = "mclk", "apb_pclk";
418 };
419 kmi@6000 {
420 compatible = "arm,pl050", "arm,primecell";
421 reg = <0x6000 0x1000>;
422 interrupt-parent = <&sic>;
423 interrupts = <3>;
424 clocks = <&xtal24mhz>, <&pclk>;
425 clock-names = "KMIREFCLK", "apb_pclk";
426 };
427 kmi@7000 {
428 compatible = "arm,pl050", "arm,primecell";
429 reg = <0x7000 0x1000>;
430 interrupt-parent = <&sic>;
431 interrupts = <4>;
432 clocks = <&xtal24mhz>, <&pclk>;
433 clock-names = "KMIREFCLK", "apb_pclk";
434 };
435 };
436 };
437};
1/dts-v1/;
2/include/ "skeleton.dtsi"
3
4/ {
5 model = "ARM Versatile AB";
6 compatible = "arm,versatile-ab";
7 #address-cells = <1>;
8 #size-cells = <1>;
9 interrupt-parent = <&vic>;
10
11 aliases {
12 serial0 = &uart0;
13 serial1 = &uart1;
14 serial2 = &uart2;
15 i2c0 = &i2c0;
16 };
17
18 memory {
19 reg = <0x0 0x08000000>;
20 };
21
22 flash@34000000 {
23 compatible = "arm,versatile-flash";
24 reg = <0x34000000 0x4000000>;
25 bank-width = <4>;
26 };
27
28 i2c0: i2c@10002000 {
29 #address-cells = <1>;
30 #size-cells = <0>;
31 compatible = "arm,versatile-i2c";
32 reg = <0x10002000 0x1000>;
33
34 rtc@68 {
35 compatible = "dallas,ds1338";
36 reg = <0x68>;
37 };
38 };
39
40 net@10010000 {
41 compatible = "smsc,lan91c111";
42 reg = <0x10010000 0x10000>;
43 interrupts = <25>;
44 };
45
46 lcd@10008000 {
47 compatible = "arm,versatile-lcd";
48 reg = <0x10008000 0x1000>;
49 };
50
51 amba {
52 compatible = "arm,amba-bus";
53 #address-cells = <1>;
54 #size-cells = <1>;
55 ranges;
56
57 vic: intc@10140000 {
58 compatible = "arm,versatile-vic";
59 interrupt-controller;
60 #interrupt-cells = <1>;
61 reg = <0x10140000 0x1000>;
62 };
63
64 sic: intc@10003000 {
65 compatible = "arm,versatile-sic";
66 interrupt-controller;
67 #interrupt-cells = <1>;
68 reg = <0x10003000 0x1000>;
69 interrupt-parent = <&vic>;
70 interrupts = <31>; /* Cascaded to vic */
71 };
72
73 dma@10130000 {
74 compatible = "arm,pl081", "arm,primecell";
75 reg = <0x10130000 0x1000>;
76 interrupts = <17>;
77 };
78
79 uart0: uart@101f1000 {
80 compatible = "arm,pl011", "arm,primecell";
81 reg = <0x101f1000 0x1000>;
82 interrupts = <12>;
83 };
84
85 uart1: uart@101f2000 {
86 compatible = "arm,pl011", "arm,primecell";
87 reg = <0x101f2000 0x1000>;
88 interrupts = <13>;
89 };
90
91 uart2: uart@101f3000 {
92 compatible = "arm,pl011", "arm,primecell";
93 reg = <0x101f3000 0x1000>;
94 interrupts = <14>;
95 };
96
97 smc@10100000 {
98 compatible = "arm,primecell";
99 reg = <0x10100000 0x1000>;
100 };
101
102 mpmc@10110000 {
103 compatible = "arm,primecell";
104 reg = <0x10110000 0x1000>;
105 };
106
107 display@10120000 {
108 compatible = "arm,pl110", "arm,primecell";
109 reg = <0x10120000 0x1000>;
110 interrupts = <16>;
111 };
112
113 sctl@101e0000 {
114 compatible = "arm,primecell";
115 reg = <0x101e0000 0x1000>;
116 };
117
118 watchdog@101e1000 {
119 compatible = "arm,primecell";
120 reg = <0x101e1000 0x1000>;
121 interrupts = <0>;
122 };
123
124 gpio0: gpio@101e4000 {
125 compatible = "arm,pl061", "arm,primecell";
126 reg = <0x101e4000 0x1000>;
127 gpio-controller;
128 interrupts = <6>;
129 #gpio-cells = <2>;
130 interrupt-controller;
131 #interrupt-cells = <2>;
132 };
133
134 gpio1: gpio@101e5000 {
135 compatible = "arm,pl061", "arm,primecell";
136 reg = <0x101e5000 0x1000>;
137 interrupts = <7>;
138 gpio-controller;
139 #gpio-cells = <2>;
140 interrupt-controller;
141 #interrupt-cells = <2>;
142 };
143
144 rtc@101e8000 {
145 compatible = "arm,pl030", "arm,primecell";
146 reg = <0x101e8000 0x1000>;
147 interrupts = <10>;
148 };
149
150 sci@101f0000 {
151 compatible = "arm,primecell";
152 reg = <0x101f0000 0x1000>;
153 interrupts = <15>;
154 };
155
156 ssp@101f4000 {
157 compatible = "arm,pl022", "arm,primecell";
158 reg = <0x101f4000 0x1000>;
159 interrupts = <11>;
160 };
161
162 fpga {
163 compatible = "arm,versatile-fpga", "simple-bus";
164 #address-cells = <1>;
165 #size-cells = <1>;
166 ranges = <0 0x10000000 0x10000>;
167
168 aaci@4000 {
169 compatible = "arm,primecell";
170 reg = <0x4000 0x1000>;
171 interrupts = <24>;
172 };
173 mmc@5000 {
174 compatible = "arm,primecell";
175 reg = < 0x5000 0x1000>;
176 interrupts = <22>;
177 };
178 kmi@6000 {
179 compatible = "arm,pl050", "arm,primecell";
180 reg = <0x6000 0x1000>;
181 interrupt-parent = <&sic>;
182 interrupts = <3>;
183 };
184 kmi@7000 {
185 compatible = "arm,pl050", "arm,primecell";
186 reg = <0x7000 0x1000>;
187 interrupt-parent = <&sic>;
188 interrupts = <4>;
189 };
190 };
191 };
192};