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1/*
2 * DTS file for all SPEAr1310 SoCs
3 *
4 * Copyright 2012 Viresh Kumar <vireshk@kernel.org>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "spear13xx.dtsi"
15
16/ {
17 compatible = "st,spear1310";
18
19 ahb {
20 spics: spics@e0700000{
21 compatible = "st,spear-spics-gpio";
22 reg = <0xe0700000 0x1000>;
23 st-spics,peripcfg-reg = <0x3b0>;
24 st-spics,sw-enable-bit = <12>;
25 st-spics,cs-value-bit = <11>;
26 st-spics,cs-enable-mask = <3>;
27 st-spics,cs-enable-shift = <8>;
28 gpio-controller;
29 #gpio-cells = <2>;
30 };
31
32 miphy0: miphy@eb800000 {
33 compatible = "st,spear1310-miphy";
34 reg = <0xeb800000 0x4000>;
35 misc = <&misc>;
36 phy-id = <0>;
37 #phy-cells = <1>;
38 status = "disabled";
39 };
40
41 miphy1: miphy@eb804000 {
42 compatible = "st,spear1310-miphy";
43 reg = <0xeb804000 0x4000>;
44 misc = <&misc>;
45 phy-id = <1>;
46 #phy-cells = <1>;
47 status = "disabled";
48 };
49
50 miphy2: miphy@eb808000 {
51 compatible = "st,spear1310-miphy";
52 reg = <0xeb808000 0x4000>;
53 misc = <&misc>;
54 phy-id = <2>;
55 #phy-cells = <1>;
56 status = "disabled";
57 };
58
59 ahci0: ahci@b1000000 {
60 compatible = "snps,spear-ahci";
61 reg = <0xb1000000 0x10000>;
62 interrupts = <0 68 0x4>;
63 phys = <&miphy0 0>;
64 phy-names = "sata-phy";
65 status = "disabled";
66 };
67
68 ahci1: ahci@b1800000 {
69 compatible = "snps,spear-ahci";
70 reg = <0xb1800000 0x10000>;
71 interrupts = <0 69 0x4>;
72 phys = <&miphy1 0>;
73 phy-names = "sata-phy";
74 status = "disabled";
75 };
76
77 ahci2: ahci@b4000000 {
78 compatible = "snps,spear-ahci";
79 reg = <0xb4000000 0x10000>;
80 interrupts = <0 70 0x4>;
81 phys = <&miphy2 0>;
82 phy-names = "sata-phy";
83 status = "disabled";
84 };
85
86 pcie0: pcie@b1000000 {
87 compatible = "st,spear1340-pcie", "snps,dw-pcie";
88 reg = <0xb1000000 0x4000>, <0x80000000 0x20000>;
89 reg-names = "dbi", "config";
90 interrupts = <0 68 0x4>;
91 interrupt-map-mask = <0 0 0 0>;
92 interrupt-map = <0x0 0 &gic 0 68 0x4>;
93 num-lanes = <1>;
94 phys = <&miphy0 1>;
95 phy-names = "pcie-phy";
96 #address-cells = <3>;
97 #size-cells = <2>;
98 device_type = "pci";
99 ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
100 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
101 bus-range = <0x00 0xff>;
102 status = "disabled";
103 };
104
105 pcie1: pcie@b1800000 {
106 compatible = "st,spear1340-pcie", "snps,dw-pcie";
107 reg = <0xb1800000 0x4000>, <0x90000000 0x20000>;
108 reg-names = "dbi", "config";
109 interrupts = <0 69 0x4>;
110 interrupt-map-mask = <0 0 0 0>;
111 interrupt-map = <0x0 0 &gic 0 69 0x4>;
112 num-lanes = <1>;
113 phys = <&miphy1 1>;
114 phy-names = "pcie-phy";
115 #address-cells = <3>;
116 #size-cells = <2>;
117 device_type = "pci";
118 ranges = <0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */
119 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */
120 bus-range = <0x00 0xff>;
121 status = "disabled";
122 };
123
124 pcie2: pcie@b4000000 {
125 compatible = "st,spear1340-pcie", "snps,dw-pcie";
126 reg = <0xb4000000 0x4000>, <0xc0000000 0x20000>;
127 reg-names = "dbi", "config";
128 interrupts = <0 70 0x4>;
129 interrupt-map-mask = <0 0 0 0>;
130 interrupt-map = <0x0 0 &gic 0 70 0x4>;
131 num-lanes = <1>;
132 phys = <&miphy2 1>;
133 phy-names = "pcie-phy";
134 #address-cells = <3>;
135 #size-cells = <2>;
136 device_type = "pci";
137 ranges = <0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */
138 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
139 bus-range = <0x00 0xff>;
140 status = "disabled";
141 };
142
143 gmac1: eth@5c400000 {
144 compatible = "st,spear600-gmac";
145 reg = <0x5c400000 0x8000>;
146 interrupts = <0 95 0x4>;
147 interrupt-names = "macirq";
148 phy-mode = "mii";
149 status = "disabled";
150 };
151
152 gmac2: eth@5c500000 {
153 compatible = "st,spear600-gmac";
154 reg = <0x5c500000 0x8000>;
155 interrupts = <0 96 0x4>;
156 interrupt-names = "macirq";
157 phy-mode = "mii";
158 status = "disabled";
159 };
160
161 gmac3: eth@5c600000 {
162 compatible = "st,spear600-gmac";
163 reg = <0x5c600000 0x8000>;
164 interrupts = <0 97 0x4>;
165 interrupt-names = "macirq";
166 phy-mode = "rmii";
167 status = "disabled";
168 };
169
170 gmac4: eth@5c700000 {
171 compatible = "st,spear600-gmac";
172 reg = <0x5c700000 0x8000>;
173 interrupts = <0 98 0x4>;
174 interrupt-names = "macirq";
175 phy-mode = "rgmii";
176 status = "disabled";
177 };
178
179 pinmux: pinmux@e0700000 {
180 compatible = "st,spear1310-pinmux";
181 reg = <0xe0700000 0x1000>;
182 #gpio-range-cells = <3>;
183 };
184
185 apb {
186 i2c1: i2c@5cd00000 {
187 #address-cells = <1>;
188 #size-cells = <0>;
189 compatible = "snps,designware-i2c";
190 reg = <0x5cd00000 0x1000>;
191 interrupts = <0 87 0x4>;
192 status = "disabled";
193 };
194
195 i2c2: i2c@5ce00000 {
196 #address-cells = <1>;
197 #size-cells = <0>;
198 compatible = "snps,designware-i2c";
199 reg = <0x5ce00000 0x1000>;
200 interrupts = <0 88 0x4>;
201 status = "disabled";
202 };
203
204 i2c3: i2c@5cf00000 {
205 #address-cells = <1>;
206 #size-cells = <0>;
207 compatible = "snps,designware-i2c";
208 reg = <0x5cf00000 0x1000>;
209 interrupts = <0 89 0x4>;
210 status = "disabled";
211 };
212
213 i2c4: i2c@5d000000 {
214 #address-cells = <1>;
215 #size-cells = <0>;
216 compatible = "snps,designware-i2c";
217 reg = <0x5d000000 0x1000>;
218 interrupts = <0 90 0x4>;
219 status = "disabled";
220 };
221
222 i2c5: i2c@5d100000 {
223 #address-cells = <1>;
224 #size-cells = <0>;
225 compatible = "snps,designware-i2c";
226 reg = <0x5d100000 0x1000>;
227 interrupts = <0 91 0x4>;
228 status = "disabled";
229 };
230
231 i2c6: i2c@5d200000 {
232 #address-cells = <1>;
233 #size-cells = <0>;
234 compatible = "snps,designware-i2c";
235 reg = <0x5d200000 0x1000>;
236 interrupts = <0 92 0x4>;
237 status = "disabled";
238 };
239
240 i2c7: i2c@5d300000 {
241 #address-cells = <1>;
242 #size-cells = <0>;
243 compatible = "snps,designware-i2c";
244 reg = <0x5d300000 0x1000>;
245 interrupts = <0 93 0x4>;
246 status = "disabled";
247 };
248
249 spi1: spi@5d400000 {
250 compatible = "arm,pl022", "arm,primecell";
251 reg = <0x5d400000 0x1000>;
252 interrupts = <0 99 0x4>;
253 #address-cells = <1>;
254 #size-cells = <0>;
255 status = "disabled";
256 };
257
258 serial@5c800000 {
259 compatible = "arm,pl011", "arm,primecell";
260 reg = <0x5c800000 0x1000>;
261 interrupts = <0 82 0x4>;
262 status = "disabled";
263 };
264
265 serial@5c900000 {
266 compatible = "arm,pl011", "arm,primecell";
267 reg = <0x5c900000 0x1000>;
268 interrupts = <0 83 0x4>;
269 status = "disabled";
270 };
271
272 serial@5ca00000 {
273 compatible = "arm,pl011", "arm,primecell";
274 reg = <0x5ca00000 0x1000>;
275 interrupts = <0 84 0x4>;
276 status = "disabled";
277 };
278
279 serial@5cb00000 {
280 compatible = "arm,pl011", "arm,primecell";
281 reg = <0x5cb00000 0x1000>;
282 interrupts = <0 85 0x4>;
283 status = "disabled";
284 };
285
286 serial@5cc00000 {
287 compatible = "arm,pl011", "arm,primecell";
288 reg = <0x5cc00000 0x1000>;
289 interrupts = <0 86 0x4>;
290 status = "disabled";
291 };
292
293 thermal@e07008c4 {
294 st,thermal-flags = <0x7000>;
295 };
296
297 gpiopinctrl: gpio@d8400000 {
298 compatible = "st,spear-plgpio";
299 reg = <0xd8400000 0x1000>;
300 interrupts = <0 100 0x4>;
301 #interrupt-cells = <1>;
302 interrupt-controller;
303 gpio-controller;
304 #gpio-cells = <2>;
305 gpio-ranges = <&pinmux 0 0 246>;
306 status = "disabled";
307
308 st-plgpio,ngpio = <246>;
309 st-plgpio,enb-reg = <0xd0>;
310 st-plgpio,wdata-reg = <0x90>;
311 st-plgpio,dir-reg = <0xb0>;
312 st-plgpio,ie-reg = <0x30>;
313 st-plgpio,rdata-reg = <0x70>;
314 st-plgpio,mis-reg = <0x10>;
315 st-plgpio,eit-reg = <0x50>;
316 };
317 };
318 };
319};