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1/*
2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
5 * whole.
6 *
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
11 *
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * Or, alternatively,
18 *
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
26 * conditions:
27 *
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
30 *
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
39 */
40
41#include <dt-bindings/gpio/gpio.h>
42#include <dt-bindings/interrupt-controller/irq.h>
43#include <dt-bindings/interrupt-controller/arm-gic.h>
44#include <dt-bindings/pinctrl/rockchip.h>
45#include <dt-bindings/clock/rk3036-cru.h>
46#include <dt-bindings/soc/rockchip,boot-mode.h>
47
48/ {
49 #address-cells = <1>;
50 #size-cells = <1>;
51
52 compatible = "rockchip,rk3036";
53
54 interrupt-parent = <&gic>;
55
56 aliases {
57 i2c0 = &i2c0;
58 i2c1 = &i2c1;
59 i2c2 = &i2c2;
60 mshc0 = &emmc;
61 mshc1 = &sdmmc;
62 mshc2 = &sdio;
63 serial0 = &uart0;
64 serial1 = &uart1;
65 serial2 = &uart2;
66 spi = &spi;
67 };
68
69 cpus {
70 #address-cells = <1>;
71 #size-cells = <0>;
72 enable-method = "rockchip,rk3036-smp";
73
74 cpu0: cpu@f00 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a7";
77 reg = <0xf00>;
78 resets = <&cru SRST_CORE0>;
79 operating-points = <
80 /* KHz uV */
81 816000 1000000
82 >;
83 clock-latency = <40000>;
84 clocks = <&cru ARMCLK>;
85 };
86
87 cpu1: cpu@f01 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a7";
90 reg = <0xf01>;
91 resets = <&cru SRST_CORE1>;
92 };
93 };
94
95 amba {
96 compatible = "simple-bus";
97 #address-cells = <1>;
98 #size-cells = <1>;
99 ranges;
100
101 pdma: pdma@20078000 {
102 compatible = "arm,pl330", "arm,primecell";
103 reg = <0x20078000 0x4000>;
104 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
106 #dma-cells = <1>;
107 arm,pl330-broken-no-flushp;
108 clocks = <&cru ACLK_DMAC2>;
109 clock-names = "apb_pclk";
110 };
111 };
112
113 arm-pmu {
114 compatible = "arm,cortex-a7-pmu";
115 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
116 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
117 interrupt-affinity = <&cpu0>, <&cpu1>;
118 };
119
120 display-subsystem {
121 compatible = "rockchip,display-subsystem";
122 ports = <&vop_out>;
123 };
124
125 timer {
126 compatible = "arm,armv7-timer";
127 arm,cpu-registers-not-fw-configured;
128 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
129 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
130 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
131 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
132 clock-frequency = <24000000>;
133 };
134
135 xin24m: oscillator {
136 compatible = "fixed-clock";
137 clock-frequency = <24000000>;
138 clock-output-names = "xin24m";
139 #clock-cells = <0>;
140 };
141
142 bus_intmem@10080000 {
143 compatible = "mmio-sram";
144 reg = <0x10080000 0x2000>;
145 #address-cells = <1>;
146 #size-cells = <1>;
147 ranges = <0 0x10080000 0x2000>;
148
149 smp-sram@0 {
150 compatible = "rockchip,rk3066-smp-sram";
151 reg = <0x00 0x10>;
152 };
153 };
154
155 gpu: gpu@10090000 {
156 compatible = "rockchip,rk3036-mali", "arm,mali-400";
157 reg = <0x10090000 0x10000>;
158 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
162 interrupt-names = "gp",
163 "gpmmu",
164 "pp0",
165 "ppmmu0";
166 assigned-clocks = <&cru SCLK_GPU>;
167 assigned-clock-rates = <100000000>;
168 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
169 clock-names = "core", "bus";
170 resets = <&cru SRST_GPU>;
171 status = "disabled";
172 };
173
174 vop: vop@10118000 {
175 compatible = "rockchip,rk3036-vop";
176 reg = <0x10118000 0x19c>;
177 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
178 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
179 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
180 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
181 reset-names = "axi", "ahb", "dclk";
182 iommus = <&vop_mmu>;
183 status = "disabled";
184
185 vop_out: port {
186 #address-cells = <1>;
187 #size-cells = <0>;
188 vop_out_hdmi: endpoint@0 {
189 reg = <0>;
190 remote-endpoint = <&hdmi_in_vop>;
191 };
192 };
193 };
194
195 vop_mmu: iommu@10118300 {
196 compatible = "rockchip,iommu";
197 reg = <0x10118300 0x100>;
198 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
199 interrupt-names = "vop_mmu";
200 #iommu-cells = <0>;
201 status = "disabled";
202 };
203
204 gic: interrupt-controller@10139000 {
205 compatible = "arm,gic-400";
206 interrupt-controller;
207 #interrupt-cells = <3>;
208 #address-cells = <0>;
209
210 reg = <0x10139000 0x1000>,
211 <0x1013a000 0x2000>,
212 <0x1013c000 0x2000>,
213 <0x1013e000 0x2000>;
214 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
215 };
216
217 usb_otg: usb@10180000 {
218 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
219 "snps,dwc2";
220 reg = <0x10180000 0x40000>;
221 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&cru HCLK_OTG0>;
223 clock-names = "otg";
224 dr_mode = "otg";
225 g-np-tx-fifo-size = <16>;
226 g-rx-fifo-size = <275>;
227 g-tx-fifo-size = <256 128 128 64 64 32>;
228 status = "disabled";
229 };
230
231 usb_host: usb@101c0000 {
232 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
233 "snps,dwc2";
234 reg = <0x101c0000 0x40000>;
235 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&cru HCLK_OTG1>;
237 clock-names = "otg";
238 dr_mode = "host";
239 status = "disabled";
240 };
241
242 emac: ethernet@10200000 {
243 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
244 reg = <0x10200000 0x4000>;
245 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
246 #address-cells = <1>;
247 #size-cells = <0>;
248 rockchip,grf = <&grf>;
249 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
250 clock-names = "hclk", "macref", "macclk";
251 /*
252 * Fix the emac parent clock is DPLL instead of APLL.
253 * since that will cause some unstable things if the cpufreq
254 * is working. (e.g: the accurate 50MHz what mac_ref need)
255 */
256 assigned-clocks = <&cru SCLK_MACPLL>;
257 assigned-clock-parents = <&cru PLL_DPLL>;
258 max-speed = <100>;
259 phy-mode = "rmii";
260 status = "disabled";
261 };
262
263 sdmmc: dwmmc@10214000 {
264 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
265 reg = <0x10214000 0x4000>;
266 clock-frequency = <37500000>;
267 max-frequency = <37500000>;
268 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
269 clock-names = "biu", "ciu";
270 fifo-depth = <0x100>;
271 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
272 resets = <&cru SRST_MMC0>;
273 reset-names = "reset";
274 status = "disabled";
275 };
276
277 sdio: dwmmc@10218000 {
278 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
279 reg = <0x10218000 0x4000>;
280 max-frequency = <37500000>;
281 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
282 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
283 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
284 fifo-depth = <0x100>;
285 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
286 resets = <&cru SRST_SDIO>;
287 reset-names = "reset";
288 status = "disabled";
289 };
290
291 emmc: dwmmc@1021c000 {
292 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
293 reg = <0x1021c000 0x4000>;
294 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
295 bus-width = <8>;
296 cap-mmc-highspeed;
297 clock-frequency = <37500000>;
298 max-frequency = <37500000>;
299 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
300 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
301 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
302 default-sample-phase = <158>;
303 disable-wp;
304 dmas = <&pdma 12>;
305 dma-names = "rx-tx";
306 fifo-depth = <0x100>;
307 mmc-ddr-1_8v;
308 non-removable;
309 pinctrl-names = "default";
310 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
311 resets = <&cru SRST_EMMC>;
312 reset-names = "reset";
313 status = "disabled";
314 };
315
316 i2s: i2s@10220000 {
317 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
318 reg = <0x10220000 0x4000>;
319 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
320 #address-cells = <1>;
321 #size-cells = <0>;
322 clock-names = "i2s_clk", "i2s_hclk";
323 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
324 dmas = <&pdma 0>, <&pdma 1>;
325 dma-names = "tx", "rx";
326 pinctrl-names = "default";
327 pinctrl-0 = <&i2s_bus>;
328 status = "disabled";
329 };
330
331 cru: clock-controller@20000000 {
332 compatible = "rockchip,rk3036-cru";
333 reg = <0x20000000 0x1000>;
334 rockchip,grf = <&grf>;
335 #clock-cells = <1>;
336 #reset-cells = <1>;
337 assigned-clocks = <&cru PLL_GPLL>;
338 assigned-clock-rates = <594000000>;
339 };
340
341 grf: syscon@20008000 {
342 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
343 reg = <0x20008000 0x1000>;
344
345 reboot-mode {
346 compatible = "syscon-reboot-mode";
347 offset = <0x1d8>;
348 mode-normal = <BOOT_NORMAL>;
349 mode-recovery = <BOOT_RECOVERY>;
350 mode-bootloader = <BOOT_FASTBOOT>;
351 mode-loader = <BOOT_BL_DOWNLOAD>;
352 };
353 };
354
355 acodec: acodec-ana@20030000 {
356 compatible = "rk3036-codec";
357 reg = <0x20030000 0x4000>;
358 rockchip,grf = <&grf>;
359 clock-names = "acodec_pclk";
360 clocks = <&cru PCLK_ACODEC>;
361 status = "disabled";
362 };
363
364 hdmi: hdmi@20034000 {
365 compatible = "rockchip,rk3036-inno-hdmi";
366 reg = <0x20034000 0x4000>;
367 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&cru PCLK_HDMI>;
369 clock-names = "pclk";
370 rockchip,grf = <&grf>;
371 pinctrl-names = "default";
372 pinctrl-0 = <&hdmi_ctl>;
373 status = "disabled";
374
375 hdmi_in: port {
376 #address-cells = <1>;
377 #size-cells = <0>;
378 hdmi_in_vop: endpoint@0 {
379 reg = <0>;
380 remote-endpoint = <&vop_out_hdmi>;
381 };
382 };
383 };
384
385 timer: timer@20044000 {
386 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
387 reg = <0x20044000 0x20>;
388 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
389 clocks = <&xin24m>, <&cru PCLK_TIMER>;
390 clock-names = "timer", "pclk";
391 };
392
393 pwm0: pwm@20050000 {
394 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
395 reg = <0x20050000 0x10>;
396 #pwm-cells = <3>;
397 clocks = <&cru PCLK_PWM>;
398 clock-names = "pwm";
399 pinctrl-names = "default";
400 pinctrl-0 = <&pwm0_pin>;
401 status = "disabled";
402 };
403
404 pwm1: pwm@20050010 {
405 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
406 reg = <0x20050010 0x10>;
407 #pwm-cells = <3>;
408 clocks = <&cru PCLK_PWM>;
409 clock-names = "pwm";
410 pinctrl-names = "default";
411 pinctrl-0 = <&pwm1_pin>;
412 status = "disabled";
413 };
414
415 pwm2: pwm@20050020 {
416 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
417 reg = <0x20050020 0x10>;
418 #pwm-cells = <3>;
419 clocks = <&cru PCLK_PWM>;
420 clock-names = "pwm";
421 pinctrl-names = "default";
422 pinctrl-0 = <&pwm2_pin>;
423 status = "disabled";
424 };
425
426 pwm3: pwm@20050030 {
427 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
428 reg = <0x20050030 0x10>;
429 #pwm-cells = <2>;
430 clocks = <&cru PCLK_PWM>;
431 clock-names = "pwm";
432 pinctrl-names = "default";
433 pinctrl-0 = <&pwm3_pin>;
434 status = "disabled";
435 };
436
437 i2c1: i2c@20056000 {
438 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
439 reg = <0x20056000 0x1000>;
440 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
441 #address-cells = <1>;
442 #size-cells = <0>;
443 clock-names = "i2c";
444 clocks = <&cru PCLK_I2C1>;
445 pinctrl-names = "default";
446 pinctrl-0 = <&i2c1_xfer>;
447 status = "disabled";
448 };
449
450 i2c2: i2c@2005a000 {
451 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
452 reg = <0x2005a000 0x1000>;
453 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
454 #address-cells = <1>;
455 #size-cells = <0>;
456 clock-names = "i2c";
457 clocks = <&cru PCLK_I2C2>;
458 pinctrl-names = "default";
459 pinctrl-0 = <&i2c2_xfer>;
460 status = "disabled";
461 };
462
463 uart0: serial@20060000 {
464 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
465 reg = <0x20060000 0x100>;
466 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
467 reg-shift = <2>;
468 reg-io-width = <4>;
469 clock-frequency = <24000000>;
470 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
471 clock-names = "baudclk", "apb_pclk";
472 pinctrl-names = "default";
473 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
474 status = "disabled";
475 };
476
477 uart1: serial@20064000 {
478 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
479 reg = <0x20064000 0x100>;
480 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
481 reg-shift = <2>;
482 reg-io-width = <4>;
483 clock-frequency = <24000000>;
484 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
485 clock-names = "baudclk", "apb_pclk";
486 pinctrl-names = "default";
487 pinctrl-0 = <&uart1_xfer>;
488 status = "disabled";
489 };
490
491 uart2: serial@20068000 {
492 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
493 reg = <0x20068000 0x100>;
494 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
495 reg-shift = <2>;
496 reg-io-width = <4>;
497 clock-frequency = <24000000>;
498 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
499 clock-names = "baudclk", "apb_pclk";
500 pinctrl-names = "default";
501 pinctrl-0 = <&uart2_xfer>;
502 status = "disabled";
503 };
504
505 i2c0: i2c@20072000 {
506 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
507 reg = <0x20072000 0x1000>;
508 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
509 #address-cells = <1>;
510 #size-cells = <0>;
511 clock-names = "i2c";
512 clocks = <&cru PCLK_I2C0>;
513 pinctrl-names = "default";
514 pinctrl-0 = <&i2c0_xfer>;
515 status = "disabled";
516 };
517
518 spi: spi@20074000 {
519 compatible = "rockchip,rockchip-spi";
520 reg = <0x20074000 0x1000>;
521 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
522 clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>;
523 clock-names = "apb-pclk","spi_pclk";
524 dmas = <&pdma 8>, <&pdma 9>;
525 dma-names = "tx", "rx";
526 pinctrl-names = "default";
527 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
528 #address-cells = <1>;
529 #size-cells = <0>;
530 status = "disabled";
531 };
532
533 pinctrl: pinctrl {
534 compatible = "rockchip,rk3036-pinctrl";
535 rockchip,grf = <&grf>;
536 #address-cells = <1>;
537 #size-cells = <1>;
538 ranges;
539
540 gpio0: gpio0@2007c000 {
541 compatible = "rockchip,gpio-bank";
542 reg = <0x2007c000 0x100>;
543 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&cru PCLK_GPIO0>;
545
546 gpio-controller;
547 #gpio-cells = <2>;
548
549 interrupt-controller;
550 #interrupt-cells = <2>;
551 };
552
553 gpio1: gpio1@20080000 {
554 compatible = "rockchip,gpio-bank";
555 reg = <0x20080000 0x100>;
556 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&cru PCLK_GPIO1>;
558
559 gpio-controller;
560 #gpio-cells = <2>;
561
562 interrupt-controller;
563 #interrupt-cells = <2>;
564 };
565
566 gpio2: gpio2@20084000 {
567 compatible = "rockchip,gpio-bank";
568 reg = <0x20084000 0x100>;
569 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&cru PCLK_GPIO2>;
571
572 gpio-controller;
573 #gpio-cells = <2>;
574
575 interrupt-controller;
576 #interrupt-cells = <2>;
577 };
578
579 pcfg_pull_default: pcfg_pull_default {
580 bias-pull-pin-default;
581 };
582
583 pcfg_pull_none: pcfg-pull-none {
584 bias-disable;
585 };
586
587 pwm0 {
588 pwm0_pin: pwm0-pin {
589 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
590 };
591 };
592
593 pwm1 {
594 pwm1_pin: pwm1-pin {
595 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
596 };
597 };
598
599 pwm2 {
600 pwm2_pin: pwm2-pin {
601 rockchip,pins = <0 1 2 &pcfg_pull_none>;
602 };
603 };
604
605 pwm3 {
606 pwm3_pin: pwm3-pin {
607 rockchip,pins = <0 27 1 &pcfg_pull_none>;
608 };
609 };
610
611 sdmmc {
612 sdmmc_clk: sdmmc-clk {
613 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>;
614 };
615
616 sdmmc_cmd: sdmmc-cmd {
617 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>;
618 };
619
620 sdmmc_cd: sdmmc-cd {
621 rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>;
622 };
623
624 sdmmc_bus1: sdmmc-bus1 {
625 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>;
626 };
627
628 sdmmc_bus4: sdmmc-bus4 {
629 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>,
630 <1 19 RK_FUNC_1 &pcfg_pull_default>,
631 <1 20 RK_FUNC_1 &pcfg_pull_default>,
632 <1 21 RK_FUNC_1 &pcfg_pull_default>;
633 };
634 };
635
636 sdio {
637 sdio_bus1: sdio-bus1 {
638 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>;
639 };
640
641 sdio_bus4: sdio-bus4 {
642 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>,
643 <0 12 RK_FUNC_1 &pcfg_pull_default>,
644 <0 13 RK_FUNC_1 &pcfg_pull_default>,
645 <0 14 RK_FUNC_1 &pcfg_pull_default>;
646 };
647
648 sdio_cmd: sdio-cmd {
649 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>;
650 };
651
652 sdio_clk: sdio-clk {
653 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>;
654 };
655 };
656
657 emmc {
658 /*
659 * We run eMMC at max speed; bump up drive strength.
660 * We also have external pulls, so disable the internal ones.
661 */
662 emmc_clk: emmc-clk {
663 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
664 };
665
666 emmc_cmd: emmc-cmd {
667 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>;
668 };
669
670 emmc_bus8: emmc-bus8 {
671 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>,
672 <1 25 RK_FUNC_2 &pcfg_pull_default>,
673 <1 26 RK_FUNC_2 &pcfg_pull_default>,
674 <1 27 RK_FUNC_2 &pcfg_pull_default>,
675 <1 28 RK_FUNC_2 &pcfg_pull_default>,
676 <1 29 RK_FUNC_2 &pcfg_pull_default>,
677 <1 30 RK_FUNC_2 &pcfg_pull_default>,
678 <1 31 RK_FUNC_2 &pcfg_pull_default>;
679 };
680 };
681
682 emac {
683 emac_xfer: emac-xfer {
684 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_default>, /* crs_dvalid */
685 <2 13 RK_FUNC_1 &pcfg_pull_default>, /* tx_en */
686 <2 14 RK_FUNC_1 &pcfg_pull_default>, /* mac_clk */
687 <2 15 RK_FUNC_1 &pcfg_pull_default>, /* rx_err */
688 <2 16 RK_FUNC_1 &pcfg_pull_default>, /* rxd1 */
689 <2 17 RK_FUNC_1 &pcfg_pull_default>, /* rxd0 */
690 <2 18 RK_FUNC_1 &pcfg_pull_default>, /* txd1 */
691 <2 19 RK_FUNC_1 &pcfg_pull_default>; /* txd0 */
692 };
693
694 emac_mdio: emac-mdio {
695 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_default>, /* mac_md */
696 <2 25 RK_FUNC_1 &pcfg_pull_default>; /* mac_mdclk */
697 };
698 };
699
700 i2c0 {
701 i2c0_xfer: i2c0-xfer {
702 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
703 <0 1 RK_FUNC_1 &pcfg_pull_none>;
704 };
705 };
706
707 i2c1 {
708 i2c1_xfer: i2c1-xfer {
709 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
710 <0 3 RK_FUNC_1 &pcfg_pull_none>;
711 };
712 };
713
714 i2c2 {
715 i2c2_xfer: i2c2-xfer {
716 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
717 <2 21 RK_FUNC_1 &pcfg_pull_none>;
718 };
719 };
720
721 i2s {
722 i2s_bus: i2s-bus {
723 rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>,
724 <1 1 RK_FUNC_1 &pcfg_pull_default>,
725 <1 2 RK_FUNC_1 &pcfg_pull_default>,
726 <1 3 RK_FUNC_1 &pcfg_pull_default>,
727 <1 4 RK_FUNC_1 &pcfg_pull_default>,
728 <1 5 RK_FUNC_1 &pcfg_pull_default>;
729 };
730 };
731
732 hdmi {
733 hdmi_ctl: hdmi-ctl {
734 rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>,
735 <1 9 RK_FUNC_1 &pcfg_pull_none>,
736 <1 10 RK_FUNC_1 &pcfg_pull_none>,
737 <1 11 RK_FUNC_1 &pcfg_pull_none>;
738 };
739 };
740
741 uart0 {
742 uart0_xfer: uart0-xfer {
743 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,
744 <0 17 RK_FUNC_1 &pcfg_pull_none>;
745 };
746
747 uart0_cts: uart0-cts {
748 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>;
749 };
750
751 uart0_rts: uart0-rts {
752 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
753 };
754 };
755
756 uart1 {
757 uart1_xfer: uart1-xfer {
758 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>,
759 <2 23 RK_FUNC_1 &pcfg_pull_none>;
760 };
761 /* no rts / cts for uart1 */
762 };
763
764 uart2 {
765 uart2_xfer: uart2-xfer {
766 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>,
767 <1 19 RK_FUNC_2 &pcfg_pull_none>;
768 };
769 /* no rts / cts for uart2 */
770 };
771
772 spi {
773 spi_txd:spi-txd {
774 rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>;
775 };
776
777 spi_rxd:spi-rxd {
778 rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>;
779 };
780
781 spi_clk:spi-clk {
782 rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>;
783 };
784
785 spi_cs0:spi-cs0 {
786 rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>;
787
788 };
789
790 spi_cs1:spi-cs1 {
791 rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>;
792
793 };
794 };
795 };
796};