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1/*
2 * Device Tree Source for the r7s72100 SoC
3 *
4 * Copyright (C) 2013-14 Renesas Solutions Corp.
5 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#include <dt-bindings/clock/r7s72100-clock.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15
16/ {
17 compatible = "renesas,r7s72100";
18 interrupt-parent = <&gic>;
19 #address-cells = <1>;
20 #size-cells = <1>;
21
22 aliases {
23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 spi0 = &spi0;
28 spi1 = &spi1;
29 spi2 = &spi2;
30 spi3 = &spi3;
31 spi4 = &spi4;
32 };
33
34 clocks {
35 ranges;
36 #address-cells = <1>;
37 #size-cells = <1>;
38
39 /* External clocks */
40 extal_clk: extal {
41 #clock-cells = <0>;
42 compatible = "fixed-clock";
43 /* If clk present, value must be set by board */
44 clock-frequency = <0>;
45 };
46
47 usb_x1_clk: usb_x1 {
48 #clock-cells = <0>;
49 compatible = "fixed-clock";
50 /* If clk present, value must be set by board */
51 clock-frequency = <0>;
52 };
53
54 rtc_x1_clk: rtc_x1 {
55 #clock-cells = <0>;
56 compatible = "fixed-clock";
57 /* If clk present, value must be set by board to 32678 */
58 clock-frequency = <0>;
59 };
60
61 rtc_x3_clk: rtc_x3 {
62 #clock-cells = <0>;
63 compatible = "fixed-clock";
64 /* If clk present, value must be set by board to 4000000 */
65 clock-frequency = <0>;
66 };
67
68 /* Fixed factor clocks */
69 b_clk: b {
70 #clock-cells = <0>;
71 compatible = "fixed-factor-clock";
72 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
73 clock-mult = <1>;
74 clock-div = <3>;
75 };
76 p1_clk: p1 {
77 #clock-cells = <0>;
78 compatible = "fixed-factor-clock";
79 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
80 clock-mult = <1>;
81 clock-div = <6>;
82 };
83 p0_clk: p0 {
84 #clock-cells = <0>;
85 compatible = "fixed-factor-clock";
86 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
87 clock-mult = <1>;
88 clock-div = <12>;
89 };
90
91 /* Special CPG clocks */
92 cpg_clocks: cpg_clocks@fcfe0000 {
93 #clock-cells = <1>;
94 compatible = "renesas,r7s72100-cpg-clocks",
95 "renesas,rz-cpg-clocks";
96 reg = <0xfcfe0000 0x18>;
97 clocks = <&extal_clk>, <&usb_x1_clk>;
98 clock-output-names = "pll", "i", "g";
99 #power-domain-cells = <0>;
100 };
101
102 /* MSTP clocks */
103 mstp3_clks: mstp3_clks@fcfe0420 {
104 #clock-cells = <1>;
105 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
106 reg = <0xfcfe0420 4>;
107 clocks = <&p0_clk>;
108 clock-indices = <R7S72100_CLK_MTU2>;
109 clock-output-names = "mtu2";
110 };
111
112 mstp4_clks: mstp4_clks@fcfe0424 {
113 #clock-cells = <1>;
114 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
115 reg = <0xfcfe0424 4>;
116 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
117 <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
118 clock-indices = <
119 R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
120 R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
121 >;
122 clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
123 };
124
125 mstp5_clks: mstp5_clks@fcfe0428 {
126 #clock-cells = <1>;
127 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
128 reg = <0xfcfe0428 4>;
129 clocks = <&p0_clk>, <&p0_clk>;
130 clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>;
131 clock-output-names = "ostm0", "ostm1";
132 };
133
134 mstp6_clks: mstp6_clks@fcfe042c {
135 #clock-cells = <1>;
136 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
137 reg = <0xfcfe042c 4>;
138 clocks = <&p0_clk>;
139 clock-indices = <R7S72100_CLK_RTC>;
140 clock-output-names = "rtc";
141 };
142
143 mstp7_clks: mstp7_clks@fcfe0430 {
144 #clock-cells = <1>;
145 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
146 reg = <0xfcfe0430 4>;
147 clocks = <&b_clk>, <&p1_clk>, <&p1_clk>;
148 clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>;
149 clock-output-names = "ether", "usb0", "usb1";
150 };
151
152 mstp8_clks: mstp8_clks@fcfe0434 {
153 #clock-cells = <1>;
154 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
155 reg = <0xfcfe0434 4>;
156 clocks = <&p1_clk>;
157 clock-indices = <R7S72100_CLK_MMCIF>;
158 clock-output-names = "mmcif";
159 };
160
161 mstp9_clks: mstp9_clks@fcfe0438 {
162 #clock-cells = <1>;
163 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
164 reg = <0xfcfe0438 4>;
165 clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
166 clock-indices = <
167 R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
168 >;
169 clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
170 };
171
172 mstp10_clks: mstp10_clks@fcfe043c {
173 #clock-cells = <1>;
174 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
175 reg = <0xfcfe043c 4>;
176 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
177 <&p1_clk>;
178 clock-indices = <
179 R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
180 R7S72100_CLK_SPI4
181 >;
182 clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
183 };
184 mstp12_clks: mstp12_clks@fcfe0444 {
185 #clock-cells = <1>;
186 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
187 reg = <0xfcfe0444 4>;
188 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
189 clock-indices = <
190 R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01
191 R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
192 >;
193 clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
194 };
195 };
196
197 cpus {
198 #address-cells = <1>;
199 #size-cells = <0>;
200
201 cpu@0 {
202 device_type = "cpu";
203 compatible = "arm,cortex-a9";
204 reg = <0>;
205 clock-frequency = <400000000>;
206 clocks = <&cpg_clocks R7S72100_CLK_I>;
207 next-level-cache = <&L2>;
208 };
209 };
210
211 pinctrl: pin-controller@fcfe3000 {
212 compatible = "renesas,r7s72100-ports";
213
214 reg = <0xfcfe3000 0x4230>;
215
216 port0: gpio-0 {
217 gpio-controller;
218 #gpio-cells = <2>;
219 gpio-ranges = <&pinctrl 0 0 6>;
220 };
221
222 port1: gpio-1 {
223 gpio-controller;
224 #gpio-cells = <2>;
225 gpio-ranges = <&pinctrl 0 16 16>;
226 };
227
228 port2: gpio-2 {
229 gpio-controller;
230 #gpio-cells = <2>;
231 gpio-ranges = <&pinctrl 0 32 16>;
232 };
233
234 port3: gpio-3 {
235 gpio-controller;
236 #gpio-cells = <2>;
237 gpio-ranges = <&pinctrl 0 48 16>;
238 };
239
240 port4: gpio-4 {
241 gpio-controller;
242 #gpio-cells = <2>;
243 gpio-ranges = <&pinctrl 0 64 16>;
244 };
245
246 port5: gpio-5 {
247 gpio-controller;
248 #gpio-cells = <2>;
249 gpio-ranges = <&pinctrl 0 80 11>;
250 };
251
252 port6: gpio-6 {
253 gpio-controller;
254 #gpio-cells = <2>;
255 gpio-ranges = <&pinctrl 0 96 16>;
256 };
257
258 port7: gpio-7 {
259 gpio-controller;
260 #gpio-cells = <2>;
261 gpio-ranges = <&pinctrl 0 112 16>;
262 };
263
264 port8: gpio-8 {
265 gpio-controller;
266 #gpio-cells = <2>;
267 gpio-ranges = <&pinctrl 0 128 16>;
268 };
269
270 port9: gpio-9 {
271 gpio-controller;
272 #gpio-cells = <2>;
273 gpio-ranges = <&pinctrl 0 144 8>;
274 };
275
276 port10: gpio-10 {
277 gpio-controller;
278 #gpio-cells = <2>;
279 gpio-ranges = <&pinctrl 0 160 16>;
280 };
281
282 port11: gpio-11 {
283 gpio-controller;
284 #gpio-cells = <2>;
285 gpio-ranges = <&pinctrl 0 176 16>;
286 };
287 };
288
289 scif0: serial@e8007000 {
290 compatible = "renesas,scif-r7s72100", "renesas,scif";
291 reg = <0xe8007000 64>;
292 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
297 clock-names = "fck";
298 power-domains = <&cpg_clocks>;
299 status = "disabled";
300 };
301
302 scif1: serial@e8007800 {
303 compatible = "renesas,scif-r7s72100", "renesas,scif";
304 reg = <0xe8007800 64>;
305 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
310 clock-names = "fck";
311 power-domains = <&cpg_clocks>;
312 status = "disabled";
313 };
314
315 scif2: serial@e8008000 {
316 compatible = "renesas,scif-r7s72100", "renesas,scif";
317 reg = <0xe8008000 64>;
318 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
323 clock-names = "fck";
324 power-domains = <&cpg_clocks>;
325 status = "disabled";
326 };
327
328 scif3: serial@e8008800 {
329 compatible = "renesas,scif-r7s72100", "renesas,scif";
330 reg = <0xe8008800 64>;
331 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
336 clock-names = "fck";
337 power-domains = <&cpg_clocks>;
338 status = "disabled";
339 };
340
341 scif4: serial@e8009000 {
342 compatible = "renesas,scif-r7s72100", "renesas,scif";
343 reg = <0xe8009000 64>;
344 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
347 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
349 clock-names = "fck";
350 power-domains = <&cpg_clocks>;
351 status = "disabled";
352 };
353
354 scif5: serial@e8009800 {
355 compatible = "renesas,scif-r7s72100", "renesas,scif";
356 reg = <0xe8009800 64>;
357 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
360 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
362 clock-names = "fck";
363 power-domains = <&cpg_clocks>;
364 status = "disabled";
365 };
366
367 scif6: serial@e800a000 {
368 compatible = "renesas,scif-r7s72100", "renesas,scif";
369 reg = <0xe800a000 64>;
370 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
371 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
373 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
375 clock-names = "fck";
376 power-domains = <&cpg_clocks>;
377 status = "disabled";
378 };
379
380 scif7: serial@e800a800 {
381 compatible = "renesas,scif-r7s72100", "renesas,scif";
382 reg = <0xe800a800 64>;
383 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
384 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
386 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
388 clock-names = "fck";
389 power-domains = <&cpg_clocks>;
390 status = "disabled";
391 };
392
393 spi0: spi@e800c800 {
394 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
395 reg = <0xe800c800 0x24>;
396 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
397 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
398 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
399 interrupt-names = "error", "rx", "tx";
400 clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
401 power-domains = <&cpg_clocks>;
402 num-cs = <1>;
403 #address-cells = <1>;
404 #size-cells = <0>;
405 status = "disabled";
406 };
407
408 spi1: spi@e800d000 {
409 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
410 reg = <0xe800d000 0x24>;
411 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
412 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
413 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
414 interrupt-names = "error", "rx", "tx";
415 clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
416 power-domains = <&cpg_clocks>;
417 num-cs = <1>;
418 #address-cells = <1>;
419 #size-cells = <0>;
420 status = "disabled";
421 };
422
423 spi2: spi@e800d800 {
424 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
425 reg = <0xe800d800 0x24>;
426 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
427 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
429 interrupt-names = "error", "rx", "tx";
430 clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
431 power-domains = <&cpg_clocks>;
432 num-cs = <1>;
433 #address-cells = <1>;
434 #size-cells = <0>;
435 status = "disabled";
436 };
437
438 spi3: spi@e800e000 {
439 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
440 reg = <0xe800e000 0x24>;
441 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
444 interrupt-names = "error", "rx", "tx";
445 clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
446 power-domains = <&cpg_clocks>;
447 num-cs = <1>;
448 #address-cells = <1>;
449 #size-cells = <0>;
450 status = "disabled";
451 };
452
453 spi4: spi@e800e800 {
454 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
455 reg = <0xe800e800 0x24>;
456 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
459 interrupt-names = "error", "rx", "tx";
460 clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
461 power-domains = <&cpg_clocks>;
462 num-cs = <1>;
463 #address-cells = <1>;
464 #size-cells = <0>;
465 status = "disabled";
466 };
467
468 gic: interrupt-controller@e8201000 {
469 compatible = "arm,pl390";
470 #interrupt-cells = <3>;
471 #address-cells = <0>;
472 interrupt-controller;
473 reg = <0xe8201000 0x1000>,
474 <0xe8202000 0x1000>;
475 };
476
477 L2: cache-controller@3ffff000 {
478 compatible = "arm,pl310-cache";
479 reg = <0x3ffff000 0x1000>;
480 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
481 arm,early-bresp-disable;
482 arm,full-line-zero-disable;
483 cache-unified;
484 cache-level = <2>;
485 };
486
487 wdt: watchdog@fcfe0000 {
488 compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
489 reg = <0xfcfe0000 0x6>;
490 interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>;
491 clocks = <&p0_clk>;
492 };
493
494 i2c0: i2c@fcfee000 {
495 #address-cells = <1>;
496 #size-cells = <0>;
497 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
498 reg = <0xfcfee000 0x44>;
499 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
500 <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
501 <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
502 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
503 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
508 clock-frequency = <100000>;
509 power-domains = <&cpg_clocks>;
510 status = "disabled";
511 };
512
513 i2c1: i2c@fcfee400 {
514 #address-cells = <1>;
515 #size-cells = <0>;
516 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
517 reg = <0xfcfee400 0x44>;
518 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
520 <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
521 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
522 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
527 clock-frequency = <100000>;
528 power-domains = <&cpg_clocks>;
529 status = "disabled";
530 };
531
532 i2c2: i2c@fcfee800 {
533 #address-cells = <1>;
534 #size-cells = <0>;
535 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
536 reg = <0xfcfee800 0x44>;
537 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
539 <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
540 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
542 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
544 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
546 clock-frequency = <100000>;
547 power-domains = <&cpg_clocks>;
548 status = "disabled";
549 };
550
551 i2c3: i2c@fcfeec00 {
552 #address-cells = <1>;
553 #size-cells = <0>;
554 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
555 reg = <0xfcfeec00 0x44>;
556 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
558 <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
559 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
560 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
565 clock-frequency = <100000>;
566 power-domains = <&cpg_clocks>;
567 status = "disabled";
568 };
569
570 mtu2: timer@fcff0000 {
571 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
572 reg = <0xfcff0000 0x400>;
573 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
574 interrupt-names = "tgi0a";
575 clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
576 clock-names = "fck";
577 power-domains = <&cpg_clocks>;
578 status = "disabled";
579 };
580
581 ether: ethernet@e8203000 {
582 compatible = "renesas,ether-r7s72100";
583 reg = <0xe8203000 0x800>,
584 <0xe8204800 0x200>;
585 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
587 power-domains = <&cpg_clocks>;
588 phy-mode = "mii";
589 #address-cells = <1>;
590 #size-cells = <0>;
591 status = "disabled";
592 };
593
594 mmcif: mmc@e804c800 {
595 compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
596 reg = <0xe804c800 0x80>;
597 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
598 GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
599 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
601 power-domains = <&cpg_clocks>;
602 reg-io-width = <4>;
603 bus-width = <8>;
604 status = "disabled";
605 };
606
607 sdhi0: sd@e804e000 {
608 compatible = "renesas,sdhi-r7s72100";
609 reg = <0xe804e000 0x100>;
610 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
611 GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
612 GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
613
614 clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
615 <&mstp12_clks R7S72100_CLK_SDHI01>;
616 clock-names = "core", "cd";
617 power-domains = <&cpg_clocks>;
618 cap-sd-highspeed;
619 cap-sdio-irq;
620 status = "disabled";
621 };
622
623 sdhi1: sd@e804e800 {
624 compatible = "renesas,sdhi-r7s72100";
625 reg = <0xe804e800 0x100>;
626 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
627 GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
628 GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
629
630 clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
631 <&mstp12_clks R7S72100_CLK_SDHI11>;
632 clock-names = "core", "cd";
633 power-domains = <&cpg_clocks>;
634 cap-sd-highspeed;
635 cap-sdio-irq;
636 status = "disabled";
637 };
638
639 ostm0: timer@fcfec000 {
640 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
641 reg = <0xfcfec000 0x30>;
642 interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
643 clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
644 power-domains = <&cpg_clocks>;
645 status = "disabled";
646 };
647
648 ostm1: timer@fcfec400 {
649 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
650 reg = <0xfcfec400 0x30>;
651 interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
652 clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
653 power-domains = <&cpg_clocks>;
654 status = "disabled";
655 };
656
657 rtc: rtc@fcff1000 {
658 compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";
659 reg = <0xfcff1000 0x2e>;
660 interrupts = <GIC_SPI 276 IRQ_TYPE_EDGE_RISING
661 GIC_SPI 277 IRQ_TYPE_EDGE_RISING
662 GIC_SPI 278 IRQ_TYPE_EDGE_RISING>;
663 interrupt-names = "alarm", "period", "carry";
664 clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>,
665 <&rtc_x3_clk>, <&extal_clk>;
666 clock-names = "fck", "rtc_x1", "rtc_x3", "extal";
667 power-domains = <&cpg_clocks>;
668 status = "disabled";
669 };
670};