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1/*
2 * Copyright 2014 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <dt-bindings/gpio/gpio.h>
13
14/ {
15 /* these are used by bootloader for disabling nodes */
16 aliases {
17 led0 = &led0;
18 led1 = &led1;
19 led2 = &led2;
20 nand = &gpmi;
21 usb0 = &usbh1;
22 usb1 = &usbotg;
23 };
24
25 chosen {
26 bootargs = "console=ttymxc1,115200";
27 };
28
29 leds {
30 compatible = "gpio-leds";
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_gpio_leds>;
33
34 led0: user1 {
35 label = "user1";
36 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
37 default-state = "on";
38 linux,default-trigger = "heartbeat";
39 };
40
41 led1: user2 {
42 label = "user2";
43 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
44 default-state = "off";
45 };
46
47 led2: user3 {
48 label = "user3";
49 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
50 default-state = "off";
51 };
52 };
53
54 memory@10000000 {
55 reg = <0x10000000 0x20000000>;
56 };
57
58 reg_1p0v: regulator-1p0v {
59 compatible = "regulator-fixed";
60 regulator-name = "1P0V";
61 regulator-min-microvolt = <1000000>;
62 regulator-max-microvolt = <1000000>;
63 regulator-always-on;
64 };
65
66 reg_3p3v: regulator-3p3v {
67 compatible = "regulator-fixed";
68 regulator-name = "3P3V";
69 regulator-min-microvolt = <3300000>;
70 regulator-max-microvolt = <3300000>;
71 regulator-always-on;
72 };
73
74 reg_5p0v: regulator-5p0v {
75 compatible = "regulator-fixed";
76 regulator-name = "5P0V";
77 regulator-min-microvolt = <5000000>;
78 regulator-max-microvolt = <5000000>;
79 regulator-always-on;
80 };
81};
82
83&gpmi {
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_gpmi_nand>;
86 status = "okay";
87};
88
89&hdmi {
90 ddc-i2c-bus = <&i2c3>;
91 status = "okay";
92};
93
94&i2c1 {
95 clock-frequency = <100000>;
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_i2c1>;
98 status = "okay";
99
100 eeprom1: eeprom@50 {
101 compatible = "atmel,24c02";
102 reg = <0x50>;
103 pagesize = <16>;
104 };
105
106 eeprom2: eeprom@51 {
107 compatible = "atmel,24c02";
108 reg = <0x51>;
109 pagesize = <16>;
110 };
111
112 eeprom3: eeprom@52 {
113 compatible = "atmel,24c02";
114 reg = <0x52>;
115 pagesize = <16>;
116 };
117
118 eeprom4: eeprom@53 {
119 compatible = "atmel,24c02";
120 reg = <0x53>;
121 pagesize = <16>;
122 };
123
124 gpio: pca9555@23 {
125 compatible = "nxp,pca9555";
126 reg = <0x23>;
127 gpio-controller;
128 #gpio-cells = <2>;
129 };
130
131 rtc: ds1672@68 {
132 compatible = "dallas,ds1672";
133 reg = <0x68>;
134 };
135};
136
137&i2c2 {
138 clock-frequency = <100000>;
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_i2c2>;
141 status = "okay";
142
143 ltc3676: pmic@3c {
144 compatible = "lltc,ltc3676";
145 reg = <0x3c>;
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_pmic>;
148 interrupt-parent = <&gpio1>;
149 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
150
151 regulators {
152 /* VDD_SOC (1+R1/R2 = 1.635) */
153 reg_vdd_soc: sw1 {
154 regulator-name = "vddsoc";
155 regulator-min-microvolt = <674400>;
156 regulator-max-microvolt = <1308000>;
157 lltc,fb-voltage-divider = <127000 200000>;
158 regulator-ramp-delay = <7000>;
159 regulator-boot-on;
160 regulator-always-on;
161 };
162
163 /* VDD_1P8 (1+R1/R2 = 2.505): ENET-PHY */
164 reg_1p8v: sw2 {
165 regulator-name = "vdd1p8";
166 regulator-min-microvolt = <1033310>;
167 regulator-max-microvolt = <2004000>;
168 lltc,fb-voltage-divider = <301000 200000>;
169 regulator-ramp-delay = <7000>;
170 regulator-boot-on;
171 regulator-always-on;
172 };
173
174 /* VDD_ARM (1+R1/R2 = 1.635) */
175 reg_vdd_arm: sw3 {
176 regulator-name = "vddarm";
177 regulator-min-microvolt = <674400>;
178 regulator-max-microvolt = <1308000>;
179 lltc,fb-voltage-divider = <127000 200000>;
180 regulator-ramp-delay = <7000>;
181 regulator-boot-on;
182 regulator-always-on;
183 };
184
185 /* VDD_DDR (1+R1/R2 = 2.105) */
186 reg_vdd_ddr: sw4 {
187 regulator-name = "vddddr";
188 regulator-min-microvolt = <868310>;
189 regulator-max-microvolt = <1684000>;
190 lltc,fb-voltage-divider = <221000 200000>;
191 regulator-ramp-delay = <7000>;
192 regulator-boot-on;
193 regulator-always-on;
194 };
195
196 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
197 reg_2p5v: ldo2 {
198 regulator-name = "vdd2p5";
199 regulator-min-microvolt = <2490375>;
200 regulator-max-microvolt = <2490375>;
201 lltc,fb-voltage-divider = <487000 200000>;
202 regulator-boot-on;
203 regulator-always-on;
204 };
205
206 /* VDD_HIGH (1+R1/R2 = 4.17) */
207 reg_3p0v: ldo4 {
208 regulator-name = "vdd3p0";
209 regulator-min-microvolt = <3023250>;
210 regulator-max-microvolt = <3023250>;
211 lltc,fb-voltage-divider = <634000 200000>;
212 regulator-boot-on;
213 regulator-always-on;
214 };
215 };
216 };
217};
218
219&i2c3 {
220 clock-frequency = <100000>;
221 pinctrl-names = "default";
222 pinctrl-0 = <&pinctrl_i2c3>;
223 status = "okay";
224};
225
226&pcie {
227 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_pcie>;
229 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
230 status = "okay";
231};
232
233&pwm2 {
234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
236 status = "disabled";
237};
238
239&pwm3 {
240 pinctrl-names = "default";
241 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
242 status = "disabled";
243};
244
245&uart2 {
246 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_uart2>;
248 status = "okay";
249};
250
251&uart3 {
252 pinctrl-names = "default";
253 pinctrl-0 = <&pinctrl_uart3>;
254 status = "okay";
255};
256
257&uart5 {
258 pinctrl-names = "default";
259 pinctrl-0 = <&pinctrl_uart5>;
260 status = "okay"; };
261
262&usbh1 {
263 status = "okay";
264};
265
266&wdog1 {
267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_wdog>;
269 fsl,ext-reset-output;
270};
271
272&iomuxc {
273 pinctrl_gpio_leds: gpioledsgrp {
274 fsl,pins = <
275 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
276 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
277 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
278 >;
279 };
280
281 pinctrl_gpmi_nand: gpminandgrp {
282 fsl,pins = <
283 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
284 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
285 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
286 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
287 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
288 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
289 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
290 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
291 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
292 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
293 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
294 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
295 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
296 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
297 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
298 >;
299 };
300
301 pinctrl_i2c1: i2c1grp {
302 fsl,pins = <
303 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
304 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
305 >;
306 };
307
308 pinctrl_i2c2: i2c2grp {
309 fsl,pins = <
310 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
311 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
312 >;
313 };
314
315 pinctrl_i2c3: i2c3grp {
316 fsl,pins = <
317 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
318 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
319 >;
320 };
321
322 pinctrl_pcie: pciegrp {
323 fsl,pins = <
324 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
325 >;
326 };
327
328 pinctrl_pmic: pmicgrp {
329 fsl,pins = <
330 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
331 >;
332 };
333
334 pinctrl_pwm2: pwm2grp {
335 fsl,pins = <
336 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
337 >;
338 };
339
340 pinctrl_pwm3: pwm3grp {
341 fsl,pins = <
342 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
343 >;
344 };
345
346 pinctrl_uart2: uart2grp {
347 fsl,pins = <
348 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
349 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
350 >;
351 };
352
353 pinctrl_uart3: uart3grp {
354 fsl,pins = <
355 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
356 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
357 >;
358 };
359
360 pinctrl_uart5: uart5grp {
361 fsl,pins = <
362 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
363 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
364 >;
365 };
366
367 pinctrl_wdog: wdoggrp {
368 fsl,pins = <
369 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
370 >;
371 };
372};