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1/*
2 * Copyright 2015 Timesys Corporation.
3 * Copyright 2015 General Electric Company
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/dts-v1/;
44
45#include "imx6q-bx50v3.dtsi"
46
47/ {
48 model = "General Electric B850v3";
49 compatible = "ge,imx6q-b850v3", "advantech,imx6q-ba16", "fsl,imx6q";
50
51 chosen {
52 stdout-path = &uart3;
53 };
54};
55
56&clks {
57 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
58 <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
59 <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
60 <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
61 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
62 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
63 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
64 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
65};
66
67&ldb {
68 fsl,dual-channel;
69 status = "okay";
70
71 lvds0: lvds-channel@0 {
72 fsl,data-mapping = "spwg";
73 fsl,data-width = <24>;
74 status = "okay";
75
76 port@4 {
77 reg = <4>;
78
79 lvds0_out: endpoint {
80 remote-endpoint = <&stdp4028_in>;
81 };
82 };
83 };
84};
85
86&i2c2 {
87 pca9547_ddc: mux@70 {
88 compatible = "nxp,pca9547";
89 reg = <0x70>;
90 #address-cells = <1>;
91 #size-cells = <0>;
92
93 mux2_i2c1: i2c@0 {
94 #address-cells = <1>;
95 #size-cells = <0>;
96 reg = <0x0>;
97 };
98
99 mux2_i2c2: i2c@1 {
100 #address-cells = <1>;
101 #size-cells = <0>;
102 reg = <0x1>;
103 };
104
105 mux2_i2c3: i2c@2 {
106 #address-cells = <1>;
107 #size-cells = <0>;
108 reg = <0x2>;
109 };
110
111 mux2_i2c4: i2c@3 {
112 #address-cells = <1>;
113 #size-cells = <0>;
114 reg = <0x3>;
115 };
116
117 mux2_i2c5: i2c@4 {
118 #address-cells = <1>;
119 #size-cells = <0>;
120 reg = <0x4>;
121 };
122
123 mux2_i2c6: i2c@5 {
124 #address-cells = <1>;
125 #size-cells = <0>;
126 reg = <0x5>;
127 };
128
129 mux2_i2c7: i2c@6 {
130 #address-cells = <1>;
131 #size-cells = <0>;
132 reg = <0x6>;
133 };
134
135 mux2_i2c8: i2c@7 {
136 #address-cells = <1>;
137 #size-cells = <0>;
138 reg = <0x7>;
139 };
140 };
141};
142
143&hdmi {
144 ddc-i2c-bus = <&mux2_i2c1>;
145};
146
147&mux1_i2c1 {
148 ads7830@4a {
149 compatible = "ti,ads7830";
150 reg = <0x4a>;
151 };
152};
153
154&mux2_i2c2 {
155 clock-frequency = <100000>;
156
157 stdp2690@72 {
158 compatible = "megachips,stdp2690-ge-b850v3-fw";
159 #address-cells = <1>;
160 #size-cells = <0>;
161 reg = <0x72>;
162
163 ports {
164 #address-cells = <1>;
165 #size-cells = <0>;
166
167 port@0 {
168 reg = <0>;
169
170 stdp2690_in: endpoint {
171 remote-endpoint = <&stdp4028_out>;
172 };
173 };
174
175 port@1 {
176 reg = <1>;
177
178 stdp2690_out: endpoint {
179 /* Connector for external display */
180 };
181 };
182 };
183 };
184
185 stdp4028@73 {
186 compatible = "megachips,stdp4028-ge-b850v3-fw";
187 #address-cells = <1>;
188 #size-cells = <0>;
189 reg = <0x73>;
190 interrupt-parent = <&gpio2>;
191 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
192
193 ports {
194 #address-cells = <1>;
195 #size-cells = <0>;
196
197 port@0 {
198 reg = <0>;
199
200 stdp4028_in: endpoint {
201 remote-endpoint = <&lvds0_out>;
202 };
203 };
204
205 port@1 {
206 reg = <1>;
207
208 stdp4028_out: endpoint {
209 remote-endpoint = <&stdp2690_in>;
210 };
211 };
212 };
213 };
214};
215
216&pci_root {
217 /* PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch */
218 bridge@1,0 {
219 compatible = "pci10b5,8605";
220 reg = <0x00010000 0 0 0 0>;
221
222 #address-cells = <3>;
223 #size-cells = <2>;
224 #interrupt-cells = <1>;
225
226 bridge@2,1 {
227 compatible = "pci10b5,8605";
228 reg = <0x00020800 0 0 0 0>;
229
230 #address-cells = <3>;
231 #size-cells = <2>;
232 #interrupt-cells = <1>;
233
234 /* Intel Corporation I210 Gigabit Network Connection */
235 ethernet@3,0 {
236 compatible = "pci8086,1533";
237 reg = <0x00030000 0 0 0 0>;
238 };
239 };
240
241 bridge@2,2 {
242 compatible = "pci10b5,8605";
243 reg = <0x00021000 0 0 0 0>;
244
245 #address-cells = <3>;
246 #size-cells = <2>;
247 #interrupt-cells = <1>;
248
249 /* Intel Corporation I210 Gigabit Network Connection */
250 switch_nic: ethernet@4,0 {
251 compatible = "pci8086,1533";
252 reg = <0x00040000 0 0 0 0>;
253 };
254 };
255 };
256};
257
258&switch_ports {
259 port@0 {
260 reg = <0>;
261 label = "eneport1";
262 phy-handle = <&switchphy0>;
263 };
264
265 port@1 {
266 reg = <1>;
267 label = "eneport2";
268 phy-handle = <&switchphy1>;
269 };
270
271 port@2 {
272 reg = <2>;
273 label = "enix";
274 phy-handle = <&switchphy2>;
275 };
276
277 port@3 {
278 reg = <3>;
279 label = "enid";
280 phy-handle = <&switchphy3>;
281 };
282
283 port@4 {
284 reg = <4>;
285 label = "cpu";
286 ethernet = <&switch_nic>;
287 phy-handle = <&switchphy4>;
288 };
289};