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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SAMSUNG EXYNOS5440 SoC device tree source
4 *
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 */
8
9#include <dt-bindings/clock/exynos5440.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12
13/ {
14 compatible = "samsung,exynos5440", "samsung,exynos5";
15
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 serial0 = &serial_0;
22 serial1 = &serial_1;
23 spi0 = &spi_0;
24 tmuctrl0 = &tmuctrl_0;
25 tmuctrl1 = &tmuctrl_1;
26 tmuctrl2 = &tmuctrl_2;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu@0 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a15";
36 reg = <0>;
37 };
38 cpu@1 {
39 device_type = "cpu";
40 compatible = "arm,cortex-a15";
41 reg = <1>;
42 };
43 cpu@2 {
44 device_type = "cpu";
45 compatible = "arm,cortex-a15";
46 reg = <2>;
47 };
48 cpu@3 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a15";
51 reg = <3>;
52 };
53 };
54
55 soc: soc {
56 compatible = "simple-bus";
57 #address-cells = <1>;
58 #size-cells = <1>;
59 ranges;
60
61 clock: clock-controller@160000 {
62 compatible = "samsung,exynos5440-clock";
63 reg = <0x160000 0x1000>;
64 #clock-cells = <1>;
65 };
66
67 gic: interrupt-controller@2e0000 {
68 compatible = "arm,cortex-a15-gic";
69 #interrupt-cells = <3>;
70 interrupt-controller;
71 reg = <0x2E1000 0x1000>,
72 <0x2E2000 0x2000>,
73 <0x2E4000 0x2000>,
74 <0x2E6000 0x2000>;
75 interrupts = <GIC_PPI 9
76 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
77 };
78
79
80 arm-pmu {
81 compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
82 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
86 };
87
88 timer {
89 compatible = "arm,cortex-a15-timer",
90 "arm,armv7-timer";
91 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
93 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
94 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
95 clock-frequency = <50000000>;
96 };
97
98 cpufreq@160000 {
99 compatible = "samsung,exynos5440-cpufreq";
100 reg = <0x160000 0x1000>;
101 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
102 operating-points = <
103 /* KHz uV */
104 1500000 1100000
105 1400000 1075000
106 1300000 1050000
107 1200000 1025000
108 1100000 1000000
109 1000000 975000
110 900000 950000
111 800000 925000
112 >;
113 };
114
115 serial_0: serial@b0000 {
116 compatible = "samsung,exynos4210-uart";
117 reg = <0xB0000 0x1000>;
118 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
119 clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
120 clock-names = "uart", "clk_uart_baud0";
121 };
122
123 serial_1: serial@c0000 {
124 compatible = "samsung,exynos4210-uart";
125 reg = <0xC0000 0x1000>;
126 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
127 clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
128 clock-names = "uart", "clk_uart_baud0";
129 };
130
131 spi_0: spi@d0000 {
132 compatible = "samsung,exynos5440-spi";
133 reg = <0xD0000 0x100>;
134 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
135 #address-cells = <1>;
136 #size-cells = <0>;
137 samsung,spi-src-clk = <0>;
138 num-cs = <1>;
139 clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>;
140 clock-names = "spi", "spi_busclk0";
141 };
142
143 pin_ctrl: pinctrl@e0000 {
144 compatible = "samsung,exynos5440-pinctrl";
145 reg = <0xE0000 0x1000>;
146 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
154 interrupt-controller;
155 #interrupt-cells = <2>;
156 #gpio-cells = <2>;
157
158 fan: fan {
159 samsung,exynos5440-pin-function = <1>;
160 };
161
162 hdd_led0: hdd_led0 {
163 samsung,exynos5440-pin-function = <2>;
164 };
165
166 hdd_led1: hdd_led1 {
167 samsung,exynos5440-pin-function = <3>;
168 };
169
170 uart1: uart1 {
171 samsung,exynos5440-pin-function = <4>;
172 };
173 };
174
175 i2c@f0000 {
176 compatible = "samsung,exynos5440-i2c";
177 reg = <0xF0000 0x1000>;
178 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
179 #address-cells = <1>;
180 #size-cells = <0>;
181 clocks = <&clock CLK_B_125>;
182 clock-names = "i2c";
183 };
184
185 i2c@100000 {
186 compatible = "samsung,exynos5440-i2c";
187 reg = <0x100000 0x1000>;
188 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
189 #address-cells = <1>;
190 #size-cells = <0>;
191 clocks = <&clock CLK_B_125>;
192 clock-names = "i2c";
193 };
194
195 watchdog@110000 {
196 compatible = "samsung,s3c6410-wdt";
197 reg = <0x110000 0x1000>;
198 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
199 clocks = <&clock CLK_B_125>;
200 clock-names = "watchdog";
201 };
202
203 gmac: ethernet@230000 {
204 compatible = "snps,dwmac-3.70a", "snps,dwmac";
205 reg = <0x00230000 0x8000>;
206 interrupt-parent = <&gic>;
207 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
208 interrupt-names = "macirq";
209 phy-mode = "sgmii";
210 clocks = <&clock CLK_GMAC0>;
211 clock-names = "stmmaceth";
212 };
213
214 amba {
215 #address-cells = <1>;
216 #size-cells = <1>;
217 compatible = "simple-bus";
218 interrupt-parent = <&gic>;
219 ranges;
220 };
221
222 rtc@130000 {
223 compatible = "samsung,s3c6410-rtc";
224 reg = <0x130000 0x1000>;
225 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&clock CLK_B_125>;
228 clock-names = "rtc";
229 };
230
231 tmuctrl_0: tmuctrl@160118 {
232 compatible = "samsung,exynos5440-tmu";
233 reg = <0x160118 0x230>, <0x160368 0x10>;
234 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
235 clocks = <&clock CLK_B_125>;
236 clock-names = "tmu_apbif";
237 #include "exynos5440-tmu-sensor-conf.dtsi"
238 };
239
240 tmuctrl_1: tmuctrl@16011c {
241 compatible = "samsung,exynos5440-tmu";
242 reg = <0x16011C 0x230>, <0x160368 0x10>;
243 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&clock CLK_B_125>;
245 clock-names = "tmu_apbif";
246 #include "exynos5440-tmu-sensor-conf.dtsi"
247 };
248
249 tmuctrl_2: tmuctrl@160120 {
250 compatible = "samsung,exynos5440-tmu";
251 reg = <0x160120 0x230>, <0x160368 0x10>;
252 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&clock CLK_B_125>;
254 clock-names = "tmu_apbif";
255 #include "exynos5440-tmu-sensor-conf.dtsi"
256 };
257
258 sata@210000 {
259 compatible = "snps,exynos5440-ahci";
260 reg = <0x210000 0x10000>;
261 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&clock CLK_SATA>;
263 clock-names = "sata";
264 };
265
266 ohci@220000 {
267 compatible = "samsung,exynos5440-ohci";
268 reg = <0x220000 0x1000>;
269 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&clock CLK_USB>;
271 clock-names = "usbhost";
272 };
273
274 ehci@221000 {
275 compatible = "samsung,exynos5440-ehci";
276 reg = <0x221000 0x1000>;
277 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
278 clocks = <&clock CLK_USB>;
279 clock-names = "usbhost";
280 };
281
282 pcie_phy0: pcie-phy@270000 {
283 #phy-cells = <0>;
284 compatible = "samsung,exynos5440-pcie-phy";
285 reg = <0x270000 0x1000>, <0x271000 0x40>;
286 };
287
288 pcie_phy1: pcie-phy@272000 {
289 #phy-cells = <0>;
290 compatible = "samsung,exynos5440-pcie-phy";
291 reg = <0x272000 0x1000>, <0x271040 0x40>;
292 };
293
294 pcie_0: pcie@290000 {
295 compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
296 reg = <0x290000 0x1000>, <0x40000000 0x1000>;
297 reg-names = "elbi", "config";
298 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
302 clock-names = "pcie", "pcie_bus";
303 #address-cells = <3>;
304 #size-cells = <2>;
305 device_type = "pci";
306 phys = <&pcie_phy0>;
307 ranges = <0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
308 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
309 bus-range = <0x00 0xff>;
310 #interrupt-cells = <1>;
311 interrupt-map-mask = <0 0 0 0>;
312 interrupt-map = <0x0 0 &gic 53>;
313 num-lanes = <4>;
314 status = "disabled";
315 };
316
317 pcie_1: pcie@2a0000 {
318 compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
319 reg = <0x2a0000 0x1000>, <0x60000000 0x1000>;
320 reg-names = "elbi", "config";
321 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
325 clock-names = "pcie", "pcie_bus";
326 #address-cells = <3>;
327 #size-cells = <2>;
328 device_type = "pci";
329 phys = <&pcie_phy1>;
330 ranges = <0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
331 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
332 bus-range = <0x00 0xff>;
333 #interrupt-cells = <1>;
334 interrupt-map-mask = <0 0 0 0>;
335 interrupt-map = <0x0 0 &gic 56>;
336 num-lanes = <4>;
337 status = "disabled";
338 };
339 };
340
341 thermal-zones {
342 cpu0_thermal: cpu0-thermal {
343 thermal-sensors = <&tmuctrl_0>;
344 #include "exynos5440-trip-points.dtsi"
345 };
346 cpu1_thermal: cpu1-thermal {
347 thermal-sensors = <&tmuctrl_1>;
348 #include "exynos5440-trip-points.dtsi"
349 };
350 cpu2_thermal: cpu2-thermal {
351 thermal-sensors = <&tmuctrl_2>;
352 #include "exynos5440-trip-points.dtsi"
353 };
354 };
355};