1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2/*
  3 * Device Tree file for Marvell Armada 395 GP board
  4 *
  5 * Copyright (C) 2016 Marvell
  6 *
  7 * Grzegorz Jaszczyk <jaz@semihalf.com>
  8 */
  9
 10/dts-v1/;
 11#include "armada-395.dtsi"
 12
 13/ {
 14	model = "Marvell Armada 395 GP Board";
 15	compatible = "marvell,a395-gp", "marvell,armada395",
 16		     "marvell,armada390";
 17
 18	chosen {
 19		stdout-path = "serial0:115200n8";
 20	};
 21
 22	memory {
 23		device_type = "memory";
 24		reg = <0x00000000 0x40000000>; /* 1 GB */
 25	};
 26
 27	soc {
 28		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
 29			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
 30
 31		internal-regs {
 32			i2c@11000 {
 33				status = "okay";
 34				clock-frequency = <100000>;
 35
 36				eeprom@57 {
 37					compatible = "atmel,24c64";
 38					reg = <0x57>;
 39				};
 40			};
 41
 42			serial@12000 {
 43				/*
 44				 * Exported on the micro USB connector CON17
 45				 * through an FTDI
 46				 */
 47				status = "okay";
 48			};
 49
 50			/* CON1 */
 51			usb@58000 {
 52				status = "okay";
 53			};
 54
 55			/* CON2 */
 56			sata@a8000 {
 57				status = "okay";
 58			};
 59
 60			flash@d0000 {
 61				status = "okay";
 62				pinctrl-0 = <&nand_pins>;
 63				pinctrl-names = "default";
 64				num-cs = <1>;
 65				marvell,nand-keep-config;
 66				marvell,nand-enable-arbiter;
 67				nand-on-flash-bbt;
 68				nand-ecc-strength = <4>;
 69				nand-ecc-step-size = <512>;
 70
 71				partitions {
 72					compatible = "fixed-partitions";
 73					#address-cells = <1>;
 74					#size-cells = <1>;
 75
 76					partition@0 {
 77						label = "U-Boot";
 78						reg = <0x00000000 0x00600000>;
 79						read-only;
 80					};
 81
 82					partition@800000 {
 83						label = "uImage";
 84						reg = <0x00600000 0x00400000>;
 85						read-only;
 86					};
 87
 88					partition@1000000 {
 89						label = "Root";
 90						reg = <0x00a00000 0x3f600000>;
 91					};
 92				};
 93			};
 94
 95			/* CON18 */
 96			sdhci@d8000 {
 97				clock-frequency = <200000000>;
 98				broken-cd;
 99				wp-inverted;
100				bus-width = <8>;
101				status = "okay";
102				no-1-8-v;
103			};
104
105			/* CON4 */
106			usb3@f0000 {
107				status = "okay";
108			};
109		};
110
111		pcie {
112			status = "okay";
113
114			/*
115			 * The two PCIe units are accessible through
116			 * mini PCIe slot on the board.
117			 */
118
119			/* CON7 */
120			pcie@2,0 {
121				/* Port 1, Lane 0 */
122				status = "okay";
123			};
124
125			/* CON8 */
126			pcie@4,0 {
127				/* Port 3, Lane 0 */
128				status = "okay";
129			};
130		};
131	};
132};