1/*
  2 * Support for peripherals on the AXS10x mainboard (VDK version)
  3 *
  4 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
  5 *
  6 * This program is free software; you can redistribute it and/or modify
  7 * it under the terms of the GNU General Public License version 2 as
  8 * published by the Free Software Foundation.
  9 */
 10
 11/ {
 12	axs10x_mb_vdk {
 13		compatible = "simple-bus";
 14		#address-cells = <1>;
 15		#size-cells = <1>;
 16		ranges = <0x00000000 0xe0000000 0x10000000>;
 17		interrupt-parent = <&mb_intc>;
 18
 19		clocks {
 20			apbclk: apbclk {
 21				compatible = "fixed-clock";
 22				clock-frequency = <50000000>;
 23				#clock-cells = <0>;
 24			};
 25
 26			mmcclk: mmcclk {
 27				compatible = "fixed-clock";
 28				clock-frequency = <50000000>;
 29				#clock-cells = <0>;
 30			};
 31
 32			pguclk: pguclk {
 33				#clock-cells = <0>;
 34				compatible = "fixed-clock";
 35				clock-frequency = <25175000>;
 36			};
 37		};
 38
 39		ethernet@0x18000 {
 40			#interrupt-cells = <1>;
 41			compatible = "snps,dwmac";
 42			reg = < 0x18000 0x2000 >;
 43			interrupts = < 4 >;
 44			interrupt-names = "macirq";
 45			phy-mode = "rgmii";
 46			snps,phy-addr = < 0 >;  // VDK model phy address is 0
 47			snps,pbl = < 32 >;
 48			clocks = <&apbclk>;
 49			clock-names = "stmmaceth";
 50		};
 51
 52		ehci@0x40000 {
 53			compatible = "generic-ehci";
 54			reg = < 0x40000 0x100 >;
 55			interrupts = < 8 >;
 56		};
 57
 58		uart@0x20000 {
 59			compatible = "snps,dw-apb-uart";
 60			reg = <0x20000 0x100>;
 61			clock-frequency = <2403200>;
 62			interrupts = <17>;
 63			baud = <115200>;
 64			reg-shift = <2>;
 65			reg-io-width = <4>;
 66		};
 67
 68		uart@0x21000 {
 69			compatible = "snps,dw-apb-uart";
 70			reg = <0x21000 0x100>;
 71			clock-frequency = <2403200>;
 72			interrupts = <18>;
 73			baud = <115200>;
 74			reg-shift = <2>;
 75			reg-io-width = <4>;
 76		};
 77
 78		uart@0x22000 {
 79			compatible = "snps,dw-apb-uart";
 80			reg = <0x22000 0x100>;
 81			clock-frequency = <2403200>;
 82			interrupts = <19>;
 83			baud = <115200>;
 84			reg-shift = <2>;
 85			reg-io-width = <4>;
 86		};
 87
 88/* PGU output directly sent to virtual LCD screen; hdmi controller not modelled */
 89		pgu@17000 {
 90			compatible = "snps,arcpgu";
 91			reg = <0x17000 0x400>;
 92			clocks = <&pguclk>;
 93			clock-names = "pxlclk";
 94		};
 95
 96/* VDK has additional ps2 keyboard/mouse interface integrated in LCD screen model */
 97		ps2: ps2@e0017400 {
 98			compatible = "snps,arc_ps2";
 99			reg = <0x17400 0x14>;
100			interrupts = <5>;
101			interrupt-names = "arc_ps2_irq";
102		};
103
104		mmc@0x15000 {
105			compatible = "snps,dw-mshc";
106			reg = <0x15000 0x400>;
107			fifo-depth = <1024>;
108			card-detect-delay = <200>;
109			clocks = <&apbclk>, <&mmcclk>;
110			clock-names = "biu", "ciu";
111			interrupts = <7>;
112			bus-width = <4>;
113		};
114	};
115
116	/*
117	 * Embedded Vision subsystem UIO mappings; only relevant for EV VDK
118	 *
119	 * This node is intentionally put outside of MB above becase
120	 * it maps areas outside of MB's 0xEz-0xFz.
121	 */
122	uio_ev: uio@0xD0000000 {
123		compatible = "generic-uio";
124		reg = <0xD0000000 0x2000 0xD1000000 0x2000 0x90000000 0x10000000 0xC0000000 0x10000000>;
125		reg-names = "ev_gsa", "ev_ctrl", "ev_shared_mem", "ev_code_mem";
126		interrupt-parent = <&mb_intc>;
127		interrupts = <23>;
128	};
129};