1/*
  2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  3 * Copyright (c) 2013 Linaro Ltd.
  4 *
  5 * This program is free software; you can redistribute it and/or modify
  6 * it under the terms of the GNU General Public License version 2 as
  7 * published by the Free Software Foundation.
  8 *
  9 * Common Clock Framework support for all PLL's in Samsung platforms
 10*/
 11
 12#ifndef __SAMSUNG_CLK_PLL_H
 13#define __SAMSUNG_CLK_PLL_H
 14
 15enum samsung_pll_type {
 16	pll_2126,
 17	pll_3000,
 18	pll_35xx,
 19	pll_36xx,
 20	pll_2550,
 21	pll_2650,
 22	pll_4500,
 23	pll_4502,
 24	pll_4508,
 25	pll_4600,
 26	pll_4650,
 27	pll_4650c,
 28	pll_6552,
 29	pll_6552_s3c2416,
 30	pll_6553,
 31	pll_s3c2410_mpll,
 32	pll_s3c2410_upll,
 33	pll_s3c2440_mpll,
 34	pll_2550x,
 35	pll_2550xx,
 36	pll_2650x,
 37	pll_2650xx,
 38	pll_1450x,
 39	pll_1451x,
 40	pll_1452x,
 41	pll_1460x,
 42};
 43
 44#define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
 45	((u64)(_fin) * (BIT(_ks) * (_m) + (_k)) / BIT(_ks) / ((_p) << (_s)))
 46#define PLL_VALID_RATE(_fin, _fout, _m, _p, _s, _k, _ks) ((_fout) + \
 47	BUILD_BUG_ON_ZERO(PLL_RATE(_fin, _m, _p, _s, _k, _ks) != (_fout)))
 48
 49#define PLL_35XX_RATE(_fin, _rate, _m, _p, _s)			\
 50	{							\
 51		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
 52				_m, _p, _s, 0, 16),		\
 53		.mdiv	=	(_m),				\
 54		.pdiv	=	(_p),				\
 55		.sdiv	=	(_s),				\
 56	}
 57
 58#define PLL_S3C2410_MPLL_RATE(_fin, _rate, _m, _p, _s)		\
 59	{							\
 60		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
 61				_m + 8, _p + 2, _s, 0, 16),	\
 62		.mdiv	=	(_m),				\
 63		.pdiv	=	(_p),				\
 64		.sdiv	=	(_s),				\
 65	}
 66
 67#define PLL_S3C2440_MPLL_RATE(_fin, _rate, _m, _p, _s)		\
 68	{							\
 69		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
 70				2 * (_m + 8), _p + 2, _s, 0, 16), \
 71		.mdiv	=	(_m),				\
 72		.pdiv	=	(_p),				\
 73		.sdiv	=	(_s),				\
 74	}
 75
 76#define PLL_36XX_RATE(_fin, _rate, _m, _p, _s, _k)		\
 77	{							\
 78		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
 79				_m, _p, _s, _k, 16),		\
 80		.mdiv	=	(_m),				\
 81		.pdiv	=	(_p),				\
 82		.sdiv	=	(_s),				\
 83		.kdiv	=	(_k),				\
 84	}
 85
 86#define PLL_4508_RATE(_fin, _rate, _m, _p, _s, _afc)		\
 87	{							\
 88		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
 89				_m, _p, _s - 1, 0, 16),		\
 90		.mdiv	=	(_m),				\
 91		.pdiv	=	(_p),				\
 92		.sdiv	=	(_s),				\
 93		.afc	=	(_afc),				\
 94	}
 95
 96#define PLL_4600_RATE(_fin, _rate, _m, _p, _s, _k, _vsel)	\
 97	{							\
 98		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
 99				_m, _p, _s, _k, 16),		\
100		.mdiv	=	(_m),				\
101		.pdiv	=	(_p),				\
102		.sdiv	=	(_s),				\
103		.kdiv	=	(_k),				\
104		.vsel	=	(_vsel),			\
105	}
106
107#define PLL_4650_RATE(_fin, _rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \
108	{							\
109		.rate	=	PLL_VALID_RATE(_fin, _rate,	\
110				_m, _p, _s, _k, 10),		\
111		.mdiv	=	(_m),				\
112		.pdiv	=	(_p),				\
113		.sdiv	=	(_s),				\
114		.kdiv	=	(_k),				\
115		.mfr	=	(_mfr),				\
116		.mrr	=	(_mrr),				\
117		.vsel	=	(_vsel),			\
118	}
119
120/* NOTE: Rate table should be kept sorted in descending order. */
121
122struct samsung_pll_rate_table {
123	unsigned int rate;
124	unsigned int pdiv;
125	unsigned int mdiv;
126	unsigned int sdiv;
127	unsigned int kdiv;
128	unsigned int afc;
129	unsigned int mfr;
130	unsigned int mrr;
131	unsigned int vsel;
132};
133
134#endif /* __SAMSUNG_CLK_PLL_H */