1/* SPDX-License-Identifier: GPL-2.0 */
 2#ifndef _ASM_X86_PROCESSOR_FLAGS_H
 3#define _ASM_X86_PROCESSOR_FLAGS_H
 
 4
 5#include <uapi/asm/processor-flags.h>
 6#include <linux/mem_encrypt.h>
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 7
 8#ifdef CONFIG_VM86
 9#define X86_VM_MASK	X86_EFLAGS_VM
10#else
11#define X86_VM_MASK	0 /* No VM86 support */
12#endif
 
 
 
 
 
 
 
 
 
13
14/*
15 * CR3's layout varies depending on several things.
16 *
17 * If CR4.PCIDE is set (64-bit only), then CR3[11:0] is the address space ID.
18 * If PAE is enabled, then CR3[11:5] is part of the PDPT address
19 * (i.e. it's 32-byte aligned, not page-aligned) and CR3[4:0] is ignored.
20 * Otherwise (non-PAE, non-PCID), CR3[3] is PWT, CR3[4] is PCD, and
21 * CR3[2:0] and CR3[11:5] are ignored.
22 *
23 * In all cases, Linux puts zeros in the low ignored bits and in PWT and PCD.
24 *
25 * CR3[63] is always read as zero.  If CR4.PCIDE is set, then CR3[63] may be
26 * written as 1 to prevent the write to CR3 from flushing the TLB.
27 *
28 * On systems with SME, one bit (in a variable position!) is stolen to indicate
29 * that the top-level paging structure is encrypted.
30 *
31 * All of the remaining bits indicate the physical address of the top-level
32 * paging structure.
33 *
34 * CR3_ADDR_MASK is the mask used by read_cr3_pa().
35 */
36#ifdef CONFIG_X86_64
37/* Mask off the address space ID and SME encryption bits. */
38#define CR3_ADDR_MASK	__sme_clr(0x7FFFFFFFFFFFF000ull)
39#define CR3_PCID_MASK	0xFFFull
40#define CR3_NOFLUSH	BIT_ULL(63)
41
42#ifdef CONFIG_PAGE_TABLE_ISOLATION
43# define X86_CR3_PTI_PCID_USER_BIT	11
44#endif
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
45
46#else
47/*
48 * CR3_ADDR_MASK needs at least bits 31:5 set on PAE systems, and we save
49 * a tiny bit of code size by setting all the bits.
50 */
51#define CR3_ADDR_MASK	0xFFFFFFFFull
52#define CR3_PCID_MASK	0ull
53#define CR3_NOFLUSH	0
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
54#endif
55
56#endif /* _ASM_X86_PROCESSOR_FLAGS_H */

 
  1#ifndef _ASM_X86_PROCESSOR_FLAGS_H
  2#define _ASM_X86_PROCESSOR_FLAGS_H
  3/* Various flags defined: can be included from assembler. */
  4
  5/*
  6 * EFLAGS bits
  7 */
  8#define X86_EFLAGS_CF	0x00000001 /* Carry Flag */
  9#define X86_EFLAGS_PF	0x00000004 /* Parity Flag */
 10#define X86_EFLAGS_AF	0x00000010 /* Auxiliary carry Flag */
 11#define X86_EFLAGS_ZF	0x00000040 /* Zero Flag */
 12#define X86_EFLAGS_SF	0x00000080 /* Sign Flag */
 13#define X86_EFLAGS_TF	0x00000100 /* Trap Flag */
 14#define X86_EFLAGS_IF	0x00000200 /* Interrupt Flag */
 15#define X86_EFLAGS_DF	0x00000400 /* Direction Flag */
 16#define X86_EFLAGS_OF	0x00000800 /* Overflow Flag */
 17#define X86_EFLAGS_IOPL	0x00003000 /* IOPL mask */
 18#define X86_EFLAGS_NT	0x00004000 /* Nested Task */
 19#define X86_EFLAGS_RF	0x00010000 /* Resume Flag */
 20#define X86_EFLAGS_VM	0x00020000 /* Virtual Mode */
 21#define X86_EFLAGS_AC	0x00040000 /* Alignment Check */
 22#define X86_EFLAGS_VIF	0x00080000 /* Virtual Interrupt Flag */
 23#define X86_EFLAGS_VIP	0x00100000 /* Virtual Interrupt Pending */
 24#define X86_EFLAGS_ID	0x00200000 /* CPUID detection flag */
 25
 26/*
 27 * Basic CPU control in CR0
 28 */
 29#define X86_CR0_PE	0x00000001 /* Protection Enable */
 30#define X86_CR0_MP	0x00000002 /* Monitor Coprocessor */
 31#define X86_CR0_EM	0x00000004 /* Emulation */
 32#define X86_CR0_TS	0x00000008 /* Task Switched */
 33#define X86_CR0_ET	0x00000010 /* Extension Type */
 34#define X86_CR0_NE	0x00000020 /* Numeric Error */
 35#define X86_CR0_WP	0x00010000 /* Write Protect */
 36#define X86_CR0_AM	0x00040000 /* Alignment Mask */
 37#define X86_CR0_NW	0x20000000 /* Not Write-through */
 38#define X86_CR0_CD	0x40000000 /* Cache Disable */
 39#define X86_CR0_PG	0x80000000 /* Paging */
 40
 41/*
 42 * Paging options in CR3
 43 */
 44#define X86_CR3_PWT	0x00000008 /* Page Write Through */
 45#define X86_CR3_PCD	0x00000010 /* Page Cache Disable */
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 46
 47/*
 48 * Intel CPU features in CR4
 49 */
 50#define X86_CR4_VME	0x00000001 /* enable vm86 extensions */
 51#define X86_CR4_PVI	0x00000002 /* virtual interrupts flag enable */
 52#define X86_CR4_TSD	0x00000004 /* disable time stamp at ipl 3 */
 53#define X86_CR4_DE	0x00000008 /* enable debugging extensions */
 54#define X86_CR4_PSE	0x00000010 /* enable page size extensions */
 55#define X86_CR4_PAE	0x00000020 /* enable physical address extensions */
 56#define X86_CR4_MCE	0x00000040 /* Machine check enable */
 57#define X86_CR4_PGE	0x00000080 /* enable global pages */
 58#define X86_CR4_PCE	0x00000100 /* enable performance counters at ipl 3 */
 59#define X86_CR4_OSFXSR	0x00000200 /* enable fast FPU save and restore */
 60#define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
 61#define X86_CR4_VMXE	0x00002000 /* enable VMX virtualization */
 62#define X86_CR4_RDWRGSFS 0x00010000 /* enable RDWRGSFS support */
 63#define X86_CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */
 64#define X86_CR4_SMEP	0x00100000 /* enable SMEP support */
 65
 66/*
 67 * x86-64 Task Priority Register, CR8
 68 */
 69#define X86_CR8_TPR	0x0000000F /* task priority register */
 70
 71/*
 72 * AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h>
 73 */
 74
 
 75/*
 76 *      NSC/Cyrix CPU configuration register indexes
 
 77 */
 78#define CX86_PCR0	0x20
 79#define CX86_GCR	0xb8
 80#define CX86_CCR0	0xc0
 81#define CX86_CCR1	0xc1
 82#define CX86_CCR2	0xc2
 83#define CX86_CCR3	0xc3
 84#define CX86_CCR4	0xe8
 85#define CX86_CCR5	0xe9
 86#define CX86_CCR6	0xea
 87#define CX86_CCR7	0xeb
 88#define CX86_PCR1	0xf0
 89#define CX86_DIR0	0xfe
 90#define CX86_DIR1	0xff
 91#define CX86_ARR_BASE	0xc4
 92#define CX86_RCR_BASE	0xdc
 93
 94#ifdef __KERNEL__
 95#ifdef CONFIG_VM86
 96#define X86_VM_MASK	X86_EFLAGS_VM
 97#else
 98#define X86_VM_MASK	0 /* No VM86 support */
 99#endif
100#endif
101
102#endif /* _ASM_X86_PROCESSOR_FLAGS_H */