1/*
  2 * Copyright (C) 2013 Imagination Technologies
  3 * Author: Paul Burton <paul.burton@mips.com>
  4 *
  5 * This program is free software; you can redistribute it and/or modify it
  6 * under the terms of the GNU General Public License as published by the
  7 * Free Software Foundation;  either version 2 of the  License, or (at your
  8 * option) any later version.
  9 */
 10
 11#include <linux/cpu.h>
 12#include <linux/delay.h>
 13#include <linux/io.h>
 14#include <linux/sched/task_stack.h>
 15#include <linux/sched/hotplug.h>
 16#include <linux/slab.h>
 17#include <linux/smp.h>
 18#include <linux/types.h>
 19
 20#include <asm/bcache.h>
 21#include <asm/mips-cps.h>
 22#include <asm/mips_mt.h>
 23#include <asm/mipsregs.h>
 24#include <asm/pm-cps.h>
 25#include <asm/r4kcache.h>
 26#include <asm/smp-cps.h>
 27#include <asm/time.h>
 28#include <asm/uasm.h>
 29
 30static bool threads_disabled;
 31static DECLARE_BITMAP(core_power, NR_CPUS);
 32
 33struct core_boot_config *mips_cps_core_bootcfg;
 34
 35static int __init setup_nothreads(char *s)
 36{
 37	threads_disabled = true;
 38	return 0;
 39}
 40early_param("nothreads", setup_nothreads);
 41
 42static unsigned core_vpe_count(unsigned int cluster, unsigned core)
 43{
 44	if (threads_disabled)
 45		return 1;
 46
 47	return mips_cps_numvps(cluster, core);
 48}
 49
 50static void __init cps_smp_setup(void)
 51{
 52	unsigned int nclusters, ncores, nvpes, core_vpes;
 53	unsigned long core_entry;
 54	int cl, c, v;
 55
 56	/* Detect & record VPE topology */
 57	nvpes = 0;
 58	nclusters = mips_cps_numclusters();
 59	pr_info("%s topology ", cpu_has_mips_r6 ? "VP" : "VPE");
 60	for (cl = 0; cl < nclusters; cl++) {
 61		if (cl > 0)
 62			pr_cont(",");
 63		pr_cont("{");
 64
 65		ncores = mips_cps_numcores(cl);
 66		for (c = 0; c < ncores; c++) {
 67			core_vpes = core_vpe_count(cl, c);
 68
 69			if (c > 0)
 70				pr_cont(",");
 71			pr_cont("%u", core_vpes);
 72
 73			/* Use the number of VPEs in cluster 0 core 0 for smp_num_siblings */
 74			if (!cl && !c)
 75				smp_num_siblings = core_vpes;
 76
 77			for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
 78				cpu_set_cluster(&cpu_data[nvpes + v], cl);
 79				cpu_set_core(&cpu_data[nvpes + v], c);
 80				cpu_set_vpe_id(&cpu_data[nvpes + v], v);
 81			}
 82
 83			nvpes += core_vpes;
 84		}
 85
 86		pr_cont("}");
 87	}
 88	pr_cont(" total %u\n", nvpes);
 89
 90	/* Indicate present CPUs (CPU being synonymous with VPE) */
 91	for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) {
 92		set_cpu_possible(v, cpu_cluster(&cpu_data[v]) == 0);
 93		set_cpu_present(v, cpu_cluster(&cpu_data[v]) == 0);
 94		__cpu_number_map[v] = v;
 95		__cpu_logical_map[v] = v;
 96	}
 97
 98	/* Set a coherent default CCA (CWB) */
 99	change_c0_config(CONF_CM_CMASK, 0x5);
100
101	/* Core 0 is powered up (we're running on it) */
102	bitmap_set(core_power, 0, 1);
103
104	/* Initialise core 0 */
105	mips_cps_core_init();
106
107	/* Make core 0 coherent with everything */
108	write_gcr_cl_coherence(0xff);
109
110	if (mips_cm_revision() >= CM_REV_CM3) {
111		core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
112		write_gcr_bev_base(core_entry);
113	}
114
115#ifdef CONFIG_MIPS_MT_FPAFF
116	/* If we have an FPU, enroll ourselves in the FPU-full mask */
117	if (cpu_has_fpu)
118		cpumask_set_cpu(0, &mt_fpu_cpumask);
119#endif /* CONFIG_MIPS_MT_FPAFF */
120}
121
122static void __init cps_prepare_cpus(unsigned int max_cpus)
123{
124	unsigned ncores, core_vpes, c, cca;
125	bool cca_unsuitable, cores_limited;
126	u32 *entry_code;
127
128	mips_mt_set_cpuoptions();
129
130	/* Detect whether the CCA is unsuited to multi-core SMP */
131	cca = read_c0_config() & CONF_CM_CMASK;
132	switch (cca) {
133	case 0x4: /* CWBE */
134	case 0x5: /* CWB */
135		/* The CCA is coherent, multi-core is fine */
136		cca_unsuitable = false;
137		break;
138
139	default:
140		/* CCA is not coherent, multi-core is not usable */
141		cca_unsuitable = true;
142	}
143
144	/* Warn the user if the CCA prevents multi-core */
145	cores_limited = false;
146	if (cca_unsuitable || cpu_has_dc_aliases) {
147		for_each_present_cpu(c) {
148			if (cpus_are_siblings(smp_processor_id(), c))
149				continue;
150
151			set_cpu_present(c, false);
152			cores_limited = true;
153		}
154	}
155	if (cores_limited)
156		pr_warn("Using only one core due to %s%s%s\n",
157			cca_unsuitable ? "unsuitable CCA" : "",
158			(cca_unsuitable && cpu_has_dc_aliases) ? " & " : "",
159			cpu_has_dc_aliases ? "dcache aliasing" : "");
160
161	/*
162	 * Patch the start of mips_cps_core_entry to provide:
163	 *
164	 * s0 = kseg0 CCA
165	 */
166	entry_code = (u32 *)&mips_cps_core_entry;
167	uasm_i_addiu(&entry_code, 16, 0, cca);
168	blast_dcache_range((unsigned long)&mips_cps_core_entry,
169			   (unsigned long)entry_code);
170	bc_wback_inv((unsigned long)&mips_cps_core_entry,
171		     (void *)entry_code - (void *)&mips_cps_core_entry);
172	__sync();
173
174	/* Allocate core boot configuration structs */
175	ncores = mips_cps_numcores(0);
176	mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg),
177					GFP_KERNEL);
178	if (!mips_cps_core_bootcfg) {
179		pr_err("Failed to allocate boot config for %u cores\n", ncores);
180		goto err_out;
181	}
182
183	/* Allocate VPE boot configuration structs */
184	for (c = 0; c < ncores; c++) {
185		core_vpes = core_vpe_count(0, c);
186		mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes,
187				sizeof(*mips_cps_core_bootcfg[c].vpe_config),
188				GFP_KERNEL);
189		if (!mips_cps_core_bootcfg[c].vpe_config) {
190			pr_err("Failed to allocate %u VPE boot configs\n",
191			       core_vpes);
192			goto err_out;
193		}
194	}
195
196	/* Mark this CPU as booted */
197	atomic_set(&mips_cps_core_bootcfg[cpu_core(&current_cpu_data)].vpe_mask,
198		   1 << cpu_vpe_id(&current_cpu_data));
199
200	return;
201err_out:
202	/* Clean up allocations */
203	if (mips_cps_core_bootcfg) {
204		for (c = 0; c < ncores; c++)
205			kfree(mips_cps_core_bootcfg[c].vpe_config);
206		kfree(mips_cps_core_bootcfg);
207		mips_cps_core_bootcfg = NULL;
208	}
209
210	/* Effectively disable SMP by declaring CPUs not present */
211	for_each_possible_cpu(c) {
212		if (c == 0)
213			continue;
214		set_cpu_present(c, false);
215	}
216}
217
218static void boot_core(unsigned int core, unsigned int vpe_id)
219{
220	u32 stat, seq_state;
221	unsigned timeout;
222
223	/* Select the appropriate core */
224	mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
225
226	/* Set its reset vector */
227	write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
228
229	/* Ensure its coherency is disabled */
230	write_gcr_co_coherence(0);
231
232	/* Start it with the legacy memory map and exception base */
233	write_gcr_co_reset_ext_base(CM_GCR_Cx_RESET_EXT_BASE_UEB);
234
235	/* Ensure the core can access the GCRs */
236	set_gcr_access(1 << core);
237
238	if (mips_cpc_present()) {
239		/* Reset the core */
240		mips_cpc_lock_other(core);
241
242		if (mips_cm_revision() >= CM_REV_CM3) {
243			/* Run only the requested VP following the reset */
244			write_cpc_co_vp_stop(0xf);
245			write_cpc_co_vp_run(1 << vpe_id);
246
247			/*
248			 * Ensure that the VP_RUN register is written before the
249			 * core leaves reset.
250			 */
251			wmb();
252		}
253
254		write_cpc_co_cmd(CPC_Cx_CMD_RESET);
255
256		timeout = 100;
257		while (true) {
258			stat = read_cpc_co_stat_conf();
259			seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE;
260			seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
261
262			/* U6 == coherent execution, ie. the core is up */
263			if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U6)
264				break;
265
266			/* Delay a little while before we start warning */
267			if (timeout) {
268				timeout--;
269				mdelay(10);
270				continue;
271			}
272
273			pr_warn("Waiting for core %u to start... STAT_CONF=0x%x\n",
274				core, stat);
275			mdelay(1000);
276		}
277
278		mips_cpc_unlock_other();
279	} else {
280		/* Take the core out of reset */
281		write_gcr_co_reset_release(0);
282	}
283
284	mips_cm_unlock_other();
285
286	/* The core is now powered up */
287	bitmap_set(core_power, core, 1);
288}
289
290static void remote_vpe_boot(void *dummy)
291{
292	unsigned core = cpu_core(&current_cpu_data);
293	struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
294
295	mips_cps_boot_vpes(core_cfg, cpu_vpe_id(&current_cpu_data));
296}
297
298static int cps_boot_secondary(int cpu, struct task_struct *idle)
299{
300	unsigned core = cpu_core(&cpu_data[cpu]);
301	unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
302	struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
303	struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
304	unsigned long core_entry;
305	unsigned int remote;
306	int err;
307
308	/* We don't yet support booting CPUs in other clusters */
309	if (cpu_cluster(&cpu_data[cpu]) != cpu_cluster(&raw_current_cpu_data))
310		return -ENOSYS;
311
312	vpe_cfg->pc = (unsigned long)&smp_bootstrap;
313	vpe_cfg->sp = __KSTK_TOS(idle);
314	vpe_cfg->gp = (unsigned long)task_thread_info(idle);
315
316	atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);
317
318	preempt_disable();
319
320	if (!test_bit(core, core_power)) {
321		/* Boot a VPE on a powered down core */
322		boot_core(core, vpe_id);
323		goto out;
324	}
325
326	if (cpu_has_vp) {
327		mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
328		core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
329		write_gcr_co_reset_base(core_entry);
330		mips_cm_unlock_other();
331	}
332
333	if (!cpus_are_siblings(cpu, smp_processor_id())) {
334		/* Boot a VPE on another powered up core */
335		for (remote = 0; remote < NR_CPUS; remote++) {
336			if (!cpus_are_siblings(cpu, remote))
337				continue;
338			if (cpu_online(remote))
339				break;
340		}
341		if (remote >= NR_CPUS) {
342			pr_crit("No online CPU in core %u to start CPU%d\n",
343				core, cpu);
344			goto out;
345		}
346
347		err = smp_call_function_single(remote, remote_vpe_boot,
348					       NULL, 1);
349		if (err)
350			panic("Failed to call remote CPU\n");
351		goto out;
352	}
353
354	BUG_ON(!cpu_has_mipsmt && !cpu_has_vp);
355
356	/* Boot a VPE on this core */
357	mips_cps_boot_vpes(core_cfg, vpe_id);
358out:
359	preempt_enable();
360	return 0;
361}
362
363static void cps_init_secondary(void)
364{
365	/* Disable MT - we only want to run 1 TC per VPE */
366	if (cpu_has_mipsmt)
367		dmt();
368
369	if (mips_cm_revision() >= CM_REV_CM3) {
370		unsigned int ident = read_gic_vl_ident();
371
372		/*
373		 * Ensure that our calculation of the VP ID matches up with
374		 * what the GIC reports, otherwise we'll have configured
375		 * interrupts incorrectly.
376		 */
377		BUG_ON(ident != mips_cm_vp_id(smp_processor_id()));
378	}
379
380	if (cpu_has_veic)
381		clear_c0_status(ST0_IM);
382	else
383		change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
384					 STATUSF_IP4 | STATUSF_IP5 |
385					 STATUSF_IP6 | STATUSF_IP7);
386}
387
388static void cps_smp_finish(void)
389{
390	write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
391
392#ifdef CONFIG_MIPS_MT_FPAFF
393	/* If we have an FPU, enroll ourselves in the FPU-full mask */
394	if (cpu_has_fpu)
395		cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
396#endif /* CONFIG_MIPS_MT_FPAFF */
397
398	local_irq_enable();
399}
400
401#ifdef CONFIG_HOTPLUG_CPU
402
403static int cps_cpu_disable(void)
404{
405	unsigned cpu = smp_processor_id();
406	struct core_boot_config *core_cfg;
407
408	if (!cpu)
409		return -EBUSY;
410
411	if (!cps_pm_support_state(CPS_PM_POWER_GATED))
412		return -EINVAL;
413
414	core_cfg = &mips_cps_core_bootcfg[cpu_core(&current_cpu_data)];
415	atomic_sub(1 << cpu_vpe_id(&current_cpu_data), &core_cfg->vpe_mask);
416	smp_mb__after_atomic();
417	set_cpu_online(cpu, false);
418	calculate_cpu_foreign_map();
419
420	return 0;
421}
422
423static unsigned cpu_death_sibling;
424static enum {
425	CPU_DEATH_HALT,
426	CPU_DEATH_POWER,
427} cpu_death;
428
429void play_dead(void)
430{
431	unsigned int cpu, core, vpe_id;
432
433	local_irq_disable();
434	idle_task_exit();
435	cpu = smp_processor_id();
436	core = cpu_core(&cpu_data[cpu]);
437	cpu_death = CPU_DEATH_POWER;
438
439	pr_debug("CPU%d going offline\n", cpu);
440
441	if (cpu_has_mipsmt || cpu_has_vp) {
442		/* Look for another online VPE within the core */
443		for_each_online_cpu(cpu_death_sibling) {
444			if (!cpus_are_siblings(cpu, cpu_death_sibling))
445				continue;
446
447			/*
448			 * There is an online VPE within the core. Just halt
449			 * this TC and leave the core alone.
450			 */
451			cpu_death = CPU_DEATH_HALT;
452			break;
453		}
454	}
455
456	/* This CPU has chosen its way out */
457	(void)cpu_report_death();
458
459	if (cpu_death == CPU_DEATH_HALT) {
460		vpe_id = cpu_vpe_id(&cpu_data[cpu]);
461
462		pr_debug("Halting core %d VP%d\n", core, vpe_id);
463		if (cpu_has_mipsmt) {
464			/* Halt this TC */
465			write_c0_tchalt(TCHALT_H);
466			instruction_hazard();
467		} else if (cpu_has_vp) {
468			write_cpc_cl_vp_stop(1 << vpe_id);
469
470			/* Ensure that the VP_STOP register is written */
471			wmb();
472		}
473	} else {
474		pr_debug("Gating power to core %d\n", core);
475		/* Power down the core */
476		cps_pm_enter_state(CPS_PM_POWER_GATED);
477	}
478
479	/* This should never be reached */
480	panic("Failed to offline CPU %u", cpu);
481}
482
483static void wait_for_sibling_halt(void *ptr_cpu)
484{
485	unsigned cpu = (unsigned long)ptr_cpu;
486	unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
487	unsigned halted;
488	unsigned long flags;
489
490	do {
491		local_irq_save(flags);
492		settc(vpe_id);
493		halted = read_tc_c0_tchalt();
494		local_irq_restore(flags);
495	} while (!(halted & TCHALT_H));
496}
497
498static void cps_cpu_die(unsigned int cpu)
499{
500	unsigned core = cpu_core(&cpu_data[cpu]);
501	unsigned int vpe_id = cpu_vpe_id(&cpu_data[cpu]);
502	ktime_t fail_time;
503	unsigned stat;
504	int err;
505
506	/* Wait for the cpu to choose its way out */
507	if (!cpu_wait_death(cpu, 5)) {
508		pr_err("CPU%u: didn't offline\n", cpu);
509		return;
510	}
511
512	/*
513	 * Now wait for the CPU to actually offline. Without doing this that
514	 * offlining may race with one or more of:
515	 *
516	 *   - Onlining the CPU again.
517	 *   - Powering down the core if another VPE within it is offlined.
518	 *   - A sibling VPE entering a non-coherent state.
519	 *
520	 * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing
521	 * with which we could race, so do nothing.
522	 */
523	if (cpu_death == CPU_DEATH_POWER) {
524		/*
525		 * Wait for the core to enter a powered down or clock gated
526		 * state, the latter happening when a JTAG probe is connected
527		 * in which case the CPC will refuse to power down the core.
528		 */
529		fail_time = ktime_add_ms(ktime_get(), 2000);
530		do {
531			mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
532			mips_cpc_lock_other(core);
533			stat = read_cpc_co_stat_conf();
534			stat &= CPC_Cx_STAT_CONF_SEQSTATE;
535			stat >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
536			mips_cpc_unlock_other();
537			mips_cm_unlock_other();
538
539			if (stat == CPC_Cx_STAT_CONF_SEQSTATE_D0 ||
540			    stat == CPC_Cx_STAT_CONF_SEQSTATE_D2 ||
541			    stat == CPC_Cx_STAT_CONF_SEQSTATE_U2)
542				break;
543
544			/*
545			 * The core ought to have powered down, but didn't &
546			 * now we don't really know what state it's in. It's
547			 * likely that its _pwr_up pin has been wired to logic
548			 * 1 & it powered back up as soon as we powered it
549			 * down...
550			 *
551			 * The best we can do is warn the user & continue in
552			 * the hope that the core is doing nothing harmful &
553			 * might behave properly if we online it later.
554			 */
555			if (WARN(ktime_after(ktime_get(), fail_time),
556				 "CPU%u hasn't powered down, seq. state %u\n",
557				 cpu, stat))
558				break;
559		} while (1);
560
561		/* Indicate the core is powered off */
562		bitmap_clear(core_power, core, 1);
563	} else if (cpu_has_mipsmt) {
564		/*
565		 * Have a CPU with access to the offlined CPUs registers wait
566		 * for its TC to halt.
567		 */
568		err = smp_call_function_single(cpu_death_sibling,
569					       wait_for_sibling_halt,
570					       (void *)(unsigned long)cpu, 1);
571		if (err)
572			panic("Failed to call remote sibling CPU\n");
573	} else if (cpu_has_vp) {
574		do {
575			mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
576			stat = read_cpc_co_vp_running();
577			mips_cm_unlock_other();
578		} while (stat & (1 << vpe_id));
579	}
580}
581
582#endif /* CONFIG_HOTPLUG_CPU */
583
584static const struct plat_smp_ops cps_smp_ops = {
585	.smp_setup		= cps_smp_setup,
586	.prepare_cpus		= cps_prepare_cpus,
587	.boot_secondary		= cps_boot_secondary,
588	.init_secondary		= cps_init_secondary,
589	.smp_finish		= cps_smp_finish,
590	.send_ipi_single	= mips_smp_send_ipi_single,
591	.send_ipi_mask		= mips_smp_send_ipi_mask,
592#ifdef CONFIG_HOTPLUG_CPU
593	.cpu_disable		= cps_cpu_disable,
594	.cpu_die		= cps_cpu_die,
595#endif
596};
597
598bool mips_cps_smp_in_use(void)
599{
600	extern const struct plat_smp_ops *mp_ops;
601	return mp_ops == &cps_smp_ops;
602}
603
604int register_cps_smp_ops(void)
605{
606	if (!mips_cm_present()) {
607		pr_warn("MIPS CPS SMP unable to proceed without a CM\n");
608		return -ENODEV;
609	}
610
611	/* check we have a GIC - we need one for IPIs */
612	if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX)) {
613		pr_warn("MIPS CPS SMP unable to proceed without a GIC\n");
614		return -ENODEV;
615	}
616
617	register_smp_ops(&cps_smp_ops);
618	return 0;
619}