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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 */
6#ifndef _ASM_PCI_H
7#define _ASM_PCI_H
8
9#include <linux/mm.h>
10
11#ifdef __KERNEL__
12
13/*
14 * This file essentially defines the interface between board
15 * specific PCI code and MIPS common PCI code. Should potentially put
16 * into include/asm/pci.h file.
17 */
18
19#include <linux/ioport.h>
20#include <linux/list.h>
21#include <linux/of.h>
22
23#ifdef CONFIG_PCI_DRIVERS_LEGACY
24
25/*
26 * Each pci channel is a top-level PCI bus seem by CPU. A machine with
27 * multiple PCI channels may have multiple PCI host controllers or a
28 * single controller supporting multiple channels.
29 */
30struct pci_controller {
31 struct list_head list;
32 struct pci_bus *bus;
33 struct device_node *of_node;
34
35 struct pci_ops *pci_ops;
36 struct resource *mem_resource;
37 unsigned long mem_offset;
38 struct resource *io_resource;
39 unsigned long io_offset;
40 unsigned long io_map_base;
41 struct resource *busn_resource;
42
43#ifndef CONFIG_PCI_DOMAINS_GENERIC
44 unsigned int index;
45 /* For compatibility with current (as of July 2003) pciutils
46 and XFree86. Eventually will be removed. */
47 unsigned int need_domain_info;
48#endif
49
50 /* Optional access methods for reading/writing the bus number
51 of the PCI controller */
52 int (*get_busno)(void);
53 void (*set_busno)(int busno);
54};
55
56/*
57 * Used by boards to register their PCI busses before the actual scanning.
58 */
59extern void register_pci_controller(struct pci_controller *hose);
60
61/*
62 * board supplied pci irq fixup routine
63 */
64extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
65
66/* Do platform specific device initialization at pci_enable_device() time */
67extern int pcibios_plat_dev_init(struct pci_dev *dev);
68
69extern char * (*pcibios_plat_setup)(char *str);
70
71#ifdef CONFIG_OF
72/* this function parses memory ranges from a device node */
73extern void pci_load_of_ranges(struct pci_controller *hose,
74 struct device_node *node);
75#else
76static inline void pci_load_of_ranges(struct pci_controller *hose,
77 struct device_node *node) {}
78#endif
79
80#ifdef CONFIG_PCI_DOMAINS_GENERIC
81static inline void set_pci_need_domain_info(struct pci_controller *hose,
82 int need_domain_info)
83{
84 /* nothing to do */
85}
86#elif defined(CONFIG_PCI_DOMAINS)
87static inline void set_pci_need_domain_info(struct pci_controller *hose,
88 int need_domain_info)
89{
90 hose->need_domain_info = need_domain_info;
91}
92#endif /* CONFIG_PCI_DOMAINS */
93
94#endif
95
96/* Can be used to override the logic in pci_scan_bus for skipping
97 already-configured bus numbers - to be used for buggy BIOSes
98 or architectures with incomplete PCI setup by the loader */
99static inline unsigned int pcibios_assign_all_busses(void)
100{
101 return 1;
102}
103
104extern unsigned long PCIBIOS_MIN_IO;
105extern unsigned long PCIBIOS_MIN_MEM;
106
107#define PCIBIOS_MIN_CARDBUS_IO 0x4000
108
109#define HAVE_PCI_MMAP
110#define ARCH_GENERIC_PCI_MMAP_RESOURCE
111#define HAVE_ARCH_PCI_RESOURCE_TO_USER
112
113/*
114 * Dynamic DMA mapping stuff.
115 * MIPS has everything mapped statically.
116 */
117
118#include <linux/types.h>
119#include <linux/slab.h>
120#include <linux/scatterlist.h>
121#include <linux/string.h>
122#include <asm/io.h>
123
124/*
125 * The PCI address space does equal the physical memory address space.
126 * The networking and block device layers use this boolean for bounce
127 * buffer decisions.
128 */
129#define PCI_DMA_BUS_IS_PHYS (1)
130
131#ifdef CONFIG_PCI_DOMAINS_GENERIC
132static inline int pci_proc_domain(struct pci_bus *bus)
133{
134 return pci_domain_nr(bus);
135}
136#elif defined(CONFIG_PCI_DOMAINS)
137#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
138
139static inline int pci_proc_domain(struct pci_bus *bus)
140{
141 struct pci_controller *hose = bus->sysdata;
142 return hose->need_domain_info;
143}
144#endif /* CONFIG_PCI_DOMAINS */
145
146#endif /* __KERNEL__ */
147
148/* Do platform specific device initialization at pci_enable_device() time */
149extern int pcibios_plat_dev_init(struct pci_dev *dev);
150
151/* Chances are this interrupt is wired PC-style ... */
152static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
153{
154 return channel ? 15 : 14;
155}
156
157#endif /* _ASM_PCI_H */
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 */
6#ifndef _ASM_PCI_H
7#define _ASM_PCI_H
8
9#include <linux/mm.h>
10
11#ifdef __KERNEL__
12
13/*
14 * This file essentially defines the interface between board
15 * specific PCI code and MIPS common PCI code. Should potentially put
16 * into include/asm/pci.h file.
17 */
18
19#include <linux/ioport.h>
20
21/*
22 * Each pci channel is a top-level PCI bus seem by CPU. A machine with
23 * multiple PCI channels may have multiple PCI host controllers or a
24 * single controller supporting multiple channels.
25 */
26struct pci_controller {
27 struct pci_controller *next;
28 struct pci_bus *bus;
29
30 struct pci_ops *pci_ops;
31 struct resource *mem_resource;
32 unsigned long mem_offset;
33 struct resource *io_resource;
34 unsigned long io_offset;
35 unsigned long io_map_base;
36
37 unsigned int index;
38 /* For compatibility with current (as of July 2003) pciutils
39 and XFree86. Eventually will be removed. */
40 unsigned int need_domain_info;
41
42 int iommu;
43
44 /* Optional access methods for reading/writing the bus number
45 of the PCI controller */
46 int (*get_busno)(void);
47 void (*set_busno)(int busno);
48};
49
50/*
51 * Used by boards to register their PCI busses before the actual scanning.
52 */
53extern struct pci_controller * alloc_pci_controller(void);
54extern void register_pci_controller(struct pci_controller *hose);
55
56/*
57 * board supplied pci irq fixup routine
58 */
59extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
60
61
62/* Can be used to override the logic in pci_scan_bus for skipping
63 already-configured bus numbers - to be used for buggy BIOSes
64 or architectures with incomplete PCI setup by the loader */
65
66extern unsigned int pcibios_assign_all_busses(void);
67
68extern unsigned long PCIBIOS_MIN_IO;
69extern unsigned long PCIBIOS_MIN_MEM;
70
71#define PCIBIOS_MIN_CARDBUS_IO 0x4000
72
73extern void pcibios_set_master(struct pci_dev *dev);
74
75static inline void pcibios_penalize_isa_irq(int irq, int active)
76{
77 /* We don't do dynamic PCI IRQ allocation */
78}
79
80#define HAVE_PCI_MMAP
81
82extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
83 enum pci_mmap_state mmap_state, int write_combine);
84
85/*
86 * Dynamic DMA mapping stuff.
87 * MIPS has everything mapped statically.
88 */
89
90#include <linux/types.h>
91#include <linux/slab.h>
92#include <asm/scatterlist.h>
93#include <linux/string.h>
94#include <asm/io.h>
95
96struct pci_dev;
97
98/*
99 * The PCI address space does equal the physical memory address space. The
100 * networking and block device layers use this boolean for bounce buffer
101 * decisions. This is set if any hose does not have an IOMMU.
102 */
103extern unsigned int PCI_DMA_BUS_IS_PHYS;
104
105#ifdef CONFIG_PCI
106static inline void pci_dma_burst_advice(struct pci_dev *pdev,
107 enum pci_dma_burst_strategy *strat,
108 unsigned long *strategy_parameter)
109{
110 *strat = PCI_DMA_BURST_INFINITY;
111 *strategy_parameter = ~0UL;
112}
113#endif
114
115extern void pcibios_resource_to_bus(struct pci_dev *dev,
116 struct pci_bus_region *region, struct resource *res);
117
118extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
119 struct pci_bus_region *region);
120
121#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
122
123static inline int pci_proc_domain(struct pci_bus *bus)
124{
125 struct pci_controller *hose = bus->sysdata;
126 return hose->need_domain_info;
127}
128
129#endif /* __KERNEL__ */
130
131/* implement the pci_ DMA API in terms of the generic device dma_ one */
132#include <asm-generic/pci-dma-compat.h>
133
134/* Do platform specific device initialization at pci_enable_device() time */
135extern int pcibios_plat_dev_init(struct pci_dev *dev);
136
137/* Chances are this interrupt is wired PC-style ... */
138static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
139{
140 return channel ? 15 : 14;
141}
142
143#ifdef CONFIG_CPU_CAVIUM_OCTEON
144/* MSI arch hook for OCTEON */
145#define arch_setup_msi_irqs arch_setup_msi_irqs
146#endif
147
148extern int pci_probe_only;
149
150extern char * (*pcibios_plat_setup)(char *str);
151
152#endif /* _ASM_PCI_H */