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1/*
2 * Atheros AR71xx/AR724x/AR913x specific interrupt handling
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/irqchip.h>
19#include <linux/of_irq.h>
20
21#include <asm/irq_cpu.h>
22#include <asm/mipsregs.h>
23
24#include <asm/mach-ath79/ath79.h>
25#include <asm/mach-ath79/ar71xx_regs.h>
26#include "common.h"
27#include "machtypes.h"
28
29
30static void ar934x_ip2_irq_dispatch(struct irq_desc *desc)
31{
32 u32 status;
33
34 status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
35
36 if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
37 ath79_ddr_wb_flush(3);
38 generic_handle_irq(ATH79_IP2_IRQ(0));
39 } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
40 ath79_ddr_wb_flush(4);
41 generic_handle_irq(ATH79_IP2_IRQ(1));
42 } else {
43 spurious_interrupt();
44 }
45}
46
47static void ar934x_ip2_irq_init(void)
48{
49 int i;
50
51 for (i = ATH79_IP2_IRQ_BASE;
52 i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
53 irq_set_chip_and_handler(i, &dummy_irq_chip,
54 handle_level_irq);
55
56 irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
57}
58
59static void qca955x_ip2_irq_dispatch(struct irq_desc *desc)
60{
61 u32 status;
62
63 status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
64 status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL;
65
66 if (status == 0) {
67 spurious_interrupt();
68 return;
69 }
70
71 if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
72 /* TODO: flush DDR? */
73 generic_handle_irq(ATH79_IP2_IRQ(0));
74 }
75
76 if (status & QCA955X_EXT_INT_WMAC_ALL) {
77 /* TODO: flush DDR? */
78 generic_handle_irq(ATH79_IP2_IRQ(1));
79 }
80}
81
82static void qca955x_ip3_irq_dispatch(struct irq_desc *desc)
83{
84 u32 status;
85
86 status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
87 status &= QCA955X_EXT_INT_PCIE_RC2_ALL |
88 QCA955X_EXT_INT_USB1 |
89 QCA955X_EXT_INT_USB2;
90
91 if (status == 0) {
92 spurious_interrupt();
93 return;
94 }
95
96 if (status & QCA955X_EXT_INT_USB1) {
97 /* TODO: flush DDR? */
98 generic_handle_irq(ATH79_IP3_IRQ(0));
99 }
100
101 if (status & QCA955X_EXT_INT_USB2) {
102 /* TODO: flush DDR? */
103 generic_handle_irq(ATH79_IP3_IRQ(1));
104 }
105
106 if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) {
107 /* TODO: flush DDR? */
108 generic_handle_irq(ATH79_IP3_IRQ(2));
109 }
110}
111
112static void qca955x_irq_init(void)
113{
114 int i;
115
116 for (i = ATH79_IP2_IRQ_BASE;
117 i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
118 irq_set_chip_and_handler(i, &dummy_irq_chip,
119 handle_level_irq);
120
121 irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
122
123 for (i = ATH79_IP3_IRQ_BASE;
124 i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
125 irq_set_chip_and_handler(i, &dummy_irq_chip,
126 handle_level_irq);
127
128 irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
129}
130
131void __init arch_init_irq(void)
132{
133 unsigned irq_wb_chan2 = -1;
134 unsigned irq_wb_chan3 = -1;
135 bool misc_is_ar71xx;
136
137 if (mips_machtype == ATH79_MACH_GENERIC_OF) {
138 irqchip_init();
139 return;
140 }
141
142 if (soc_is_ar71xx() || soc_is_ar724x() ||
143 soc_is_ar913x() || soc_is_ar933x()) {
144 irq_wb_chan2 = 3;
145 irq_wb_chan3 = 2;
146 } else if (soc_is_ar934x()) {
147 irq_wb_chan3 = 2;
148 }
149
150 ath79_cpu_irq_init(irq_wb_chan2, irq_wb_chan3);
151
152 if (soc_is_ar71xx() || soc_is_ar913x())
153 misc_is_ar71xx = true;
154 else if (soc_is_ar724x() ||
155 soc_is_ar933x() ||
156 soc_is_ar934x() ||
157 soc_is_qca955x())
158 misc_is_ar71xx = false;
159 else
160 BUG();
161 ath79_misc_irq_init(
162 ath79_reset_base + AR71XX_RESET_REG_MISC_INT_STATUS,
163 ATH79_CPU_IRQ(6), ATH79_MISC_IRQ_BASE, misc_is_ar71xx);
164
165 if (soc_is_ar934x())
166 ar934x_ip2_irq_init();
167 else if (soc_is_qca955x())
168 qca955x_irq_init();
169}
1/*
2 * Atheros AR71xx/AR724x/AR913x specific interrupt handling
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/irq.h>
18
19#include <asm/irq_cpu.h>
20#include <asm/mipsregs.h>
21
22#include <asm/mach-ath79/ath79.h>
23#include <asm/mach-ath79/ar71xx_regs.h>
24#include "common.h"
25
26static unsigned int ath79_ip2_flush_reg;
27static unsigned int ath79_ip3_flush_reg;
28
29static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
30{
31 void __iomem *base = ath79_reset_base;
32 u32 pending;
33
34 pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) &
35 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
36
37 if (pending & MISC_INT_UART)
38 generic_handle_irq(ATH79_MISC_IRQ_UART);
39
40 else if (pending & MISC_INT_DMA)
41 generic_handle_irq(ATH79_MISC_IRQ_DMA);
42
43 else if (pending & MISC_INT_PERFC)
44 generic_handle_irq(ATH79_MISC_IRQ_PERFC);
45
46 else if (pending & MISC_INT_TIMER)
47 generic_handle_irq(ATH79_MISC_IRQ_TIMER);
48
49 else if (pending & MISC_INT_OHCI)
50 generic_handle_irq(ATH79_MISC_IRQ_OHCI);
51
52 else if (pending & MISC_INT_ERROR)
53 generic_handle_irq(ATH79_MISC_IRQ_ERROR);
54
55 else if (pending & MISC_INT_GPIO)
56 generic_handle_irq(ATH79_MISC_IRQ_GPIO);
57
58 else if (pending & MISC_INT_WDOG)
59 generic_handle_irq(ATH79_MISC_IRQ_WDOG);
60
61 else
62 spurious_interrupt();
63}
64
65static void ar71xx_misc_irq_unmask(struct irq_data *d)
66{
67 unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE;
68 void __iomem *base = ath79_reset_base;
69 u32 t;
70
71 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
72 __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
73
74 /* flush write */
75 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
76}
77
78static void ar71xx_misc_irq_mask(struct irq_data *d)
79{
80 unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE;
81 void __iomem *base = ath79_reset_base;
82 u32 t;
83
84 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
85 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
86
87 /* flush write */
88 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
89}
90
91static void ar724x_misc_irq_ack(struct irq_data *d)
92{
93 unsigned int irq = d->irq - ATH79_MISC_IRQ_BASE;
94 void __iomem *base = ath79_reset_base;
95 u32 t;
96
97 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
98 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
99
100 /* flush write */
101 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
102}
103
104static struct irq_chip ath79_misc_irq_chip = {
105 .name = "MISC",
106 .irq_unmask = ar71xx_misc_irq_unmask,
107 .irq_mask = ar71xx_misc_irq_mask,
108};
109
110static void __init ath79_misc_irq_init(void)
111{
112 void __iomem *base = ath79_reset_base;
113 int i;
114
115 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
116 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
117
118 if (soc_is_ar71xx() || soc_is_ar913x())
119 ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
120 else if (soc_is_ar724x())
121 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
122 else
123 BUG();
124
125 for (i = ATH79_MISC_IRQ_BASE;
126 i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) {
127 irq_set_chip_and_handler(i, &ath79_misc_irq_chip,
128 handle_level_irq);
129 }
130
131 irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler);
132}
133
134asmlinkage void plat_irq_dispatch(void)
135{
136 unsigned long pending;
137
138 pending = read_c0_status() & read_c0_cause() & ST0_IM;
139
140 if (pending & STATUSF_IP7)
141 do_IRQ(ATH79_CPU_IRQ_TIMER);
142
143 else if (pending & STATUSF_IP2) {
144 ath79_ddr_wb_flush(ath79_ip2_flush_reg);
145 do_IRQ(ATH79_CPU_IRQ_IP2);
146 }
147
148 else if (pending & STATUSF_IP4)
149 do_IRQ(ATH79_CPU_IRQ_GE0);
150
151 else if (pending & STATUSF_IP5)
152 do_IRQ(ATH79_CPU_IRQ_GE1);
153
154 else if (pending & STATUSF_IP3) {
155 ath79_ddr_wb_flush(ath79_ip3_flush_reg);
156 do_IRQ(ATH79_CPU_IRQ_USB);
157 }
158
159 else if (pending & STATUSF_IP6)
160 do_IRQ(ATH79_CPU_IRQ_MISC);
161
162 else
163 spurious_interrupt();
164}
165
166void __init arch_init_irq(void)
167{
168 if (soc_is_ar71xx()) {
169 ath79_ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI;
170 ath79_ip3_flush_reg = AR71XX_DDR_REG_FLUSH_USB;
171 } else if (soc_is_ar724x()) {
172 ath79_ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE;
173 ath79_ip3_flush_reg = AR724X_DDR_REG_FLUSH_USB;
174 } else if (soc_is_ar913x()) {
175 ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC;
176 ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB;
177 } else
178 BUG();
179
180 cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC;
181 mips_cpu_irq_init();
182 ath79_misc_irq_init();
183}