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1/*
2 * DaVinci Power Management Routines
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc. http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/pm.h>
12#include <linux/suspend.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/clk.h>
16#include <linux/spinlock.h>
17
18#include <asm/cacheflush.h>
19#include <asm/delay.h>
20#include <asm/io.h>
21
22#include <mach/common.h>
23#include <mach/da8xx.h>
24#include <mach/mux.h>
25#include <mach/pm.h>
26
27#include "clock.h"
28#include "psc.h"
29#include "sram.h"
30
31#define DA850_PLL1_BASE 0x01e1a000
32#define DEEPSLEEP_SLEEPCOUNT_MASK 0xFFFF
33#define DEEPSLEEP_SLEEPCOUNT 128
34
35static void (*davinci_sram_suspend) (struct davinci_pm_config *);
36static struct davinci_pm_config pm_config = {
37 .sleepcount = DEEPSLEEP_SLEEPCOUNT,
38 .ddrpsc_num = DA8XX_LPSC1_EMIF3C,
39};
40
41static void davinci_sram_push(void *dest, void *src, unsigned int size)
42{
43 memcpy(dest, src, size);
44 flush_icache_range((unsigned long)dest, (unsigned long)(dest + size));
45}
46
47static void davinci_pm_suspend(void)
48{
49 unsigned val;
50
51 if (pm_config.cpupll_reg_base != pm_config.ddrpll_reg_base) {
52
53 /* Switch CPU PLL to bypass mode */
54 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
55 val &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
56 __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
57
58 udelay(PLL_BYPASS_TIME);
59
60 /* Powerdown CPU PLL */
61 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
62 val |= PLLCTL_PLLPWRDN;
63 __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
64 }
65
66 /* Configure sleep count in deep sleep register */
67 val = __raw_readl(pm_config.deepsleep_reg);
68 val &= ~DEEPSLEEP_SLEEPCOUNT_MASK,
69 val |= pm_config.sleepcount;
70 __raw_writel(val, pm_config.deepsleep_reg);
71
72 /* System goes to sleep in this call */
73 davinci_sram_suspend(&pm_config);
74
75 if (pm_config.cpupll_reg_base != pm_config.ddrpll_reg_base) {
76
77 /* put CPU PLL in reset */
78 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
79 val &= ~PLLCTL_PLLRST;
80 __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
81
82 /* put CPU PLL in power down */
83 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
84 val &= ~PLLCTL_PLLPWRDN;
85 __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
86
87 /* wait for CPU PLL reset */
88 udelay(PLL_RESET_TIME);
89
90 /* bring CPU PLL out of reset */
91 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
92 val |= PLLCTL_PLLRST;
93 __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
94
95 /* Wait for CPU PLL to lock */
96 udelay(PLL_LOCK_TIME);
97
98 /* Remove CPU PLL from bypass mode */
99 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
100 val &= ~PLLCTL_PLLENSRC;
101 val |= PLLCTL_PLLEN;
102 __raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
103 }
104}
105
106static int davinci_pm_enter(suspend_state_t state)
107{
108 int ret = 0;
109
110 switch (state) {
111 case PM_SUSPEND_MEM:
112 davinci_pm_suspend();
113 break;
114 default:
115 ret = -EINVAL;
116 }
117
118 return ret;
119}
120
121static const struct platform_suspend_ops davinci_pm_ops = {
122 .enter = davinci_pm_enter,
123 .valid = suspend_valid_only_mem,
124};
125
126int __init davinci_pm_init(void)
127{
128 int ret;
129
130 ret = davinci_cfg_reg(DA850_RTC_ALARM);
131 if (ret)
132 return ret;
133
134 pm_config.ddr2_ctlr_base = da8xx_get_mem_ctlr();
135 pm_config.deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
136
137 pm_config.cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
138 if (!pm_config.cpupll_reg_base)
139 return -ENOMEM;
140
141 pm_config.ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K);
142 if (!pm_config.ddrpll_reg_base) {
143 ret = -ENOMEM;
144 goto no_ddrpll_mem;
145 }
146
147 pm_config.ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
148 if (!pm_config.ddrpsc_reg_base) {
149 ret = -ENOMEM;
150 goto no_ddrpsc_mem;
151 }
152
153 davinci_sram_suspend = sram_alloc(davinci_cpu_suspend_sz, NULL);
154 if (!davinci_sram_suspend) {
155 pr_err("PM: cannot allocate SRAM memory\n");
156 ret = -ENOMEM;
157 goto no_sram_mem;
158 }
159
160 davinci_sram_push(davinci_sram_suspend, davinci_cpu_suspend,
161 davinci_cpu_suspend_sz);
162
163 suspend_set_ops(&davinci_pm_ops);
164
165 return 0;
166
167no_sram_mem:
168 iounmap(pm_config.ddrpsc_reg_base);
169no_ddrpsc_mem:
170 iounmap(pm_config.ddrpll_reg_base);
171no_ddrpll_mem:
172 iounmap(pm_config.cpupll_reg_base);
173 return ret;
174}
1/*
2 * DaVinci Power Management Routines
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc. http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/pm.h>
12#include <linux/suspend.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/clk.h>
16#include <linux/spinlock.h>
17
18#include <asm/cacheflush.h>
19#include <asm/delay.h>
20#include <asm/io.h>
21
22#include <mach/da8xx.h>
23#include <mach/sram.h>
24#include <mach/pm.h>
25
26#include "clock.h"
27
28#define DEEPSLEEP_SLEEPCOUNT_MASK 0xFFFF
29
30static void (*davinci_sram_suspend) (struct davinci_pm_config *);
31static struct davinci_pm_config *pdata;
32
33static void davinci_sram_push(void *dest, void *src, unsigned int size)
34{
35 memcpy(dest, src, size);
36 flush_icache_range((unsigned long)dest, (unsigned long)(dest + size));
37}
38
39static void davinci_pm_suspend(void)
40{
41 unsigned val;
42
43 if (pdata->cpupll_reg_base != pdata->ddrpll_reg_base) {
44
45 /* Switch CPU PLL to bypass mode */
46 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
47 val &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
48 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
49
50 udelay(PLL_BYPASS_TIME);
51
52 /* Powerdown CPU PLL */
53 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
54 val |= PLLCTL_PLLPWRDN;
55 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
56 }
57
58 /* Configure sleep count in deep sleep register */
59 val = __raw_readl(pdata->deepsleep_reg);
60 val &= ~DEEPSLEEP_SLEEPCOUNT_MASK,
61 val |= pdata->sleepcount;
62 __raw_writel(val, pdata->deepsleep_reg);
63
64 /* System goes to sleep in this call */
65 davinci_sram_suspend(pdata);
66
67 if (pdata->cpupll_reg_base != pdata->ddrpll_reg_base) {
68
69 /* put CPU PLL in reset */
70 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
71 val &= ~PLLCTL_PLLRST;
72 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
73
74 /* put CPU PLL in power down */
75 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
76 val &= ~PLLCTL_PLLPWRDN;
77 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
78
79 /* wait for CPU PLL reset */
80 udelay(PLL_RESET_TIME);
81
82 /* bring CPU PLL out of reset */
83 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
84 val |= PLLCTL_PLLRST;
85 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
86
87 /* Wait for CPU PLL to lock */
88 udelay(PLL_LOCK_TIME);
89
90 /* Remove CPU PLL from bypass mode */
91 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
92 val &= ~PLLCTL_PLLENSRC;
93 val |= PLLCTL_PLLEN;
94 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
95 }
96}
97
98static int davinci_pm_enter(suspend_state_t state)
99{
100 int ret = 0;
101
102 switch (state) {
103 case PM_SUSPEND_STANDBY:
104 case PM_SUSPEND_MEM:
105 davinci_pm_suspend();
106 break;
107 default:
108 ret = -EINVAL;
109 }
110
111 return ret;
112}
113
114static const struct platform_suspend_ops davinci_pm_ops = {
115 .enter = davinci_pm_enter,
116 .valid = suspend_valid_only_mem,
117};
118
119static int __init davinci_pm_probe(struct platform_device *pdev)
120{
121 pdata = pdev->dev.platform_data;
122 if (!pdata) {
123 dev_err(&pdev->dev, "cannot get platform data\n");
124 return -ENOENT;
125 }
126
127 davinci_sram_suspend = sram_alloc(davinci_cpu_suspend_sz, NULL);
128 if (!davinci_sram_suspend) {
129 dev_err(&pdev->dev, "cannot allocate SRAM memory\n");
130 return -ENOMEM;
131 }
132
133 davinci_sram_push(davinci_sram_suspend, davinci_cpu_suspend,
134 davinci_cpu_suspend_sz);
135
136 suspend_set_ops(&davinci_pm_ops);
137
138 return 0;
139}
140
141static int __exit davinci_pm_remove(struct platform_device *pdev)
142{
143 sram_free(davinci_sram_suspend, davinci_cpu_suspend_sz);
144 return 0;
145}
146
147static struct platform_driver davinci_pm_driver = {
148 .driver = {
149 .name = "pm-davinci",
150 .owner = THIS_MODULE,
151 },
152 .remove = __exit_p(davinci_pm_remove),
153};
154
155static int __init davinci_pm_init(void)
156{
157 return platform_driver_probe(&davinci_pm_driver, davinci_pm_probe);
158}
159late_initcall(davinci_pm_init);