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1#ifndef MDP4_XML
2#define MDP4_XML
3
4/* Autogenerated file, DO NOT EDIT manually!
5
6This file was generated by the rules-ng-ng headergen tool in this git repository:
7http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git
9
10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
21- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
22
23Copyright (C) 2013-2015 by the following authors:
24- Rob Clark <robdclark@gmail.com> (robclark)
25- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26
27Permission is hereby granted, free of charge, to any person obtaining
28a copy of this software and associated documentation files (the
29"Software"), to deal in the Software without restriction, including
30without limitation the rights to use, copy, modify, merge, publish,
31distribute, sublicense, and/or sell copies of the Software, and to
32permit persons to whom the Software is furnished to do so, subject to
33the following conditions:
34
35The above copyright notice and this permission notice (including the
36next paragraph) shall be included in all copies or substantial
37portions of the Software.
38
39THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
41MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
42IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
43LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
44OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
45WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
46*/
47
48
49enum mdp4_pipe {
50 VG1 = 0,
51 VG2 = 1,
52 RGB1 = 2,
53 RGB2 = 3,
54 RGB3 = 4,
55 VG3 = 5,
56 VG4 = 6,
57};
58
59enum mdp4_mixer {
60 MIXER0 = 0,
61 MIXER1 = 1,
62 MIXER2 = 2,
63};
64
65enum mdp4_intf {
66 INTF_LCDC_DTV = 0,
67 INTF_DSI_VIDEO = 1,
68 INTF_DSI_CMD = 2,
69 INTF_EBI2_TV = 3,
70};
71
72enum mdp4_cursor_format {
73 CURSOR_ARGB = 1,
74 CURSOR_XRGB = 2,
75};
76
77enum mdp4_frame_format {
78 FRAME_LINEAR = 0,
79 FRAME_TILE_ARGB_4X4 = 1,
80 FRAME_TILE_YCBCR_420 = 2,
81};
82
83enum mdp4_scale_unit {
84 SCALE_FIR = 0,
85 SCALE_MN_PHASE = 1,
86 SCALE_PIXEL_RPT = 2,
87};
88
89enum mdp4_dma {
90 DMA_P = 0,
91 DMA_S = 1,
92 DMA_E = 2,
93};
94
95#define MDP4_IRQ_OVERLAY0_DONE 0x00000001
96#define MDP4_IRQ_OVERLAY1_DONE 0x00000002
97#define MDP4_IRQ_DMA_S_DONE 0x00000004
98#define MDP4_IRQ_DMA_E_DONE 0x00000008
99#define MDP4_IRQ_DMA_P_DONE 0x00000010
100#define MDP4_IRQ_VG1_HISTOGRAM 0x00000020
101#define MDP4_IRQ_VG2_HISTOGRAM 0x00000040
102#define MDP4_IRQ_PRIMARY_VSYNC 0x00000080
103#define MDP4_IRQ_PRIMARY_INTF_UDERRUN 0x00000100
104#define MDP4_IRQ_EXTERNAL_VSYNC 0x00000200
105#define MDP4_IRQ_EXTERNAL_INTF_UDERRUN 0x00000400
106#define MDP4_IRQ_PRIMARY_RDPTR 0x00000800
107#define MDP4_IRQ_DMA_P_HISTOGRAM 0x00020000
108#define MDP4_IRQ_DMA_S_HISTOGRAM 0x04000000
109#define MDP4_IRQ_OVERLAY2_DONE 0x40000000
110#define REG_MDP4_VERSION 0x00000000
111#define MDP4_VERSION_MINOR__MASK 0x00ff0000
112#define MDP4_VERSION_MINOR__SHIFT 16
113static inline uint32_t MDP4_VERSION_MINOR(uint32_t val)
114{
115 return ((val) << MDP4_VERSION_MINOR__SHIFT) & MDP4_VERSION_MINOR__MASK;
116}
117#define MDP4_VERSION_MAJOR__MASK 0xff000000
118#define MDP4_VERSION_MAJOR__SHIFT 24
119static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val)
120{
121 return ((val) << MDP4_VERSION_MAJOR__SHIFT) & MDP4_VERSION_MAJOR__MASK;
122}
123
124#define REG_MDP4_OVLP0_KICK 0x00000004
125
126#define REG_MDP4_OVLP1_KICK 0x00000008
127
128#define REG_MDP4_OVLP2_KICK 0x000000d0
129
130#define REG_MDP4_DMA_P_KICK 0x0000000c
131
132#define REG_MDP4_DMA_S_KICK 0x00000010
133
134#define REG_MDP4_DMA_E_KICK 0x00000014
135
136#define REG_MDP4_DISP_STATUS 0x00000018
137
138#define REG_MDP4_DISP_INTF_SEL 0x00000038
139#define MDP4_DISP_INTF_SEL_PRIM__MASK 0x00000003
140#define MDP4_DISP_INTF_SEL_PRIM__SHIFT 0
141static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val)
142{
143 return ((val) << MDP4_DISP_INTF_SEL_PRIM__SHIFT) & MDP4_DISP_INTF_SEL_PRIM__MASK;
144}
145#define MDP4_DISP_INTF_SEL_SEC__MASK 0x0000000c
146#define MDP4_DISP_INTF_SEL_SEC__SHIFT 2
147static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val)
148{
149 return ((val) << MDP4_DISP_INTF_SEL_SEC__SHIFT) & MDP4_DISP_INTF_SEL_SEC__MASK;
150}
151#define MDP4_DISP_INTF_SEL_EXT__MASK 0x00000030
152#define MDP4_DISP_INTF_SEL_EXT__SHIFT 4
153static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val)
154{
155 return ((val) << MDP4_DISP_INTF_SEL_EXT__SHIFT) & MDP4_DISP_INTF_SEL_EXT__MASK;
156}
157#define MDP4_DISP_INTF_SEL_DSI_VIDEO 0x00000040
158#define MDP4_DISP_INTF_SEL_DSI_CMD 0x00000080
159
160#define REG_MDP4_RESET_STATUS 0x0000003c
161
162#define REG_MDP4_READ_CNFG 0x0000004c
163
164#define REG_MDP4_INTR_ENABLE 0x00000050
165
166#define REG_MDP4_INTR_STATUS 0x00000054
167
168#define REG_MDP4_INTR_CLEAR 0x00000058
169
170#define REG_MDP4_EBI2_LCD0 0x00000060
171
172#define REG_MDP4_EBI2_LCD1 0x00000064
173
174#define REG_MDP4_PORTMAP_MODE 0x00000070
175
176#define REG_MDP4_CS_CONTROLLER0 0x000000c0
177
178#define REG_MDP4_CS_CONTROLLER1 0x000000c4
179
180#define REG_MDP4_LAYERMIXER2_IN_CFG 0x000100f0
181#define MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK 0x00000007
182#define MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT 0
183static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)
184{
185 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK;
186}
187#define MDP4_LAYERMIXER2_IN_CFG_PIPE0_MIXER1 0x00000008
188#define MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK 0x00000070
189#define MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT 4
190static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)
191{
192 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK;
193}
194#define MDP4_LAYERMIXER2_IN_CFG_PIPE1_MIXER1 0x00000080
195#define MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK 0x00000700
196#define MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT 8
197static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)
198{
199 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK;
200}
201#define MDP4_LAYERMIXER2_IN_CFG_PIPE2_MIXER1 0x00000800
202#define MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK 0x00007000
203#define MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT 12
204static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)
205{
206 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK;
207}
208#define MDP4_LAYERMIXER2_IN_CFG_PIPE3_MIXER1 0x00008000
209#define MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK 0x00070000
210#define MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT 16
211static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)
212{
213 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK;
214}
215#define MDP4_LAYERMIXER2_IN_CFG_PIPE4_MIXER1 0x00080000
216#define MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK 0x00700000
217#define MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT 20
218static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)
219{
220 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK;
221}
222#define MDP4_LAYERMIXER2_IN_CFG_PIPE5_MIXER1 0x00800000
223#define MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK 0x07000000
224#define MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT 24
225static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)
226{
227 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK;
228}
229#define MDP4_LAYERMIXER2_IN_CFG_PIPE6_MIXER1 0x08000000
230#define MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK 0x70000000
231#define MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT 28
232static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)
233{
234 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK;
235}
236#define MDP4_LAYERMIXER2_IN_CFG_PIPE7_MIXER1 0x80000000
237
238#define REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD 0x000100fc
239
240#define REG_MDP4_LAYERMIXER_IN_CFG 0x00010100
241#define MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK 0x00000007
242#define MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT 0
243static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)
244{
245 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK;
246}
247#define MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1 0x00000008
248#define MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK 0x00000070
249#define MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT 4
250static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)
251{
252 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK;
253}
254#define MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1 0x00000080
255#define MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK 0x00000700
256#define MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT 8
257static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)
258{
259 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK;
260}
261#define MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1 0x00000800
262#define MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK 0x00007000
263#define MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT 12
264static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)
265{
266 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK;
267}
268#define MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1 0x00008000
269#define MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK 0x00070000
270#define MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT 16
271static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)
272{
273 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK;
274}
275#define MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1 0x00080000
276#define MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK 0x00700000
277#define MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT 20
278static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)
279{
280 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK;
281}
282#define MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1 0x00800000
283#define MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK 0x07000000
284#define MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT 24
285static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)
286{
287 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK;
288}
289#define MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1 0x08000000
290#define MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK 0x70000000
291#define MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT 28
292static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)
293{
294 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK;
295}
296#define MDP4_LAYERMIXER_IN_CFG_PIPE7_MIXER1 0x80000000
297
298#define REG_MDP4_VG2_SRC_FORMAT 0x00030050
299
300#define REG_MDP4_VG2_CONST_COLOR 0x00031008
301
302#define REG_MDP4_OVERLAY_FLUSH 0x00018000
303#define MDP4_OVERLAY_FLUSH_OVLP0 0x00000001
304#define MDP4_OVERLAY_FLUSH_OVLP1 0x00000002
305#define MDP4_OVERLAY_FLUSH_VG1 0x00000004
306#define MDP4_OVERLAY_FLUSH_VG2 0x00000008
307#define MDP4_OVERLAY_FLUSH_RGB1 0x00000010
308#define MDP4_OVERLAY_FLUSH_RGB2 0x00000020
309
310static inline uint32_t __offset_OVLP(uint32_t idx)
311{
312 switch (idx) {
313 case 0: return 0x00010000;
314 case 1: return 0x00018000;
315 case 2: return 0x00088000;
316 default: return INVALID_IDX(idx);
317 }
318}
319static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); }
320
321static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); }
322
323static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); }
324#define MDP4_OVLP_SIZE_HEIGHT__MASK 0xffff0000
325#define MDP4_OVLP_SIZE_HEIGHT__SHIFT 16
326static inline uint32_t MDP4_OVLP_SIZE_HEIGHT(uint32_t val)
327{
328 return ((val) << MDP4_OVLP_SIZE_HEIGHT__SHIFT) & MDP4_OVLP_SIZE_HEIGHT__MASK;
329}
330#define MDP4_OVLP_SIZE_WIDTH__MASK 0x0000ffff
331#define MDP4_OVLP_SIZE_WIDTH__SHIFT 0
332static inline uint32_t MDP4_OVLP_SIZE_WIDTH(uint32_t val)
333{
334 return ((val) << MDP4_OVLP_SIZE_WIDTH__SHIFT) & MDP4_OVLP_SIZE_WIDTH__MASK;
335}
336
337static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); }
338
339static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); }
340
341static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { return 0x00000014 + __offset_OVLP(i0); }
342
343static inline uint32_t __offset_STAGE(uint32_t idx)
344{
345 switch (idx) {
346 case 0: return 0x00000104;
347 case 1: return 0x00000124;
348 case 2: return 0x00000144;
349 case 3: return 0x00000160;
350 default: return INVALID_IDX(idx);
351 }
352}
353static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); }
354
355static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); }
356#define MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK 0x00000003
357#define MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT 0
358static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val)
359{
360 return ((val) << MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK;
361}
362#define MDP4_OVLP_STAGE_OP_FG_INV_ALPHA 0x00000004
363#define MDP4_OVLP_STAGE_OP_FG_MOD_ALPHA 0x00000008
364#define MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK 0x00000030
365#define MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT 4
366static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val)
367{
368 return ((val) << MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK;
369}
370#define MDP4_OVLP_STAGE_OP_BG_INV_ALPHA 0x00000040
371#define MDP4_OVLP_STAGE_OP_BG_MOD_ALPHA 0x00000080
372#define MDP4_OVLP_STAGE_OP_FG_TRANSP 0x00000100
373#define MDP4_OVLP_STAGE_OP_BG_TRANSP 0x00000200
374
375static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_OVLP(i0) + __offset_STAGE(i1); }
376
377static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_OVLP(i0) + __offset_STAGE(i1); }
378
379static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_OVLP(i0) + __offset_STAGE(i1); }
380
381static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_OVLP(i0) + __offset_STAGE(i1); }
382
383static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_OVLP(i0) + __offset_STAGE(i1); }
384
385static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_OVLP(i0) + __offset_STAGE(i1); }
386
387static inline uint32_t __offset_STAGE_CO3(uint32_t idx)
388{
389 switch (idx) {
390 case 0: return 0x00001004;
391 case 1: return 0x00001404;
392 case 2: return 0x00001804;
393 case 3: return 0x00001b84;
394 default: return INVALID_IDX(idx);
395 }
396}
397static inline uint32_t REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); }
398
399static inline uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); }
400#define MDP4_OVLP_STAGE_CO3_SEL_FG_ALPHA 0x00000001
401
402static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0) { return 0x00000180 + __offset_OVLP(i0); }
403
404static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0) { return 0x00000184 + __offset_OVLP(i0); }
405
406static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0) { return 0x00000188 + __offset_OVLP(i0); }
407
408static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0) { return 0x0000018c + __offset_OVLP(i0); }
409
410static inline uint32_t REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0) { return 0x00000200 + __offset_OVLP(i0); }
411
412static inline uint32_t REG_MDP4_OVLP_CSC(uint32_t i0) { return 0x00002000 + __offset_OVLP(i0); }
413
414
415static inline uint32_t REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; }
416
417static inline uint32_t REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; }
418
419static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; }
420
421static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; }
422
423static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; }
424
425static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; }
426
427static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; }
428
429static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; }
430
431static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; }
432
433static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; }
434
435#define REG_MDP4_DMA_P_OP_MODE 0x00090070
436
437static inline uint32_t REG_MDP4_LUTN(uint32_t i0) { return 0x00094800 + 0x400*i0; }
438
439static inline uint32_t REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; }
440
441static inline uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; }
442
443#define REG_MDP4_DMA_S_OP_MODE 0x000a0028
444
445static inline uint32_t REG_MDP4_DMA_E_QUANT(uint32_t i0) { return 0x000b0070 + 0x4*i0; }
446
447static inline uint32_t __offset_DMA(enum mdp4_dma idx)
448{
449 switch (idx) {
450 case DMA_P: return 0x00090000;
451 case DMA_S: return 0x000a0000;
452 case DMA_E: return 0x000b0000;
453 default: return INVALID_IDX(idx);
454 }
455}
456static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }
457
458static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }
459#define MDP4_DMA_CONFIG_G_BPC__MASK 0x00000003
460#define MDP4_DMA_CONFIG_G_BPC__SHIFT 0
461static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val)
462{
463 return ((val) << MDP4_DMA_CONFIG_G_BPC__SHIFT) & MDP4_DMA_CONFIG_G_BPC__MASK;
464}
465#define MDP4_DMA_CONFIG_B_BPC__MASK 0x0000000c
466#define MDP4_DMA_CONFIG_B_BPC__SHIFT 2
467static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val)
468{
469 return ((val) << MDP4_DMA_CONFIG_B_BPC__SHIFT) & MDP4_DMA_CONFIG_B_BPC__MASK;
470}
471#define MDP4_DMA_CONFIG_R_BPC__MASK 0x00000030
472#define MDP4_DMA_CONFIG_R_BPC__SHIFT 4
473static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val)
474{
475 return ((val) << MDP4_DMA_CONFIG_R_BPC__SHIFT) & MDP4_DMA_CONFIG_R_BPC__MASK;
476}
477#define MDP4_DMA_CONFIG_PACK_ALIGN_MSB 0x00000080
478#define MDP4_DMA_CONFIG_PACK__MASK 0x0000ff00
479#define MDP4_DMA_CONFIG_PACK__SHIFT 8
480static inline uint32_t MDP4_DMA_CONFIG_PACK(uint32_t val)
481{
482 return ((val) << MDP4_DMA_CONFIG_PACK__SHIFT) & MDP4_DMA_CONFIG_PACK__MASK;
483}
484#define MDP4_DMA_CONFIG_DEFLKR_EN 0x01000000
485#define MDP4_DMA_CONFIG_DITHER_EN 0x01000000
486
487static inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { return 0x00000004 + __offset_DMA(i0); }
488#define MDP4_DMA_SRC_SIZE_HEIGHT__MASK 0xffff0000
489#define MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT 16
490static inline uint32_t MDP4_DMA_SRC_SIZE_HEIGHT(uint32_t val)
491{
492 return ((val) << MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT) & MDP4_DMA_SRC_SIZE_HEIGHT__MASK;
493}
494#define MDP4_DMA_SRC_SIZE_WIDTH__MASK 0x0000ffff
495#define MDP4_DMA_SRC_SIZE_WIDTH__SHIFT 0
496static inline uint32_t MDP4_DMA_SRC_SIZE_WIDTH(uint32_t val)
497{
498 return ((val) << MDP4_DMA_SRC_SIZE_WIDTH__SHIFT) & MDP4_DMA_SRC_SIZE_WIDTH__MASK;
499}
500
501static inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { return 0x00000008 + __offset_DMA(i0); }
502
503static inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { return 0x0000000c + __offset_DMA(i0); }
504
505static inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { return 0x00000010 + __offset_DMA(i0); }
506#define MDP4_DMA_DST_SIZE_HEIGHT__MASK 0xffff0000
507#define MDP4_DMA_DST_SIZE_HEIGHT__SHIFT 16
508static inline uint32_t MDP4_DMA_DST_SIZE_HEIGHT(uint32_t val)
509{
510 return ((val) << MDP4_DMA_DST_SIZE_HEIGHT__SHIFT) & MDP4_DMA_DST_SIZE_HEIGHT__MASK;
511}
512#define MDP4_DMA_DST_SIZE_WIDTH__MASK 0x0000ffff
513#define MDP4_DMA_DST_SIZE_WIDTH__SHIFT 0
514static inline uint32_t MDP4_DMA_DST_SIZE_WIDTH(uint32_t val)
515{
516 return ((val) << MDP4_DMA_DST_SIZE_WIDTH__SHIFT) & MDP4_DMA_DST_SIZE_WIDTH__MASK;
517}
518
519static inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { return 0x00000044 + __offset_DMA(i0); }
520#define MDP4_DMA_CURSOR_SIZE_WIDTH__MASK 0x0000007f
521#define MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT 0
522static inline uint32_t MDP4_DMA_CURSOR_SIZE_WIDTH(uint32_t val)
523{
524 return ((val) << MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT) & MDP4_DMA_CURSOR_SIZE_WIDTH__MASK;
525}
526#define MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK 0x007f0000
527#define MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT 16
528static inline uint32_t MDP4_DMA_CURSOR_SIZE_HEIGHT(uint32_t val)
529{
530 return ((val) << MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT) & MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK;
531}
532
533static inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) { return 0x00000048 + __offset_DMA(i0); }
534
535static inline uint32_t REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) { return 0x0000004c + __offset_DMA(i0); }
536#define MDP4_DMA_CURSOR_POS_X__MASK 0x0000ffff
537#define MDP4_DMA_CURSOR_POS_X__SHIFT 0
538static inline uint32_t MDP4_DMA_CURSOR_POS_X(uint32_t val)
539{
540 return ((val) << MDP4_DMA_CURSOR_POS_X__SHIFT) & MDP4_DMA_CURSOR_POS_X__MASK;
541}
542#define MDP4_DMA_CURSOR_POS_Y__MASK 0xffff0000
543#define MDP4_DMA_CURSOR_POS_Y__SHIFT 16
544static inline uint32_t MDP4_DMA_CURSOR_POS_Y(uint32_t val)
545{
546 return ((val) << MDP4_DMA_CURSOR_POS_Y__SHIFT) & MDP4_DMA_CURSOR_POS_Y__MASK;
547}
548
549static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) { return 0x00000060 + __offset_DMA(i0); }
550#define MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN 0x00000001
551#define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK 0x00000006
552#define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT 1
553static inline uint32_t MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val)
554{
555 return ((val) << MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT) & MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK;
556}
557#define MDP4_DMA_CURSOR_BLEND_CONFIG_TRANSP_EN 0x00000008
558
559static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) { return 0x00000064 + __offset_DMA(i0); }
560
561static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) { return 0x00000068 + __offset_DMA(i0); }
562
563static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) { return 0x0000006c + __offset_DMA(i0); }
564
565static inline uint32_t REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) { return 0x00001004 + __offset_DMA(i0); }
566
567static inline uint32_t REG_MDP4_DMA_CSC(enum mdp4_dma i0) { return 0x00003000 + __offset_DMA(i0); }
568
569
570static inline uint32_t REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; }
571
572static inline uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; }
573
574static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; }
575
576static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; }
577
578static inline uint32_t REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; }
579
580static inline uint32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; }
581
582static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; }
583
584static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; }
585
586static inline uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; }
587
588static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; }
589
590static inline uint32_t REG_MDP4_PIPE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }
591
592static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }
593#define MDP4_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000
594#define MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT 16
595static inline uint32_t MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val)
596{
597 return ((val) << MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SRC_SIZE_HEIGHT__MASK;
598}
599#define MDP4_PIPE_SRC_SIZE_WIDTH__MASK 0x0000ffff
600#define MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT 0
601static inline uint32_t MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val)
602{
603 return ((val) << MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SRC_SIZE_WIDTH__MASK;
604}
605
606static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) { return 0x00020004 + 0x10000*i0; }
607#define MDP4_PIPE_SRC_XY_Y__MASK 0xffff0000
608#define MDP4_PIPE_SRC_XY_Y__SHIFT 16
609static inline uint32_t MDP4_PIPE_SRC_XY_Y(uint32_t val)
610{
611 return ((val) << MDP4_PIPE_SRC_XY_Y__SHIFT) & MDP4_PIPE_SRC_XY_Y__MASK;
612}
613#define MDP4_PIPE_SRC_XY_X__MASK 0x0000ffff
614#define MDP4_PIPE_SRC_XY_X__SHIFT 0
615static inline uint32_t MDP4_PIPE_SRC_XY_X(uint32_t val)
616{
617 return ((val) << MDP4_PIPE_SRC_XY_X__SHIFT) & MDP4_PIPE_SRC_XY_X__MASK;
618}
619
620static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) { return 0x00020008 + 0x10000*i0; }
621#define MDP4_PIPE_DST_SIZE_HEIGHT__MASK 0xffff0000
622#define MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT 16
623static inline uint32_t MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val)
624{
625 return ((val) << MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_DST_SIZE_HEIGHT__MASK;
626}
627#define MDP4_PIPE_DST_SIZE_WIDTH__MASK 0x0000ffff
628#define MDP4_PIPE_DST_SIZE_WIDTH__SHIFT 0
629static inline uint32_t MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val)
630{
631 return ((val) << MDP4_PIPE_DST_SIZE_WIDTH__SHIFT) & MDP4_PIPE_DST_SIZE_WIDTH__MASK;
632}
633
634static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) { return 0x0002000c + 0x10000*i0; }
635#define MDP4_PIPE_DST_XY_Y__MASK 0xffff0000
636#define MDP4_PIPE_DST_XY_Y__SHIFT 16
637static inline uint32_t MDP4_PIPE_DST_XY_Y(uint32_t val)
638{
639 return ((val) << MDP4_PIPE_DST_XY_Y__SHIFT) & MDP4_PIPE_DST_XY_Y__MASK;
640}
641#define MDP4_PIPE_DST_XY_X__MASK 0x0000ffff
642#define MDP4_PIPE_DST_XY_X__SHIFT 0
643static inline uint32_t MDP4_PIPE_DST_XY_X(uint32_t val)
644{
645 return ((val) << MDP4_PIPE_DST_XY_X__SHIFT) & MDP4_PIPE_DST_XY_X__MASK;
646}
647
648static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) { return 0x00020010 + 0x10000*i0; }
649
650static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) { return 0x00020014 + 0x10000*i0; }
651
652static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { return 0x00020018 + 0x10000*i0; }
653
654static inline uint32_t REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0) { return 0x0002001c + 0x10000*i0; }
655
656static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { return 0x00020040 + 0x10000*i0; }
657#define MDP4_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff
658#define MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT 0
659static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val)
660{
661 return ((val) << MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P0__MASK;
662}
663#define MDP4_PIPE_SRC_STRIDE_A_P1__MASK 0xffff0000
664#define MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT 16
665static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val)
666{
667 return ((val) << MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P1__MASK;
668}
669
670static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) { return 0x00020044 + 0x10000*i0; }
671#define MDP4_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff
672#define MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT 0
673static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val)
674{
675 return ((val) << MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P2__MASK;
676}
677#define MDP4_PIPE_SRC_STRIDE_B_P3__MASK 0xffff0000
678#define MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT 16
679static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val)
680{
681 return ((val) << MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P3__MASK;
682}
683
684static inline uint32_t REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x10000*i0; }
685#define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK 0xffff0000
686#define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT 16
687static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(uint32_t val)
688{
689 return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK;
690}
691#define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK 0x0000ffff
692#define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT 0
693static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(uint32_t val)
694{
695 return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK;
696}
697
698static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0; }
699#define MDP4_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003
700#define MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT 0
701static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)
702{
703 return ((val) << MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_G_BPC__MASK;
704}
705#define MDP4_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c
706#define MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT 2
707static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)
708{
709 return ((val) << MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_B_BPC__MASK;
710}
711#define MDP4_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030
712#define MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT 4
713static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)
714{
715 return ((val) << MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_R_BPC__MASK;
716}
717#define MDP4_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0
718#define MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT 6
719static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)
720{
721 return ((val) << MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_A_BPC__MASK;
722}
723#define MDP4_PIPE_SRC_FORMAT_ALPHA_ENABLE 0x00000100
724#define MDP4_PIPE_SRC_FORMAT_CPP__MASK 0x00000600
725#define MDP4_PIPE_SRC_FORMAT_CPP__SHIFT 9
726static inline uint32_t MDP4_PIPE_SRC_FORMAT_CPP(uint32_t val)
727{
728 return ((val) << MDP4_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CPP__MASK;
729}
730#define MDP4_PIPE_SRC_FORMAT_ROTATED_90 0x00001000
731#define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK 0x00006000
732#define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT 13
733static inline uint32_t MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
734{
735 return ((val) << MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK;
736}
737#define MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT 0x00020000
738#define MDP4_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000
739#define MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK 0x00180000
740#define MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT 19
741static inline uint32_t MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(uint32_t val)
742{
743 return ((val) << MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT) & MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK;
744}
745#define MDP4_PIPE_SRC_FORMAT_SOLID_FILL 0x00400000
746#define MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK 0x0c000000
747#define MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT 26
748static inline uint32_t MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)
749{
750 return ((val) << MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK;
751}
752#define MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK 0x60000000
753#define MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT 29
754static inline uint32_t MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(enum mdp4_frame_format val)
755{
756 return ((val) << MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT) & MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK;
757}
758
759static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { return 0x00020054 + 0x10000*i0; }
760#define MDP4_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff
761#define MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT 0
762static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val)
763{
764 return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM0__MASK;
765}
766#define MDP4_PIPE_SRC_UNPACK_ELEM1__MASK 0x0000ff00
767#define MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT 8
768static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM1(uint32_t val)
769{
770 return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM1__MASK;
771}
772#define MDP4_PIPE_SRC_UNPACK_ELEM2__MASK 0x00ff0000
773#define MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT 16
774static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM2(uint32_t val)
775{
776 return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM2__MASK;
777}
778#define MDP4_PIPE_SRC_UNPACK_ELEM3__MASK 0xff000000
779#define MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT 24
780static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val)
781{
782 return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM3__MASK;
783}
784
785static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { return 0x00020058 + 0x10000*i0; }
786#define MDP4_PIPE_OP_MODE_SCALEX_EN 0x00000001
787#define MDP4_PIPE_OP_MODE_SCALEY_EN 0x00000002
788#define MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK 0x0000000c
789#define MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT 2
790static inline uint32_t MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(enum mdp4_scale_unit val)
791{
792 return ((val) << MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK;
793}
794#define MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK 0x00000030
795#define MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT 4
796static inline uint32_t MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(enum mdp4_scale_unit val)
797{
798 return ((val) << MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK;
799}
800#define MDP4_PIPE_OP_MODE_SRC_YCBCR 0x00000200
801#define MDP4_PIPE_OP_MODE_DST_YCBCR 0x00000400
802#define MDP4_PIPE_OP_MODE_CSC_EN 0x00000800
803#define MDP4_PIPE_OP_MODE_FLIP_LR 0x00002000
804#define MDP4_PIPE_OP_MODE_FLIP_UD 0x00004000
805#define MDP4_PIPE_OP_MODE_DITHER_EN 0x00008000
806#define MDP4_PIPE_OP_MODE_IGC_LUT_EN 0x00010000
807#define MDP4_PIPE_OP_MODE_DEINT_EN 0x00040000
808#define MDP4_PIPE_OP_MODE_DEINT_ODD_REF 0x00080000
809
810static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) { return 0x0002005c + 0x10000*i0; }
811
812static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) { return 0x00020060 + 0x10000*i0; }
813
814static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) { return 0x00021004 + 0x10000*i0; }
815
816static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) { return 0x00021008 + 0x10000*i0; }
817
818static inline uint32_t REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) { return 0x00024000 + 0x10000*i0; }
819
820
821static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; }
822
823static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; }
824
825static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; }
826
827static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; }
828
829static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; }
830
831static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; }
832
833static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; }
834
835static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; }
836
837static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; }
838
839static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; }
840
841#define REG_MDP4_LCDC 0x000c0000
842
843#define REG_MDP4_LCDC_ENABLE 0x000c0000
844
845#define REG_MDP4_LCDC_HSYNC_CTRL 0x000c0004
846#define MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
847#define MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT 0
848static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PULSEW(uint32_t val)
849{
850 return ((val) << MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK;
851}
852#define MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK 0xffff0000
853#define MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT 16
854static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PERIOD(uint32_t val)
855{
856 return ((val) << MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK;
857}
858
859#define REG_MDP4_LCDC_VSYNC_PERIOD 0x000c0008
860
861#define REG_MDP4_LCDC_VSYNC_LEN 0x000c000c
862
863#define REG_MDP4_LCDC_DISPLAY_HCTRL 0x000c0010
864#define MDP4_LCDC_DISPLAY_HCTRL_START__MASK 0x0000ffff
865#define MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT 0
866static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_START(uint32_t val)
867{
868 return ((val) << MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_START__MASK;
869}
870#define MDP4_LCDC_DISPLAY_HCTRL_END__MASK 0xffff0000
871#define MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT 16
872static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_END(uint32_t val)
873{
874 return ((val) << MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_END__MASK;
875}
876
877#define REG_MDP4_LCDC_DISPLAY_VSTART 0x000c0014
878
879#define REG_MDP4_LCDC_DISPLAY_VEND 0x000c0018
880
881#define REG_MDP4_LCDC_ACTIVE_HCTL 0x000c001c
882#define MDP4_LCDC_ACTIVE_HCTL_START__MASK 0x00007fff
883#define MDP4_LCDC_ACTIVE_HCTL_START__SHIFT 0
884static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_START(uint32_t val)
885{
886 return ((val) << MDP4_LCDC_ACTIVE_HCTL_START__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_START__MASK;
887}
888#define MDP4_LCDC_ACTIVE_HCTL_END__MASK 0x7fff0000
889#define MDP4_LCDC_ACTIVE_HCTL_END__SHIFT 16
890static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_END(uint32_t val)
891{
892 return ((val) << MDP4_LCDC_ACTIVE_HCTL_END__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_END__MASK;
893}
894#define MDP4_LCDC_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
895
896#define REG_MDP4_LCDC_ACTIVE_VSTART 0x000c0020
897
898#define REG_MDP4_LCDC_ACTIVE_VEND 0x000c0024
899
900#define REG_MDP4_LCDC_BORDER_CLR 0x000c0028
901
902#define REG_MDP4_LCDC_UNDERFLOW_CLR 0x000c002c
903#define MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
904#define MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT 0
905static inline uint32_t MDP4_LCDC_UNDERFLOW_CLR_COLOR(uint32_t val)
906{
907 return ((val) << MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK;
908}
909#define MDP4_LCDC_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
910
911#define REG_MDP4_LCDC_HSYNC_SKEW 0x000c0030
912
913#define REG_MDP4_LCDC_TEST_CNTL 0x000c0034
914
915#define REG_MDP4_LCDC_CTRL_POLARITY 0x000c0038
916#define MDP4_LCDC_CTRL_POLARITY_HSYNC_LOW 0x00000001
917#define MDP4_LCDC_CTRL_POLARITY_VSYNC_LOW 0x00000002
918#define MDP4_LCDC_CTRL_POLARITY_DATA_EN_LOW 0x00000004
919
920#define REG_MDP4_LCDC_LVDS_INTF_CTL 0x000c2000
921#define MDP4_LCDC_LVDS_INTF_CTL_MODE_SEL 0x00000004
922#define MDP4_LCDC_LVDS_INTF_CTL_RGB_OUT 0x00000008
923#define MDP4_LCDC_LVDS_INTF_CTL_CH_SWAP 0x00000010
924#define MDP4_LCDC_LVDS_INTF_CTL_CH1_RES_BIT 0x00000020
925#define MDP4_LCDC_LVDS_INTF_CTL_CH2_RES_BIT 0x00000040
926#define MDP4_LCDC_LVDS_INTF_CTL_ENABLE 0x00000080
927#define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE0_EN 0x00000100
928#define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE1_EN 0x00000200
929#define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE2_EN 0x00000400
930#define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE3_EN 0x00000800
931#define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE0_EN 0x00001000
932#define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE1_EN 0x00002000
933#define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE2_EN 0x00004000
934#define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE3_EN 0x00008000
935#define MDP4_LCDC_LVDS_INTF_CTL_CH1_CLK_LANE_EN 0x00010000
936#define MDP4_LCDC_LVDS_INTF_CTL_CH2_CLK_LANE_EN 0x00020000
937
938static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL(uint32_t i0) { return 0x000c2014 + 0x8*i0; }
939
940static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(uint32_t i0) { return 0x000c2014 + 0x8*i0; }
941#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__MASK 0x000000ff
942#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT 0
943static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(uint32_t val)
944{
945 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__MASK;
946}
947#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__MASK 0x0000ff00
948#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__SHIFT 8
949static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(uint32_t val)
950{
951 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__MASK;
952}
953#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__MASK 0x00ff0000
954#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__SHIFT 16
955static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(uint32_t val)
956{
957 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__MASK;
958}
959#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__MASK 0xff000000
960#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__SHIFT 24
961static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(uint32_t val)
962{
963 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__MASK;
964}
965
966static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(uint32_t i0) { return 0x000c2018 + 0x8*i0; }
967#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__MASK 0x000000ff
968#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT 0
969static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(uint32_t val)
970{
971 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__MASK;
972}
973#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__MASK 0x0000ff00
974#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__SHIFT 8
975static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(uint32_t val)
976{
977 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__MASK;
978}
979#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__MASK 0x00ff0000
980#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__SHIFT 16
981static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(uint32_t val)
982{
983 return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__MASK;
984}
985
986#define REG_MDP4_LCDC_LVDS_PHY_RESET 0x000c2034
987
988#define REG_MDP4_LVDS_PHY_PLL_CTRL_0 0x000c3000
989
990#define REG_MDP4_LVDS_PHY_PLL_CTRL_1 0x000c3004
991
992#define REG_MDP4_LVDS_PHY_PLL_CTRL_2 0x000c3008
993
994#define REG_MDP4_LVDS_PHY_PLL_CTRL_3 0x000c300c
995
996#define REG_MDP4_LVDS_PHY_PLL_CTRL_5 0x000c3014
997
998#define REG_MDP4_LVDS_PHY_PLL_CTRL_6 0x000c3018
999
1000#define REG_MDP4_LVDS_PHY_PLL_CTRL_7 0x000c301c
1001
1002#define REG_MDP4_LVDS_PHY_PLL_CTRL_8 0x000c3020
1003
1004#define REG_MDP4_LVDS_PHY_PLL_CTRL_9 0x000c3024
1005
1006#define REG_MDP4_LVDS_PHY_PLL_LOCKED 0x000c3080
1007
1008#define REG_MDP4_LVDS_PHY_CFG2 0x000c3108
1009
1010#define REG_MDP4_LVDS_PHY_CFG0 0x000c3100
1011#define MDP4_LVDS_PHY_CFG0_SERIALIZATION_ENBLE 0x00000010
1012#define MDP4_LVDS_PHY_CFG0_CHANNEL0 0x00000040
1013#define MDP4_LVDS_PHY_CFG0_CHANNEL1 0x00000080
1014
1015#define REG_MDP4_DTV 0x000d0000
1016
1017#define REG_MDP4_DTV_ENABLE 0x000d0000
1018
1019#define REG_MDP4_DTV_HSYNC_CTRL 0x000d0004
1020#define MDP4_DTV_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
1021#define MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT 0
1022static inline uint32_t MDP4_DTV_HSYNC_CTRL_PULSEW(uint32_t val)
1023{
1024 return ((val) << MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DTV_HSYNC_CTRL_PULSEW__MASK;
1025}
1026#define MDP4_DTV_HSYNC_CTRL_PERIOD__MASK 0xffff0000
1027#define MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT 16
1028static inline uint32_t MDP4_DTV_HSYNC_CTRL_PERIOD(uint32_t val)
1029{
1030 return ((val) << MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DTV_HSYNC_CTRL_PERIOD__MASK;
1031}
1032
1033#define REG_MDP4_DTV_VSYNC_PERIOD 0x000d0008
1034
1035#define REG_MDP4_DTV_VSYNC_LEN 0x000d000c
1036
1037#define REG_MDP4_DTV_DISPLAY_HCTRL 0x000d0018
1038#define MDP4_DTV_DISPLAY_HCTRL_START__MASK 0x0000ffff
1039#define MDP4_DTV_DISPLAY_HCTRL_START__SHIFT 0
1040static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_START(uint32_t val)
1041{
1042 return ((val) << MDP4_DTV_DISPLAY_HCTRL_START__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_START__MASK;
1043}
1044#define MDP4_DTV_DISPLAY_HCTRL_END__MASK 0xffff0000
1045#define MDP4_DTV_DISPLAY_HCTRL_END__SHIFT 16
1046static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_END(uint32_t val)
1047{
1048 return ((val) << MDP4_DTV_DISPLAY_HCTRL_END__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_END__MASK;
1049}
1050
1051#define REG_MDP4_DTV_DISPLAY_VSTART 0x000d001c
1052
1053#define REG_MDP4_DTV_DISPLAY_VEND 0x000d0020
1054
1055#define REG_MDP4_DTV_ACTIVE_HCTL 0x000d002c
1056#define MDP4_DTV_ACTIVE_HCTL_START__MASK 0x00007fff
1057#define MDP4_DTV_ACTIVE_HCTL_START__SHIFT 0
1058static inline uint32_t MDP4_DTV_ACTIVE_HCTL_START(uint32_t val)
1059{
1060 return ((val) << MDP4_DTV_ACTIVE_HCTL_START__SHIFT) & MDP4_DTV_ACTIVE_HCTL_START__MASK;
1061}
1062#define MDP4_DTV_ACTIVE_HCTL_END__MASK 0x7fff0000
1063#define MDP4_DTV_ACTIVE_HCTL_END__SHIFT 16
1064static inline uint32_t MDP4_DTV_ACTIVE_HCTL_END(uint32_t val)
1065{
1066 return ((val) << MDP4_DTV_ACTIVE_HCTL_END__SHIFT) & MDP4_DTV_ACTIVE_HCTL_END__MASK;
1067}
1068#define MDP4_DTV_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
1069
1070#define REG_MDP4_DTV_ACTIVE_VSTART 0x000d0030
1071
1072#define REG_MDP4_DTV_ACTIVE_VEND 0x000d0038
1073
1074#define REG_MDP4_DTV_BORDER_CLR 0x000d0040
1075
1076#define REG_MDP4_DTV_UNDERFLOW_CLR 0x000d0044
1077#define MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
1078#define MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT 0
1079static inline uint32_t MDP4_DTV_UNDERFLOW_CLR_COLOR(uint32_t val)
1080{
1081 return ((val) << MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK;
1082}
1083#define MDP4_DTV_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
1084
1085#define REG_MDP4_DTV_HSYNC_SKEW 0x000d0048
1086
1087#define REG_MDP4_DTV_TEST_CNTL 0x000d004c
1088
1089#define REG_MDP4_DTV_CTRL_POLARITY 0x000d0050
1090#define MDP4_DTV_CTRL_POLARITY_HSYNC_LOW 0x00000001
1091#define MDP4_DTV_CTRL_POLARITY_VSYNC_LOW 0x00000002
1092#define MDP4_DTV_CTRL_POLARITY_DATA_EN_LOW 0x00000004
1093
1094#define REG_MDP4_DSI 0x000e0000
1095
1096#define REG_MDP4_DSI_ENABLE 0x000e0000
1097
1098#define REG_MDP4_DSI_HSYNC_CTRL 0x000e0004
1099#define MDP4_DSI_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
1100#define MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT 0
1101static inline uint32_t MDP4_DSI_HSYNC_CTRL_PULSEW(uint32_t val)
1102{
1103 return ((val) << MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DSI_HSYNC_CTRL_PULSEW__MASK;
1104}
1105#define MDP4_DSI_HSYNC_CTRL_PERIOD__MASK 0xffff0000
1106#define MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT 16
1107static inline uint32_t MDP4_DSI_HSYNC_CTRL_PERIOD(uint32_t val)
1108{
1109 return ((val) << MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DSI_HSYNC_CTRL_PERIOD__MASK;
1110}
1111
1112#define REG_MDP4_DSI_VSYNC_PERIOD 0x000e0008
1113
1114#define REG_MDP4_DSI_VSYNC_LEN 0x000e000c
1115
1116#define REG_MDP4_DSI_DISPLAY_HCTRL 0x000e0010
1117#define MDP4_DSI_DISPLAY_HCTRL_START__MASK 0x0000ffff
1118#define MDP4_DSI_DISPLAY_HCTRL_START__SHIFT 0
1119static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_START(uint32_t val)
1120{
1121 return ((val) << MDP4_DSI_DISPLAY_HCTRL_START__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_START__MASK;
1122}
1123#define MDP4_DSI_DISPLAY_HCTRL_END__MASK 0xffff0000
1124#define MDP4_DSI_DISPLAY_HCTRL_END__SHIFT 16
1125static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_END(uint32_t val)
1126{
1127 return ((val) << MDP4_DSI_DISPLAY_HCTRL_END__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_END__MASK;
1128}
1129
1130#define REG_MDP4_DSI_DISPLAY_VSTART 0x000e0014
1131
1132#define REG_MDP4_DSI_DISPLAY_VEND 0x000e0018
1133
1134#define REG_MDP4_DSI_ACTIVE_HCTL 0x000e001c
1135#define MDP4_DSI_ACTIVE_HCTL_START__MASK 0x00007fff
1136#define MDP4_DSI_ACTIVE_HCTL_START__SHIFT 0
1137static inline uint32_t MDP4_DSI_ACTIVE_HCTL_START(uint32_t val)
1138{
1139 return ((val) << MDP4_DSI_ACTIVE_HCTL_START__SHIFT) & MDP4_DSI_ACTIVE_HCTL_START__MASK;
1140}
1141#define MDP4_DSI_ACTIVE_HCTL_END__MASK 0x7fff0000
1142#define MDP4_DSI_ACTIVE_HCTL_END__SHIFT 16
1143static inline uint32_t MDP4_DSI_ACTIVE_HCTL_END(uint32_t val)
1144{
1145 return ((val) << MDP4_DSI_ACTIVE_HCTL_END__SHIFT) & MDP4_DSI_ACTIVE_HCTL_END__MASK;
1146}
1147#define MDP4_DSI_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
1148
1149#define REG_MDP4_DSI_ACTIVE_VSTART 0x000e0020
1150
1151#define REG_MDP4_DSI_ACTIVE_VEND 0x000e0024
1152
1153#define REG_MDP4_DSI_BORDER_CLR 0x000e0028
1154
1155#define REG_MDP4_DSI_UNDERFLOW_CLR 0x000e002c
1156#define MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
1157#define MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT 0
1158static inline uint32_t MDP4_DSI_UNDERFLOW_CLR_COLOR(uint32_t val)
1159{
1160 return ((val) << MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK;
1161}
1162#define MDP4_DSI_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
1163
1164#define REG_MDP4_DSI_HSYNC_SKEW 0x000e0030
1165
1166#define REG_MDP4_DSI_TEST_CNTL 0x000e0034
1167
1168#define REG_MDP4_DSI_CTRL_POLARITY 0x000e0038
1169#define MDP4_DSI_CTRL_POLARITY_HSYNC_LOW 0x00000001
1170#define MDP4_DSI_CTRL_POLARITY_VSYNC_LOW 0x00000002
1171#define MDP4_DSI_CTRL_POLARITY_DATA_EN_LOW 0x00000004
1172
1173
1174#endif /* MDP4_XML */