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1/**
2 * AMCC SoC PPC4xx Crypto Driver
3 *
4 * Copyright (c) 2008 Applied Micro Circuits Corporation.
5 * All rights reserved. James Hsiao <jhsiao@amcc.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * This filr defines the register set for Security Subsystem
18 */
19
20#ifndef __CRYPTO4XX_REG_DEF_H__
21#define __CRYPTO4XX_REG_DEF_H__
22
23/* CRYPTO4XX Register offset */
24#define CRYPTO4XX_DESCRIPTOR 0x00000000
25#define CRYPTO4XX_CTRL_STAT 0x00000000
26#define CRYPTO4XX_SOURCE 0x00000004
27#define CRYPTO4XX_DEST 0x00000008
28#define CRYPTO4XX_SA 0x0000000C
29#define CRYPTO4XX_SA_LENGTH 0x00000010
30#define CRYPTO4XX_LENGTH 0x00000014
31
32#define CRYPTO4XX_PE_DMA_CFG 0x00000040
33#define CRYPTO4XX_PE_DMA_STAT 0x00000044
34#define CRYPTO4XX_PDR_BASE 0x00000048
35#define CRYPTO4XX_RDR_BASE 0x0000004c
36#define CRYPTO4XX_RING_SIZE 0x00000050
37#define CRYPTO4XX_RING_CTRL 0x00000054
38#define CRYPTO4XX_INT_RING_STAT 0x00000058
39#define CRYPTO4XX_EXT_RING_STAT 0x0000005c
40#define CRYPTO4XX_IO_THRESHOLD 0x00000060
41#define CRYPTO4XX_GATH_RING_BASE 0x00000064
42#define CRYPTO4XX_SCAT_RING_BASE 0x00000068
43#define CRYPTO4XX_PART_RING_SIZE 0x0000006c
44#define CRYPTO4XX_PART_RING_CFG 0x00000070
45
46#define CRYPTO4XX_PDR_BASE_UADDR 0x00000080
47#define CRYPTO4XX_RDR_BASE_UADDR 0x00000084
48#define CRYPTO4XX_PKT_SRC_UADDR 0x00000088
49#define CRYPTO4XX_PKT_DEST_UADDR 0x0000008c
50#define CRYPTO4XX_SA_UADDR 0x00000090
51#define CRYPTO4XX_GATH_RING_BASE_UADDR 0x000000A0
52#define CRYPTO4XX_SCAT_RING_BASE_UADDR 0x000000A4
53
54#define CRYPTO4XX_SEQ_RD 0x00000408
55#define CRYPTO4XX_SEQ_MASK_RD 0x0000040C
56
57#define CRYPTO4XX_SA_CMD_0 0x00010600
58#define CRYPTO4XX_SA_CMD_1 0x00010604
59
60#define CRYPTO4XX_STATE_PTR 0x000106dc
61#define CRYPTO4XX_STATE_IV 0x00010700
62#define CRYPTO4XX_STATE_HASH_BYTE_CNT_0 0x00010710
63#define CRYPTO4XX_STATE_HASH_BYTE_CNT_1 0x00010714
64
65#define CRYPTO4XX_STATE_IDIGEST_0 0x00010718
66#define CRYPTO4XX_STATE_IDIGEST_1 0x0001071c
67
68#define CRYPTO4XX_DATA_IN 0x00018000
69#define CRYPTO4XX_DATA_OUT 0x0001c000
70
71#define CRYPTO4XX_INT_UNMASK_STAT 0x000500a0
72#define CRYPTO4XX_INT_MASK_STAT 0x000500a4
73#define CRYPTO4XX_INT_CLR 0x000500a4
74#define CRYPTO4XX_INT_EN 0x000500a8
75
76#define CRYPTO4XX_INT_PKA 0x00000002
77#define CRYPTO4XX_INT_PDR_DONE 0x00008000
78#define CRYPTO4XX_INT_MA_WR_ERR 0x00020000
79#define CRYPTO4XX_INT_MA_RD_ERR 0x00010000
80#define CRYPTO4XX_INT_PE_ERR 0x00000200
81#define CRYPTO4XX_INT_USER_DMA_ERR 0x00000040
82#define CRYPTO4XX_INT_SLAVE_ERR 0x00000010
83#define CRYPTO4XX_INT_MASTER_ERR 0x00000008
84#define CRYPTO4XX_INT_ERROR 0x00030258
85
86#define CRYPTO4XX_INT_CFG 0x000500ac
87#define CRYPTO4XX_INT_DESCR_RD 0x000500b0
88#define CRYPTO4XX_INT_DESCR_CNT 0x000500b4
89#define CRYPTO4XX_INT_TIMEOUT_CNT 0x000500b8
90
91#define CRYPTO4XX_DEVICE_CTRL 0x00060080
92#define CRYPTO4XX_DEVICE_ID 0x00060084
93#define CRYPTO4XX_DEVICE_INFO 0x00060088
94#define CRYPTO4XX_DMA_USER_SRC 0x00060094
95#define CRYPTO4XX_DMA_USER_DEST 0x00060098
96#define CRYPTO4XX_DMA_USER_CMD 0x0006009C
97
98#define CRYPTO4XX_DMA_CFG 0x000600d4
99#define CRYPTO4XX_BYTE_ORDER_CFG 0x000600d8
100#define CRYPTO4XX_ENDIAN_CFG 0x000600d8
101
102#define CRYPTO4XX_PRNG_STAT 0x00070000
103#define CRYPTO4XX_PRNG_CTRL 0x00070004
104#define CRYPTO4XX_PRNG_SEED_L 0x00070008
105#define CRYPTO4XX_PRNG_SEED_H 0x0007000c
106
107#define CRYPTO4XX_PRNG_RES_0 0x00070020
108#define CRYPTO4XX_PRNG_RES_1 0x00070024
109#define CRYPTO4XX_PRNG_RES_2 0x00070028
110#define CRYPTO4XX_PRNG_RES_3 0x0007002C
111
112#define CRYPTO4XX_PRNG_LFSR_L 0x00070030
113#define CRYPTO4XX_PRNG_LFSR_H 0x00070034
114
115/**
116 * Initialize CRYPTO ENGINE registers, and memory bases.
117 */
118#define PPC4XX_PDR_POLL 0x3ff
119#define PPC4XX_OUTPUT_THRESHOLD 2
120#define PPC4XX_INPUT_THRESHOLD 2
121#define PPC4XX_PD_SIZE 6
122#define PPC4XX_CTX_DONE_INT 0x2000
123#define PPC4XX_PD_DONE_INT 0x8000
124#define PPC4XX_BYTE_ORDER 0x22222
125#define PPC4XX_INTERRUPT_CLR 0x3ffff
126#define PPC4XX_PRNG_CTRL_AUTO_EN 0x3
127#define PPC4XX_DC_3DES_EN 1
128#define PPC4XX_TRNG_EN 0x00020000
129#define PPC4XX_INT_DESCR_CNT 4
130#define PPC4XX_INT_TIMEOUT_CNT 0
131#define PPC4XX_INT_CFG 1
132/**
133 * all follow define are ad hoc
134 */
135#define PPC4XX_RING_RETRY 100
136#define PPC4XX_RING_POLL 100
137#define PPC4XX_SDR_SIZE PPC4XX_NUM_SD
138#define PPC4XX_GDR_SIZE PPC4XX_NUM_GD
139
140/**
141 * Generic Security Association (SA) with all possible fields. These will
142 * never likely used except for reference purpose. These structure format
143 * can be not changed as the hardware expects them to be layout as defined.
144 * Field can be removed or reduced but ordering can not be changed.
145 */
146#define CRYPTO4XX_DMA_CFG_OFFSET 0x40
147union ce_pe_dma_cfg {
148 struct {
149 u32 rsv:7;
150 u32 dir_host:1;
151 u32 rsv1:2;
152 u32 bo_td_en:1;
153 u32 dis_pdr_upd:1;
154 u32 bo_sgpd_en:1;
155 u32 bo_data_en:1;
156 u32 bo_sa_en:1;
157 u32 bo_pd_en:1;
158 u32 rsv2:4;
159 u32 dynamic_sa_en:1;
160 u32 pdr_mode:2;
161 u32 pe_mode:1;
162 u32 rsv3:5;
163 u32 reset_sg:1;
164 u32 reset_pdr:1;
165 u32 reset_pe:1;
166 } bf;
167 u32 w;
168} __attribute__((packed));
169
170#define CRYPTO4XX_PDR_BASE_OFFSET 0x48
171#define CRYPTO4XX_RDR_BASE_OFFSET 0x4c
172#define CRYPTO4XX_RING_SIZE_OFFSET 0x50
173union ce_ring_size {
174 struct {
175 u32 ring_offset:16;
176 u32 rsv:6;
177 u32 ring_size:10;
178 } bf;
179 u32 w;
180} __attribute__((packed));
181
182#define CRYPTO4XX_RING_CONTROL_OFFSET 0x54
183union ce_ring_contol {
184 struct {
185 u32 continuous:1;
186 u32 rsv:5;
187 u32 ring_retry_divisor:10;
188 u32 rsv1:4;
189 u32 ring_poll_divisor:10;
190 } bf;
191 u32 w;
192} __attribute__((packed));
193
194#define CRYPTO4XX_IO_THRESHOLD_OFFSET 0x60
195union ce_io_threshold {
196 struct {
197 u32 rsv:6;
198 u32 output_threshold:10;
199 u32 rsv1:6;
200 u32 input_threshold:10;
201 } bf;
202 u32 w;
203} __attribute__((packed));
204
205#define CRYPTO4XX_GATHER_RING_BASE_OFFSET 0x64
206#define CRYPTO4XX_SCATTER_RING_BASE_OFFSET 0x68
207
208union ce_part_ring_size {
209 struct {
210 u32 sdr_size:16;
211 u32 gdr_size:16;
212 } bf;
213 u32 w;
214} __attribute__((packed));
215
216#define MAX_BURST_SIZE_32 0
217#define MAX_BURST_SIZE_64 1
218#define MAX_BURST_SIZE_128 2
219#define MAX_BURST_SIZE_256 3
220
221/* gather descriptor control length */
222struct gd_ctl_len {
223 u32 len:16;
224 u32 rsv:14;
225 u32 done:1;
226 u32 ready:1;
227} __attribute__((packed));
228
229struct ce_gd {
230 u32 ptr;
231 struct gd_ctl_len ctl_len;
232} __attribute__((packed));
233
234struct sd_ctl {
235 u32 ctl:30;
236 u32 done:1;
237 u32 rdy:1;
238} __attribute__((packed));
239
240struct ce_sd {
241 u32 ptr;
242 struct sd_ctl ctl;
243} __attribute__((packed));
244
245#define PD_PAD_CTL_32 0x10
246#define PD_PAD_CTL_64 0x20
247#define PD_PAD_CTL_128 0x40
248#define PD_PAD_CTL_256 0x80
249union ce_pd_ctl {
250 struct {
251 u32 pd_pad_ctl:8;
252 u32 status:8;
253 u32 next_hdr:8;
254 u32 rsv:2;
255 u32 cached_sa:1;
256 u32 hash_final:1;
257 u32 init_arc4:1;
258 u32 rsv1:1;
259 u32 pe_done:1;
260 u32 host_ready:1;
261 } bf;
262 u32 w;
263} __attribute__((packed));
264
265union ce_pd_ctl_len {
266 struct {
267 u32 bypass:8;
268 u32 pe_done:1;
269 u32 host_ready:1;
270 u32 rsv:2;
271 u32 pkt_len:20;
272 } bf;
273 u32 w;
274} __attribute__((packed));
275
276struct ce_pd {
277 union ce_pd_ctl pd_ctl;
278 u32 src;
279 u32 dest;
280 u32 sa; /* get from ctx->sa_dma_addr */
281 u32 sa_len; /* only if dynamic sa is used */
282 union ce_pd_ctl_len pd_ctl_len;
283
284} __attribute__((packed));
285#endif