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1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __QCOM_CLK_RCG_H__
15#define __QCOM_CLK_RCG_H__
16
17#include <linux/clk-provider.h>
18#include "clk-regmap.h"
19
20struct freq_tbl {
21 unsigned long freq;
22 u8 src;
23 u8 pre_div;
24 u16 m;
25 u16 n;
26};
27
28/**
29 * struct parent_map - map table for PLL source select configuration values
30 * @src: source PLL
31 * @cfg: configuration value
32 */
33struct parent_map {
34 u8 src;
35 u8 cfg;
36};
37
38/**
39 * struct mn - M/N:D counter
40 * @mnctr_en_bit: bit to enable mn counter
41 * @mnctr_reset_bit: bit to assert mn counter reset
42 * @mnctr_mode_shift: lowest bit of mn counter mode field
43 * @n_val_shift: lowest bit of n value field
44 * @m_val_shift: lowest bit of m value field
45 * @width: number of bits in m/n/d values
46 * @reset_in_cc: true if the mnctr_reset_bit is in the CC register
47 */
48struct mn {
49 u8 mnctr_en_bit;
50 u8 mnctr_reset_bit;
51 u8 mnctr_mode_shift;
52#define MNCTR_MODE_DUAL 0x2
53#define MNCTR_MODE_MASK 0x3
54 u8 n_val_shift;
55 u8 m_val_shift;
56 u8 width;
57 bool reset_in_cc;
58};
59
60/**
61 * struct pre_div - pre-divider
62 * @pre_div_shift: lowest bit of pre divider field
63 * @pre_div_width: number of bits in predivider
64 */
65struct pre_div {
66 u8 pre_div_shift;
67 u8 pre_div_width;
68};
69
70/**
71 * struct src_sel - source selector
72 * @src_sel_shift: lowest bit of source selection field
73 * @parent_map: map from software's parent index to hardware's src_sel field
74 */
75struct src_sel {
76 u8 src_sel_shift;
77#define SRC_SEL_MASK 0x7
78 const struct parent_map *parent_map;
79};
80
81/**
82 * struct clk_rcg - root clock generator
83 *
84 * @ns_reg: NS register
85 * @md_reg: MD register
86 * @mn: mn counter
87 * @p: pre divider
88 * @s: source selector
89 * @freq_tbl: frequency table
90 * @clkr: regmap clock handle
91 * @lock: register lock
92 *
93 */
94struct clk_rcg {
95 u32 ns_reg;
96 u32 md_reg;
97
98 struct mn mn;
99 struct pre_div p;
100 struct src_sel s;
101
102 const struct freq_tbl *freq_tbl;
103
104 struct clk_regmap clkr;
105};
106
107extern const struct clk_ops clk_rcg_ops;
108extern const struct clk_ops clk_rcg_bypass_ops;
109extern const struct clk_ops clk_rcg_bypass2_ops;
110extern const struct clk_ops clk_rcg_pixel_ops;
111extern const struct clk_ops clk_rcg_esc_ops;
112extern const struct clk_ops clk_rcg_lcc_ops;
113
114#define to_clk_rcg(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg, clkr)
115
116/**
117 * struct clk_dyn_rcg - root clock generator with glitch free mux
118 *
119 * @mux_sel_bit: bit to switch glitch free mux
120 * @ns_reg: NS0 and NS1 register
121 * @md_reg: MD0 and MD1 register
122 * @bank_reg: register to XOR @mux_sel_bit into to switch glitch free mux
123 * @mn: mn counter (banked)
124 * @s: source selector (banked)
125 * @freq_tbl: frequency table
126 * @clkr: regmap clock handle
127 * @lock: register lock
128 *
129 */
130struct clk_dyn_rcg {
131 u32 ns_reg[2];
132 u32 md_reg[2];
133 u32 bank_reg;
134
135 u8 mux_sel_bit;
136
137 struct mn mn[2];
138 struct pre_div p[2];
139 struct src_sel s[2];
140
141 const struct freq_tbl *freq_tbl;
142
143 struct clk_regmap clkr;
144};
145
146extern const struct clk_ops clk_dyn_rcg_ops;
147
148#define to_clk_dyn_rcg(_hw) \
149 container_of(to_clk_regmap(_hw), struct clk_dyn_rcg, clkr)
150
151/**
152 * struct clk_rcg2 - root clock generator
153 *
154 * @cmd_rcgr: corresponds to *_CMD_RCGR
155 * @mnd_width: number of bits in m/n/d values
156 * @hid_width: number of bits in half integer divider
157 * @parent_map: map from software's parent index to hardware's src_sel field
158 * @freq_tbl: frequency table
159 * @current_freq: last cached frequency when using branches with shared RCGs
160 * @clkr: regmap clock handle
161 *
162 */
163struct clk_rcg2 {
164 u32 cmd_rcgr;
165 u8 mnd_width;
166 u8 hid_width;
167 const struct parent_map *parent_map;
168 const struct freq_tbl *freq_tbl;
169 unsigned long current_freq;
170 struct clk_regmap clkr;
171};
172
173#define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
174
175extern const struct clk_ops clk_rcg2_ops;
176extern const struct clk_ops clk_rcg2_floor_ops;
177extern const struct clk_ops clk_rcg2_shared_ops;
178extern const struct clk_ops clk_edp_pixel_ops;
179extern const struct clk_ops clk_byte_ops;
180extern const struct clk_ops clk_byte2_ops;
181extern const struct clk_ops clk_pixel_ops;
182extern const struct clk_ops clk_gfx3d_ops;
183
184#endif