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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 | /* * Hisilicon Hi3620 clock gate driver * * Copyright (c) 2012-2013 Hisilicon Limited. * Copyright (c) 2012-2013 Linaro Limited. * * Author: Haojian Zhuang <haojian.zhuang@linaro.org> * Xin Li <li.xin@linaro.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * */ #ifndef __HISI_CLK_H #define __HISI_CLK_H #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/spinlock.h> struct platform_device; struct hisi_clock_data { struct clk_onecell_data clk_data; void __iomem *base; }; struct hisi_fixed_rate_clock { unsigned int id; char *name; const char *parent_name; unsigned long flags; unsigned long fixed_rate; }; struct hisi_fixed_factor_clock { unsigned int id; char *name; const char *parent_name; unsigned long mult; unsigned long div; unsigned long flags; }; struct hisi_mux_clock { unsigned int id; const char *name; const char *const *parent_names; u8 num_parents; unsigned long flags; unsigned long offset; u8 shift; u8 width; u8 mux_flags; u32 *table; const char *alias; }; struct hisi_divider_clock { unsigned int id; const char *name; const char *parent_name; unsigned long flags; unsigned long offset; u8 shift; u8 width; u8 div_flags; struct clk_div_table *table; const char *alias; }; struct hi6220_divider_clock { unsigned int id; const char *name; const char *parent_name; unsigned long flags; unsigned long offset; u8 shift; u8 width; u32 mask_bit; const char *alias; }; struct hisi_gate_clock { unsigned int id; const char *name; const char *parent_name; unsigned long flags; unsigned long offset; u8 bit_idx; u8 gate_flags; const char *alias; }; struct clk *hisi_register_clkgate_sep(struct device *, const char *, const char *, unsigned long, void __iomem *, u8, u8, spinlock_t *); struct clk *hi6220_register_clkdiv(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u32 mask_bit, spinlock_t *lock); struct hisi_clock_data *hisi_clk_alloc(struct platform_device *, int); struct hisi_clock_data *hisi_clk_init(struct device_node *, int); int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *, int, struct hisi_clock_data *); int hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *, int, struct hisi_clock_data *); int hisi_clk_register_mux(const struct hisi_mux_clock *, int, struct hisi_clock_data *); int hisi_clk_register_divider(const struct hisi_divider_clock *, int, struct hisi_clock_data *); int hisi_clk_register_gate(const struct hisi_gate_clock *, int, struct hisi_clock_data *); void hisi_clk_register_gate_sep(const struct hisi_gate_clock *, int, struct hisi_clock_data *); void hi6220_clk_register_divider(const struct hi6220_divider_clock *, int, struct hisi_clock_data *); #define hisi_clk_unregister(type) \ static inline \ void hisi_clk_unregister_##type(const struct hisi_##type##_clock *clks, \ int nums, struct hisi_clock_data *data) \ { \ struct clk **clocks = data->clk_data.clks; \ int i; \ for (i = 0; i < nums; i++) { \ int id = clks[i].id; \ if (clocks[id]) \ clk_unregister_##type(clocks[id]); \ } \ } hisi_clk_unregister(fixed_rate) hisi_clk_unregister(fixed_factor) hisi_clk_unregister(mux) hisi_clk_unregister(divider) hisi_clk_unregister(gate) #endif /* __HISI_CLK_H */ |