1/*
  2 *
  3 * Copyright (C) 2013 Texas Instruments Incorporated
  4 *
  5 * Interconnects common for AM335x and AM43x
  6 *
  7 * This program is free software; you can redistribute it and/or
  8 * modify it under the terms of the GNU General Public License as
  9 * published by the Free Software Foundation version 2.
 10 *
 11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 12 * kind, whether express or implied; without even the implied warranty
 13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 14 * GNU General Public License for more details.
 15 */
 16
 17#include <linux/sizes.h>
 18#include "omap_hwmod.h"
 19#include "omap_hwmod_33xx_43xx_common_data.h"
 20
 21/* mpu -> l3 main */
 22struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
 23	.master		= &am33xx_mpu_hwmod,
 24	.slave		= &am33xx_l3_main_hwmod,
 25	.clk		= "dpll_mpu_m2_ck",
 26	.user		= OCP_USER_MPU,
 27};
 28
 29/* l3 main -> l3 s */
 30struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
 31	.master		= &am33xx_l3_main_hwmod,
 32	.slave		= &am33xx_l3_s_hwmod,
 33	.clk		= "l3s_gclk",
 34	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 35};
 36
 37/* l3 s -> l4 per/ls */
 38struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
 39	.master		= &am33xx_l3_s_hwmod,
 40	.slave		= &am33xx_l4_ls_hwmod,
 41	.clk		= "l3s_gclk",
 42	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 43};
 44
 45/* l3 s -> l4 wkup */
 46struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
 47	.master		= &am33xx_l3_s_hwmod,
 48	.slave		= &am33xx_l4_wkup_hwmod,
 49	.clk		= "l3s_gclk",
 50	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 51};
 52
 53/* l3 main -> l3 instr */
 54struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
 55	.master		= &am33xx_l3_main_hwmod,
 56	.slave		= &am33xx_l3_instr_hwmod,
 57	.clk		= "l3s_gclk",
 58	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 59};
 60
 61/* mpu -> prcm */
 62struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
 63	.master		= &am33xx_mpu_hwmod,
 64	.slave		= &am33xx_prcm_hwmod,
 65	.clk		= "dpll_mpu_m2_ck",
 66	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 67};
 68
 69/* l3 s -> l3 main*/
 70struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
 71	.master		= &am33xx_l3_s_hwmod,
 72	.slave		= &am33xx_l3_main_hwmod,
 73	.clk		= "l3s_gclk",
 74	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 75};
 76
 77/* pru-icss -> l3 main */
 78struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
 79	.master		= &am33xx_pruss_hwmod,
 80	.slave		= &am33xx_l3_main_hwmod,
 81	.clk		= "l3_gclk",
 82	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 83};
 84
 85/* gfx -> l3 main */
 86struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
 87	.master		= &am33xx_gfx_hwmod,
 88	.slave		= &am33xx_l3_main_hwmod,
 89	.clk		= "dpll_core_m4_ck",
 90	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 91};
 92
 93/* l3 main -> gfx */
 94struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
 95	.master		= &am33xx_l3_main_hwmod,
 96	.slave		= &am33xx_gfx_hwmod,
 97	.clk		= "dpll_core_m4_ck",
 98	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 99};
100
101/* l4 wkup -> rtc */
102struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
103	.master		= &am33xx_l4_wkup_hwmod,
104	.slave		= &am33xx_rtc_hwmod,
105	.clk		= "clkdiv32k_ick",
106	.user		= OCP_USER_MPU,
107};
108
109/* l4 per/ls -> DCAN0 */
110struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
111	.master		= &am33xx_l4_ls_hwmod,
112	.slave		= &am33xx_dcan0_hwmod,
113	.clk		= "l4ls_gclk",
114	.user		= OCP_USER_MPU | OCP_USER_SDMA,
115};
116
117/* l4 per/ls -> DCAN1 */
118struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
119	.master		= &am33xx_l4_ls_hwmod,
120	.slave		= &am33xx_dcan1_hwmod,
121	.clk		= "l4ls_gclk",
122	.user		= OCP_USER_MPU | OCP_USER_SDMA,
123};
124
125/* l4 per/ls -> GPIO2 */
126struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
127	.master		= &am33xx_l4_ls_hwmod,
128	.slave		= &am33xx_gpio1_hwmod,
129	.clk		= "l4ls_gclk",
130	.user		= OCP_USER_MPU | OCP_USER_SDMA,
131};
132
133/* l4 per/ls -> gpio3 */
134struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
135	.master		= &am33xx_l4_ls_hwmod,
136	.slave		= &am33xx_gpio2_hwmod,
137	.clk		= "l4ls_gclk",
138	.user		= OCP_USER_MPU | OCP_USER_SDMA,
139};
140
141/* l4 per/ls -> gpio4 */
142struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
143	.master		= &am33xx_l4_ls_hwmod,
144	.slave		= &am33xx_gpio3_hwmod,
145	.clk		= "l4ls_gclk",
146	.user		= OCP_USER_MPU | OCP_USER_SDMA,
147};
148
149struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
150	.master		= &am33xx_cpgmac0_hwmod,
151	.slave		= &am33xx_mdio_hwmod,
152	.user		= OCP_USER_MPU,
153};
154
155struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
156	.master		= &am33xx_l4_ls_hwmod,
157	.slave		= &am33xx_elm_hwmod,
158	.clk		= "l4ls_gclk",
159	.user		= OCP_USER_MPU,
160};
161
162static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
163	{
164		.pa_start	= 0x48300000,
165		.pa_end		= 0x48300000 + SZ_16 - 1,
166		.flags		= ADDR_TYPE_RT
167	},
168	{ }
169};
170
171struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
172	.master		= &am33xx_l4_ls_hwmod,
173	.slave		= &am33xx_epwmss0_hwmod,
174	.clk		= "l4ls_gclk",
175	.addr		= am33xx_epwmss0_addr_space,
176	.user		= OCP_USER_MPU,
177};
178
179static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
180	{
181		.pa_start	= 0x48302000,
182		.pa_end		= 0x48302000 + SZ_16 - 1,
183		.flags		= ADDR_TYPE_RT
184	},
185	{ }
186};
187
188struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
189	.master		= &am33xx_l4_ls_hwmod,
190	.slave		= &am33xx_epwmss1_hwmod,
191	.clk		= "l4ls_gclk",
192	.addr		= am33xx_epwmss1_addr_space,
193	.user		= OCP_USER_MPU,
194};
195
196static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
197	{
198		.pa_start	= 0x48304000,
199		.pa_end		= 0x48304000 + SZ_16 - 1,
200		.flags		= ADDR_TYPE_RT
201	},
202	{ }
203};
204
205struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
206	.master		= &am33xx_l4_ls_hwmod,
207	.slave		= &am33xx_epwmss2_hwmod,
208	.clk		= "l4ls_gclk",
209	.addr		= am33xx_epwmss2_addr_space,
210	.user		= OCP_USER_MPU,
211};
212
213/* l3s cfg -> gpmc */
214struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
215	.master		= &am33xx_l3_s_hwmod,
216	.slave		= &am33xx_gpmc_hwmod,
217	.clk		= "l3s_gclk",
218	.user		= OCP_USER_MPU,
219};
220
221/* i2c2 */
222struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
223	.master		= &am33xx_l4_ls_hwmod,
224	.slave		= &am33xx_i2c2_hwmod,
225	.clk		= "l4ls_gclk",
226	.user		= OCP_USER_MPU,
227};
228
229struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
230	.master		= &am33xx_l4_ls_hwmod,
231	.slave		= &am33xx_i2c3_hwmod,
232	.clk		= "l4ls_gclk",
233	.user		= OCP_USER_MPU,
234};
235
236/* l4 ls -> mailbox */
237struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
238	.master		= &am33xx_l4_ls_hwmod,
239	.slave		= &am33xx_mailbox_hwmod,
240	.clk		= "l4ls_gclk",
241	.user		= OCP_USER_MPU,
242};
243
244/* l4 ls -> spinlock */
245struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
246	.master		= &am33xx_l4_ls_hwmod,
247	.slave		= &am33xx_spinlock_hwmod,
248	.clk		= "l4ls_gclk",
249	.user		= OCP_USER_MPU,
250};
251
252/* l4 ls -> mcasp0 */
253static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
254	{
255		.pa_start	= 0x48038000,
256		.pa_end		= 0x48038000 + SZ_8K - 1,
257		.flags		= ADDR_TYPE_RT
258	},
259	{ }
260};
261
262struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
263	.master		= &am33xx_l4_ls_hwmod,
264	.slave		= &am33xx_mcasp0_hwmod,
265	.clk		= "l4ls_gclk",
266	.addr		= am33xx_mcasp0_addr_space,
267	.user		= OCP_USER_MPU,
268};
269
270/* l4 ls -> mcasp1 */
271static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
272	{
273		.pa_start	= 0x4803C000,
274		.pa_end		= 0x4803C000 + SZ_8K - 1,
275		.flags		= ADDR_TYPE_RT
276	},
277	{ }
278};
279
280struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
281	.master		= &am33xx_l4_ls_hwmod,
282	.slave		= &am33xx_mcasp1_hwmod,
283	.clk		= "l4ls_gclk",
284	.addr		= am33xx_mcasp1_addr_space,
285	.user		= OCP_USER_MPU,
286};
287
288/* l4 ls -> mmc0 */
289static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
290	{
291		.pa_start	= 0x48060100,
292		.pa_end		= 0x48060100 + SZ_4K - 1,
293		.flags		= ADDR_TYPE_RT,
294	},
295	{ }
296};
297
298struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
299	.master		= &am33xx_l4_ls_hwmod,
300	.slave		= &am33xx_mmc0_hwmod,
301	.clk		= "l4ls_gclk",
302	.addr		= am33xx_mmc0_addr_space,
303	.user		= OCP_USER_MPU,
304};
305
306/* l4 ls -> mmc1 */
307static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
308	{
309		.pa_start	= 0x481d8100,
310		.pa_end		= 0x481d8100 + SZ_4K - 1,
311		.flags		= ADDR_TYPE_RT,
312	},
313	{ }
314};
315
316struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
317	.master		= &am33xx_l4_ls_hwmod,
318	.slave		= &am33xx_mmc1_hwmod,
319	.clk		= "l4ls_gclk",
320	.addr		= am33xx_mmc1_addr_space,
321	.user		= OCP_USER_MPU,
322};
323
324/* l3 s -> mmc2 */
325static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
326	{
327		.pa_start	= 0x47810100,
328		.pa_end		= 0x47810100 + SZ_64K - 1,
329		.flags		= ADDR_TYPE_RT,
330	},
331	{ }
332};
333
334struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
335	.master		= &am33xx_l3_s_hwmod,
336	.slave		= &am33xx_mmc2_hwmod,
337	.clk		= "l3s_gclk",
338	.addr		= am33xx_mmc2_addr_space,
339	.user		= OCP_USER_MPU,
340};
341
342/* l4 ls -> mcspi0 */
343struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
344	.master		= &am33xx_l4_ls_hwmod,
345	.slave		= &am33xx_spi0_hwmod,
346	.clk		= "l4ls_gclk",
347	.user		= OCP_USER_MPU,
348};
349
350/* l4 ls -> mcspi1 */
351struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
352	.master		= &am33xx_l4_ls_hwmod,
353	.slave		= &am33xx_spi1_hwmod,
354	.clk		= "l4ls_gclk",
355	.user		= OCP_USER_MPU,
356};
357
358/* l4 per -> timer2 */
359struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
360	.master		= &am33xx_l4_ls_hwmod,
361	.slave		= &am33xx_timer2_hwmod,
362	.clk		= "l4ls_gclk",
363	.user		= OCP_USER_MPU,
364};
365
366/* l4 per -> timer3 */
367struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
368	.master		= &am33xx_l4_ls_hwmod,
369	.slave		= &am33xx_timer3_hwmod,
370	.clk		= "l4ls_gclk",
371	.user		= OCP_USER_MPU,
372};
373
374/* l4 per -> timer4 */
375struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
376	.master		= &am33xx_l4_ls_hwmod,
377	.slave		= &am33xx_timer4_hwmod,
378	.clk		= "l4ls_gclk",
379	.user		= OCP_USER_MPU,
380};
381
382/* l4 per -> timer5 */
383struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
384	.master		= &am33xx_l4_ls_hwmod,
385	.slave		= &am33xx_timer5_hwmod,
386	.clk		= "l4ls_gclk",
387	.user		= OCP_USER_MPU,
388};
389
390/* l4 per -> timer6 */
391struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
392	.master		= &am33xx_l4_ls_hwmod,
393	.slave		= &am33xx_timer6_hwmod,
394	.clk		= "l4ls_gclk",
395	.user		= OCP_USER_MPU,
396};
397
398/* l4 per -> timer7 */
399struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
400	.master		= &am33xx_l4_ls_hwmod,
401	.slave		= &am33xx_timer7_hwmod,
402	.clk		= "l4ls_gclk",
403	.user		= OCP_USER_MPU,
404};
405
406/* l3 main -> tpcc */
407struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
408	.master		= &am33xx_l3_main_hwmod,
409	.slave		= &am33xx_tpcc_hwmod,
410	.clk		= "l3_gclk",
411	.user		= OCP_USER_MPU,
412};
413
414/* l3 main -> tpcc0 */
415static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
416	{
417		.pa_start	= 0x49800000,
418		.pa_end		= 0x49800000 + SZ_8K - 1,
419		.flags		= ADDR_TYPE_RT,
420	},
421	{ }
422};
423
424struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
425	.master		= &am33xx_l3_main_hwmod,
426	.slave		= &am33xx_tptc0_hwmod,
427	.clk		= "l3_gclk",
428	.addr		= am33xx_tptc0_addr_space,
429	.user		= OCP_USER_MPU,
430};
431
432/* l3 main -> tpcc1 */
433static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
434	{
435		.pa_start	= 0x49900000,
436		.pa_end		= 0x49900000 + SZ_8K - 1,
437		.flags		= ADDR_TYPE_RT,
438	},
439	{ }
440};
441
442struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
443	.master		= &am33xx_l3_main_hwmod,
444	.slave		= &am33xx_tptc1_hwmod,
445	.clk		= "l3_gclk",
446	.addr		= am33xx_tptc1_addr_space,
447	.user		= OCP_USER_MPU,
448};
449
450/* l3 main -> tpcc2 */
451static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
452	{
453		.pa_start	= 0x49a00000,
454		.pa_end		= 0x49a00000 + SZ_8K - 1,
455		.flags		= ADDR_TYPE_RT,
456	},
457	{ }
458};
459
460struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
461	.master		= &am33xx_l3_main_hwmod,
462	.slave		= &am33xx_tptc2_hwmod,
463	.clk		= "l3_gclk",
464	.addr		= am33xx_tptc2_addr_space,
465	.user		= OCP_USER_MPU,
466};
467
468/* l4 ls -> uart2 */
469struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
470	.master		= &am33xx_l4_ls_hwmod,
471	.slave		= &am33xx_uart2_hwmod,
472	.clk		= "l4ls_gclk",
473	.user		= OCP_USER_MPU,
474};
475
476/* l4 ls -> uart3 */
477struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
478	.master		= &am33xx_l4_ls_hwmod,
479	.slave		= &am33xx_uart3_hwmod,
480	.clk		= "l4ls_gclk",
481	.user		= OCP_USER_MPU,
482};
483
484/* l4 ls -> uart4 */
485struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
486	.master		= &am33xx_l4_ls_hwmod,
487	.slave		= &am33xx_uart4_hwmod,
488	.clk		= "l4ls_gclk",
489	.user		= OCP_USER_MPU,
490};
491
492/* l4 ls -> uart5 */
493struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
494	.master		= &am33xx_l4_ls_hwmod,
495	.slave		= &am33xx_uart5_hwmod,
496	.clk		= "l4ls_gclk",
497	.user		= OCP_USER_MPU,
498};
499
500/* l4 ls -> uart6 */
501struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
502	.master		= &am33xx_l4_ls_hwmod,
503	.slave		= &am33xx_uart6_hwmod,
504	.clk		= "l4ls_gclk",
505	.user		= OCP_USER_MPU,
506};
507
508/* l3 main -> ocmc */
509struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
510	.master		= &am33xx_l3_main_hwmod,
511	.slave		= &am33xx_ocmcram_hwmod,
512	.user		= OCP_USER_MPU | OCP_USER_SDMA,
513};
514
515/* l3 main -> sha0 HIB2 */
516static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = {
517	{
518		.pa_start	= 0x53100000,
519		.pa_end		= 0x53100000 + SZ_512 - 1,
520		.flags		= ADDR_TYPE_RT
521	},
522	{ }
523};
524
525struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = {
526	.master		= &am33xx_l3_main_hwmod,
527	.slave		= &am33xx_sha0_hwmod,
528	.clk		= "sha0_fck",
529	.addr		= am33xx_sha0_addrs,
530	.user		= OCP_USER_MPU | OCP_USER_SDMA,
531};
532
533/* l3 main -> AES0 HIB2 */
534static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = {
535	{
536		.pa_start	= 0x53500000,
537		.pa_end		= 0x53500000 + SZ_1M - 1,
538		.flags		= ADDR_TYPE_RT
539	},
540	{ }
541};
542
543struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
544	.master		= &am33xx_l3_main_hwmod,
545	.slave		= &am33xx_aes0_hwmod,
546	.clk		= "aes0_fck",
547	.addr		= am33xx_aes0_addrs,
548	.user		= OCP_USER_MPU | OCP_USER_SDMA,
549};
550
551/* l4 per -> rng */
552struct omap_hwmod_ocp_if am33xx_l4_per__rng = {
553	.master		= &am33xx_l4_ls_hwmod,
554	.slave		= &am33xx_rng_hwmod,
555	.clk		= "rng_fck",
556	.user		= OCP_USER_MPU,
557};