Loading...
1/* Generic I/O port emulation, based on MN10300 code
2 *
3 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public Licence
8 * as published by the Free Software Foundation; either version
9 * 2 of the Licence, or (at your option) any later version.
10 */
11#ifndef __ASM_GENERIC_IO_H
12#define __ASM_GENERIC_IO_H
13
14#include <asm/page.h> /* I/O is all done through memory accesses */
15#include <linux/string.h> /* for memset() and memcpy() */
16#include <linux/types.h>
17
18#ifdef CONFIG_GENERIC_IOMAP
19#include <asm-generic/iomap.h>
20#endif
21
22#include <asm-generic/pci_iomap.h>
23
24#ifndef mmiowb
25#define mmiowb() do {} while (0)
26#endif
27
28/*
29 * __raw_{read,write}{b,w,l,q}() access memory in native endianness.
30 *
31 * On some architectures memory mapped IO needs to be accessed differently.
32 * On the simple architectures, we just read/write the memory location
33 * directly.
34 */
35
36#ifndef __raw_readb
37#define __raw_readb __raw_readb
38static inline u8 __raw_readb(const volatile void __iomem *addr)
39{
40 return *(const volatile u8 __force *)addr;
41}
42#endif
43
44#ifndef __raw_readw
45#define __raw_readw __raw_readw
46static inline u16 __raw_readw(const volatile void __iomem *addr)
47{
48 return *(const volatile u16 __force *)addr;
49}
50#endif
51
52#ifndef __raw_readl
53#define __raw_readl __raw_readl
54static inline u32 __raw_readl(const volatile void __iomem *addr)
55{
56 return *(const volatile u32 __force *)addr;
57}
58#endif
59
60#ifdef CONFIG_64BIT
61#ifndef __raw_readq
62#define __raw_readq __raw_readq
63static inline u64 __raw_readq(const volatile void __iomem *addr)
64{
65 return *(const volatile u64 __force *)addr;
66}
67#endif
68#endif /* CONFIG_64BIT */
69
70#ifndef __raw_writeb
71#define __raw_writeb __raw_writeb
72static inline void __raw_writeb(u8 value, volatile void __iomem *addr)
73{
74 *(volatile u8 __force *)addr = value;
75}
76#endif
77
78#ifndef __raw_writew
79#define __raw_writew __raw_writew
80static inline void __raw_writew(u16 value, volatile void __iomem *addr)
81{
82 *(volatile u16 __force *)addr = value;
83}
84#endif
85
86#ifndef __raw_writel
87#define __raw_writel __raw_writel
88static inline void __raw_writel(u32 value, volatile void __iomem *addr)
89{
90 *(volatile u32 __force *)addr = value;
91}
92#endif
93
94#ifdef CONFIG_64BIT
95#ifndef __raw_writeq
96#define __raw_writeq __raw_writeq
97static inline void __raw_writeq(u64 value, volatile void __iomem *addr)
98{
99 *(volatile u64 __force *)addr = value;
100}
101#endif
102#endif /* CONFIG_64BIT */
103
104/*
105 * {read,write}{b,w,l,q}() access little endian memory and return result in
106 * native endianness.
107 */
108
109#ifndef readb
110#define readb readb
111static inline u8 readb(const volatile void __iomem *addr)
112{
113 return __raw_readb(addr);
114}
115#endif
116
117#ifndef readw
118#define readw readw
119static inline u16 readw(const volatile void __iomem *addr)
120{
121 return __le16_to_cpu(__raw_readw(addr));
122}
123#endif
124
125#ifndef readl
126#define readl readl
127static inline u32 readl(const volatile void __iomem *addr)
128{
129 return __le32_to_cpu(__raw_readl(addr));
130}
131#endif
132
133#ifdef CONFIG_64BIT
134#ifndef readq
135#define readq readq
136static inline u64 readq(const volatile void __iomem *addr)
137{
138 return __le64_to_cpu(__raw_readq(addr));
139}
140#endif
141#endif /* CONFIG_64BIT */
142
143#ifndef writeb
144#define writeb writeb
145static inline void writeb(u8 value, volatile void __iomem *addr)
146{
147 __raw_writeb(value, addr);
148}
149#endif
150
151#ifndef writew
152#define writew writew
153static inline void writew(u16 value, volatile void __iomem *addr)
154{
155 __raw_writew(cpu_to_le16(value), addr);
156}
157#endif
158
159#ifndef writel
160#define writel writel
161static inline void writel(u32 value, volatile void __iomem *addr)
162{
163 __raw_writel(__cpu_to_le32(value), addr);
164}
165#endif
166
167#ifdef CONFIG_64BIT
168#ifndef writeq
169#define writeq writeq
170static inline void writeq(u64 value, volatile void __iomem *addr)
171{
172 __raw_writeq(__cpu_to_le64(value), addr);
173}
174#endif
175#endif /* CONFIG_64BIT */
176
177/*
178 * {read,write}{b,w,l,q}_relaxed() are like the regular version, but
179 * are not guaranteed to provide ordering against spinlocks or memory
180 * accesses.
181 */
182#ifndef readb_relaxed
183#define readb_relaxed readb
184#endif
185
186#ifndef readw_relaxed
187#define readw_relaxed readw
188#endif
189
190#ifndef readl_relaxed
191#define readl_relaxed readl
192#endif
193
194#if defined(readq) && !defined(readq_relaxed)
195#define readq_relaxed readq
196#endif
197
198#ifndef writeb_relaxed
199#define writeb_relaxed writeb
200#endif
201
202#ifndef writew_relaxed
203#define writew_relaxed writew
204#endif
205
206#ifndef writel_relaxed
207#define writel_relaxed writel
208#endif
209
210#if defined(writeq) && !defined(writeq_relaxed)
211#define writeq_relaxed writeq
212#endif
213
214/*
215 * {read,write}s{b,w,l,q}() repeatedly access the same memory address in
216 * native endianness in 8-, 16-, 32- or 64-bit chunks (@count times).
217 */
218#ifndef readsb
219#define readsb readsb
220static inline void readsb(const volatile void __iomem *addr, void *buffer,
221 unsigned int count)
222{
223 if (count) {
224 u8 *buf = buffer;
225
226 do {
227 u8 x = __raw_readb(addr);
228 *buf++ = x;
229 } while (--count);
230 }
231}
232#endif
233
234#ifndef readsw
235#define readsw readsw
236static inline void readsw(const volatile void __iomem *addr, void *buffer,
237 unsigned int count)
238{
239 if (count) {
240 u16 *buf = buffer;
241
242 do {
243 u16 x = __raw_readw(addr);
244 *buf++ = x;
245 } while (--count);
246 }
247}
248#endif
249
250#ifndef readsl
251#define readsl readsl
252static inline void readsl(const volatile void __iomem *addr, void *buffer,
253 unsigned int count)
254{
255 if (count) {
256 u32 *buf = buffer;
257
258 do {
259 u32 x = __raw_readl(addr);
260 *buf++ = x;
261 } while (--count);
262 }
263}
264#endif
265
266#ifdef CONFIG_64BIT
267#ifndef readsq
268#define readsq readsq
269static inline void readsq(const volatile void __iomem *addr, void *buffer,
270 unsigned int count)
271{
272 if (count) {
273 u64 *buf = buffer;
274
275 do {
276 u64 x = __raw_readq(addr);
277 *buf++ = x;
278 } while (--count);
279 }
280}
281#endif
282#endif /* CONFIG_64BIT */
283
284#ifndef writesb
285#define writesb writesb
286static inline void writesb(volatile void __iomem *addr, const void *buffer,
287 unsigned int count)
288{
289 if (count) {
290 const u8 *buf = buffer;
291
292 do {
293 __raw_writeb(*buf++, addr);
294 } while (--count);
295 }
296}
297#endif
298
299#ifndef writesw
300#define writesw writesw
301static inline void writesw(volatile void __iomem *addr, const void *buffer,
302 unsigned int count)
303{
304 if (count) {
305 const u16 *buf = buffer;
306
307 do {
308 __raw_writew(*buf++, addr);
309 } while (--count);
310 }
311}
312#endif
313
314#ifndef writesl
315#define writesl writesl
316static inline void writesl(volatile void __iomem *addr, const void *buffer,
317 unsigned int count)
318{
319 if (count) {
320 const u32 *buf = buffer;
321
322 do {
323 __raw_writel(*buf++, addr);
324 } while (--count);
325 }
326}
327#endif
328
329#ifdef CONFIG_64BIT
330#ifndef writesq
331#define writesq writesq
332static inline void writesq(volatile void __iomem *addr, const void *buffer,
333 unsigned int count)
334{
335 if (count) {
336 const u64 *buf = buffer;
337
338 do {
339 __raw_writeq(*buf++, addr);
340 } while (--count);
341 }
342}
343#endif
344#endif /* CONFIG_64BIT */
345
346#ifndef PCI_IOBASE
347#define PCI_IOBASE ((void __iomem *)0)
348#endif
349
350#ifndef IO_SPACE_LIMIT
351#define IO_SPACE_LIMIT 0xffff
352#endif
353
354/*
355 * {in,out}{b,w,l}() access little endian I/O. {in,out}{b,w,l}_p() can be
356 * implemented on hardware that needs an additional delay for I/O accesses to
357 * take effect.
358 */
359
360#ifndef inb
361#define inb inb
362static inline u8 inb(unsigned long addr)
363{
364 return readb(PCI_IOBASE + addr);
365}
366#endif
367
368#ifndef inw
369#define inw inw
370static inline u16 inw(unsigned long addr)
371{
372 return readw(PCI_IOBASE + addr);
373}
374#endif
375
376#ifndef inl
377#define inl inl
378static inline u32 inl(unsigned long addr)
379{
380 return readl(PCI_IOBASE + addr);
381}
382#endif
383
384#ifndef outb
385#define outb outb
386static inline void outb(u8 value, unsigned long addr)
387{
388 writeb(value, PCI_IOBASE + addr);
389}
390#endif
391
392#ifndef outw
393#define outw outw
394static inline void outw(u16 value, unsigned long addr)
395{
396 writew(value, PCI_IOBASE + addr);
397}
398#endif
399
400#ifndef outl
401#define outl outl
402static inline void outl(u32 value, unsigned long addr)
403{
404 writel(value, PCI_IOBASE + addr);
405}
406#endif
407
408#ifndef inb_p
409#define inb_p inb_p
410static inline u8 inb_p(unsigned long addr)
411{
412 return inb(addr);
413}
414#endif
415
416#ifndef inw_p
417#define inw_p inw_p
418static inline u16 inw_p(unsigned long addr)
419{
420 return inw(addr);
421}
422#endif
423
424#ifndef inl_p
425#define inl_p inl_p
426static inline u32 inl_p(unsigned long addr)
427{
428 return inl(addr);
429}
430#endif
431
432#ifndef outb_p
433#define outb_p outb_p
434static inline void outb_p(u8 value, unsigned long addr)
435{
436 outb(value, addr);
437}
438#endif
439
440#ifndef outw_p
441#define outw_p outw_p
442static inline void outw_p(u16 value, unsigned long addr)
443{
444 outw(value, addr);
445}
446#endif
447
448#ifndef outl_p
449#define outl_p outl_p
450static inline void outl_p(u32 value, unsigned long addr)
451{
452 outl(value, addr);
453}
454#endif
455
456/*
457 * {in,out}s{b,w,l}{,_p}() are variants of the above that repeatedly access a
458 * single I/O port multiple times.
459 */
460
461#ifndef insb
462#define insb insb
463static inline void insb(unsigned long addr, void *buffer, unsigned int count)
464{
465 readsb(PCI_IOBASE + addr, buffer, count);
466}
467#endif
468
469#ifndef insw
470#define insw insw
471static inline void insw(unsigned long addr, void *buffer, unsigned int count)
472{
473 readsw(PCI_IOBASE + addr, buffer, count);
474}
475#endif
476
477#ifndef insl
478#define insl insl
479static inline void insl(unsigned long addr, void *buffer, unsigned int count)
480{
481 readsl(PCI_IOBASE + addr, buffer, count);
482}
483#endif
484
485#ifndef outsb
486#define outsb outsb
487static inline void outsb(unsigned long addr, const void *buffer,
488 unsigned int count)
489{
490 writesb(PCI_IOBASE + addr, buffer, count);
491}
492#endif
493
494#ifndef outsw
495#define outsw outsw
496static inline void outsw(unsigned long addr, const void *buffer,
497 unsigned int count)
498{
499 writesw(PCI_IOBASE + addr, buffer, count);
500}
501#endif
502
503#ifndef outsl
504#define outsl outsl
505static inline void outsl(unsigned long addr, const void *buffer,
506 unsigned int count)
507{
508 writesl(PCI_IOBASE + addr, buffer, count);
509}
510#endif
511
512#ifndef insb_p
513#define insb_p insb_p
514static inline void insb_p(unsigned long addr, void *buffer, unsigned int count)
515{
516 insb(addr, buffer, count);
517}
518#endif
519
520#ifndef insw_p
521#define insw_p insw_p
522static inline void insw_p(unsigned long addr, void *buffer, unsigned int count)
523{
524 insw(addr, buffer, count);
525}
526#endif
527
528#ifndef insl_p
529#define insl_p insl_p
530static inline void insl_p(unsigned long addr, void *buffer, unsigned int count)
531{
532 insl(addr, buffer, count);
533}
534#endif
535
536#ifndef outsb_p
537#define outsb_p outsb_p
538static inline void outsb_p(unsigned long addr, const void *buffer,
539 unsigned int count)
540{
541 outsb(addr, buffer, count);
542}
543#endif
544
545#ifndef outsw_p
546#define outsw_p outsw_p
547static inline void outsw_p(unsigned long addr, const void *buffer,
548 unsigned int count)
549{
550 outsw(addr, buffer, count);
551}
552#endif
553
554#ifndef outsl_p
555#define outsl_p outsl_p
556static inline void outsl_p(unsigned long addr, const void *buffer,
557 unsigned int count)
558{
559 outsl(addr, buffer, count);
560}
561#endif
562
563#ifndef CONFIG_GENERIC_IOMAP
564#ifndef ioread8
565#define ioread8 ioread8
566static inline u8 ioread8(const volatile void __iomem *addr)
567{
568 return readb(addr);
569}
570#endif
571
572#ifndef ioread16
573#define ioread16 ioread16
574static inline u16 ioread16(const volatile void __iomem *addr)
575{
576 return readw(addr);
577}
578#endif
579
580#ifndef ioread32
581#define ioread32 ioread32
582static inline u32 ioread32(const volatile void __iomem *addr)
583{
584 return readl(addr);
585}
586#endif
587
588#ifdef CONFIG_64BIT
589#ifndef ioread64
590#define ioread64 ioread64
591static inline u64 ioread64(const volatile void __iomem *addr)
592{
593 return readq(addr);
594}
595#endif
596#endif /* CONFIG_64BIT */
597
598#ifndef iowrite8
599#define iowrite8 iowrite8
600static inline void iowrite8(u8 value, volatile void __iomem *addr)
601{
602 writeb(value, addr);
603}
604#endif
605
606#ifndef iowrite16
607#define iowrite16 iowrite16
608static inline void iowrite16(u16 value, volatile void __iomem *addr)
609{
610 writew(value, addr);
611}
612#endif
613
614#ifndef iowrite32
615#define iowrite32 iowrite32
616static inline void iowrite32(u32 value, volatile void __iomem *addr)
617{
618 writel(value, addr);
619}
620#endif
621
622#ifdef CONFIG_64BIT
623#ifndef iowrite64
624#define iowrite64 iowrite64
625static inline void iowrite64(u64 value, volatile void __iomem *addr)
626{
627 writeq(value, addr);
628}
629#endif
630#endif /* CONFIG_64BIT */
631
632#ifndef ioread16be
633#define ioread16be ioread16be
634static inline u16 ioread16be(const volatile void __iomem *addr)
635{
636 return swab16(readw(addr));
637}
638#endif
639
640#ifndef ioread32be
641#define ioread32be ioread32be
642static inline u32 ioread32be(const volatile void __iomem *addr)
643{
644 return swab32(readl(addr));
645}
646#endif
647
648#ifdef CONFIG_64BIT
649#ifndef ioread64be
650#define ioread64be ioread64be
651static inline u64 ioread64be(const volatile void __iomem *addr)
652{
653 return swab64(readq(addr));
654}
655#endif
656#endif /* CONFIG_64BIT */
657
658#ifndef iowrite16be
659#define iowrite16be iowrite16be
660static inline void iowrite16be(u16 value, void volatile __iomem *addr)
661{
662 writew(swab16(value), addr);
663}
664#endif
665
666#ifndef iowrite32be
667#define iowrite32be iowrite32be
668static inline void iowrite32be(u32 value, volatile void __iomem *addr)
669{
670 writel(swab32(value), addr);
671}
672#endif
673
674#ifdef CONFIG_64BIT
675#ifndef iowrite64be
676#define iowrite64be iowrite64be
677static inline void iowrite64be(u64 value, volatile void __iomem *addr)
678{
679 writeq(swab64(value), addr);
680}
681#endif
682#endif /* CONFIG_64BIT */
683
684#ifndef ioread8_rep
685#define ioread8_rep ioread8_rep
686static inline void ioread8_rep(const volatile void __iomem *addr, void *buffer,
687 unsigned int count)
688{
689 readsb(addr, buffer, count);
690}
691#endif
692
693#ifndef ioread16_rep
694#define ioread16_rep ioread16_rep
695static inline void ioread16_rep(const volatile void __iomem *addr,
696 void *buffer, unsigned int count)
697{
698 readsw(addr, buffer, count);
699}
700#endif
701
702#ifndef ioread32_rep
703#define ioread32_rep ioread32_rep
704static inline void ioread32_rep(const volatile void __iomem *addr,
705 void *buffer, unsigned int count)
706{
707 readsl(addr, buffer, count);
708}
709#endif
710
711#ifdef CONFIG_64BIT
712#ifndef ioread64_rep
713#define ioread64_rep ioread64_rep
714static inline void ioread64_rep(const volatile void __iomem *addr,
715 void *buffer, unsigned int count)
716{
717 readsq(addr, buffer, count);
718}
719#endif
720#endif /* CONFIG_64BIT */
721
722#ifndef iowrite8_rep
723#define iowrite8_rep iowrite8_rep
724static inline void iowrite8_rep(volatile void __iomem *addr,
725 const void *buffer,
726 unsigned int count)
727{
728 writesb(addr, buffer, count);
729}
730#endif
731
732#ifndef iowrite16_rep
733#define iowrite16_rep iowrite16_rep
734static inline void iowrite16_rep(volatile void __iomem *addr,
735 const void *buffer,
736 unsigned int count)
737{
738 writesw(addr, buffer, count);
739}
740#endif
741
742#ifndef iowrite32_rep
743#define iowrite32_rep iowrite32_rep
744static inline void iowrite32_rep(volatile void __iomem *addr,
745 const void *buffer,
746 unsigned int count)
747{
748 writesl(addr, buffer, count);
749}
750#endif
751
752#ifdef CONFIG_64BIT
753#ifndef iowrite64_rep
754#define iowrite64_rep iowrite64_rep
755static inline void iowrite64_rep(volatile void __iomem *addr,
756 const void *buffer,
757 unsigned int count)
758{
759 writesq(addr, buffer, count);
760}
761#endif
762#endif /* CONFIG_64BIT */
763#endif /* CONFIG_GENERIC_IOMAP */
764
765#ifdef __KERNEL__
766
767#include <linux/vmalloc.h>
768#define __io_virt(x) ((void __force *)(x))
769
770#ifndef CONFIG_GENERIC_IOMAP
771struct pci_dev;
772extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
773
774#ifndef pci_iounmap
775#define pci_iounmap pci_iounmap
776static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p)
777{
778}
779#endif
780#endif /* CONFIG_GENERIC_IOMAP */
781
782/*
783 * Change virtual addresses to physical addresses and vv.
784 * These are pretty trivial
785 */
786#ifndef virt_to_phys
787#define virt_to_phys virt_to_phys
788static inline unsigned long virt_to_phys(volatile void *address)
789{
790 return __pa((unsigned long)address);
791}
792#endif
793
794#ifndef phys_to_virt
795#define phys_to_virt phys_to_virt
796static inline void *phys_to_virt(unsigned long address)
797{
798 return __va(address);
799}
800#endif
801
802/**
803 * DOC: ioremap() and ioremap_*() variants
804 *
805 * If you have an IOMMU your architecture is expected to have both ioremap()
806 * and iounmap() implemented otherwise the asm-generic helpers will provide a
807 * direct mapping.
808 *
809 * There are ioremap_*() call variants, if you have no IOMMU we naturally will
810 * default to direct mapping for all of them, you can override these defaults.
811 * If you have an IOMMU you are highly encouraged to provide your own
812 * ioremap variant implementation as there currently is no safe architecture
813 * agnostic default. To avoid possible improper behaviour default asm-generic
814 * ioremap_*() variants all return NULL when an IOMMU is available. If you've
815 * defined your own ioremap_*() variant you must then declare your own
816 * ioremap_*() variant as defined to itself to avoid the default NULL return.
817 */
818
819#ifdef CONFIG_MMU
820
821#ifndef ioremap_uc
822#define ioremap_uc ioremap_uc
823static inline void __iomem *ioremap_uc(phys_addr_t offset, size_t size)
824{
825 return NULL;
826}
827#endif
828
829#else /* !CONFIG_MMU */
830
831/*
832 * Change "struct page" to physical address.
833 *
834 * This implementation is for the no-MMU case only... if you have an MMU
835 * you'll need to provide your own definitions.
836 */
837
838#ifndef ioremap
839#define ioremap ioremap
840static inline void __iomem *ioremap(phys_addr_t offset, size_t size)
841{
842 return (void __iomem *)(unsigned long)offset;
843}
844#endif
845
846#ifndef __ioremap
847#define __ioremap __ioremap
848static inline void __iomem *__ioremap(phys_addr_t offset, size_t size,
849 unsigned long flags)
850{
851 return ioremap(offset, size);
852}
853#endif
854
855#ifndef ioremap_nocache
856#define ioremap_nocache ioremap_nocache
857static inline void __iomem *ioremap_nocache(phys_addr_t offset, size_t size)
858{
859 return ioremap(offset, size);
860}
861#endif
862
863#ifndef ioremap_uc
864#define ioremap_uc ioremap_uc
865static inline void __iomem *ioremap_uc(phys_addr_t offset, size_t size)
866{
867 return ioremap_nocache(offset, size);
868}
869#endif
870
871#ifndef ioremap_wc
872#define ioremap_wc ioremap_wc
873static inline void __iomem *ioremap_wc(phys_addr_t offset, size_t size)
874{
875 return ioremap_nocache(offset, size);
876}
877#endif
878
879#ifndef ioremap_wt
880#define ioremap_wt ioremap_wt
881static inline void __iomem *ioremap_wt(phys_addr_t offset, size_t size)
882{
883 return ioremap_nocache(offset, size);
884}
885#endif
886
887#ifndef iounmap
888#define iounmap iounmap
889
890static inline void iounmap(void __iomem *addr)
891{
892}
893#endif
894#endif /* CONFIG_MMU */
895
896#ifdef CONFIG_HAS_IOPORT_MAP
897#ifndef CONFIG_GENERIC_IOMAP
898#ifndef ioport_map
899#define ioport_map ioport_map
900static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
901{
902 return PCI_IOBASE + (port & IO_SPACE_LIMIT);
903}
904#endif
905
906#ifndef ioport_unmap
907#define ioport_unmap ioport_unmap
908static inline void ioport_unmap(void __iomem *p)
909{
910}
911#endif
912#else /* CONFIG_GENERIC_IOMAP */
913extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
914extern void ioport_unmap(void __iomem *p);
915#endif /* CONFIG_GENERIC_IOMAP */
916#endif /* CONFIG_HAS_IOPORT_MAP */
917
918#ifndef xlate_dev_kmem_ptr
919#define xlate_dev_kmem_ptr xlate_dev_kmem_ptr
920static inline void *xlate_dev_kmem_ptr(void *addr)
921{
922 return addr;
923}
924#endif
925
926#ifndef xlate_dev_mem_ptr
927#define xlate_dev_mem_ptr xlate_dev_mem_ptr
928static inline void *xlate_dev_mem_ptr(phys_addr_t addr)
929{
930 return __va(addr);
931}
932#endif
933
934#ifndef unxlate_dev_mem_ptr
935#define unxlate_dev_mem_ptr unxlate_dev_mem_ptr
936static inline void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr)
937{
938}
939#endif
940
941#ifdef CONFIG_VIRT_TO_BUS
942#ifndef virt_to_bus
943static inline unsigned long virt_to_bus(void *address)
944{
945 return (unsigned long)address;
946}
947
948static inline void *bus_to_virt(unsigned long address)
949{
950 return (void *)address;
951}
952#endif
953#endif
954
955#ifndef memset_io
956#define memset_io memset_io
957static inline void memset_io(volatile void __iomem *addr, int value,
958 size_t size)
959{
960 memset(__io_virt(addr), value, size);
961}
962#endif
963
964#ifndef memcpy_fromio
965#define memcpy_fromio memcpy_fromio
966static inline void memcpy_fromio(void *buffer,
967 const volatile void __iomem *addr,
968 size_t size)
969{
970 memcpy(buffer, __io_virt(addr), size);
971}
972#endif
973
974#ifndef memcpy_toio
975#define memcpy_toio memcpy_toio
976static inline void memcpy_toio(volatile void __iomem *addr, const void *buffer,
977 size_t size)
978{
979 memcpy(__io_virt(addr), buffer, size);
980}
981#endif
982
983#endif /* __KERNEL__ */
984
985#endif /* __ASM_GENERIC_IO_H */
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/* Generic I/O port emulation.
3 *
4 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
5 * Written by David Howells (dhowells@redhat.com)
6 */
7#ifndef __ASM_GENERIC_IO_H
8#define __ASM_GENERIC_IO_H
9
10#include <asm/page.h> /* I/O is all done through memory accesses */
11#include <linux/string.h> /* for memset() and memcpy() */
12#include <linux/types.h>
13#include <linux/instruction_pointer.h>
14
15#ifdef CONFIG_GENERIC_IOMAP
16#include <asm-generic/iomap.h>
17#endif
18
19#include <asm/mmiowb.h>
20#include <asm-generic/pci_iomap.h>
21
22#ifndef __io_br
23#define __io_br() barrier()
24#endif
25
26/* prevent prefetching of coherent DMA data ahead of a dma-complete */
27#ifndef __io_ar
28#ifdef rmb
29#define __io_ar(v) rmb()
30#else
31#define __io_ar(v) barrier()
32#endif
33#endif
34
35/* flush writes to coherent DMA data before possibly triggering a DMA read */
36#ifndef __io_bw
37#ifdef wmb
38#define __io_bw() wmb()
39#else
40#define __io_bw() barrier()
41#endif
42#endif
43
44/* serialize device access against a spin_unlock, usually handled there. */
45#ifndef __io_aw
46#define __io_aw() mmiowb_set_pending()
47#endif
48
49#ifndef __io_pbw
50#define __io_pbw() __io_bw()
51#endif
52
53#ifndef __io_paw
54#define __io_paw() __io_aw()
55#endif
56
57#ifndef __io_pbr
58#define __io_pbr() __io_br()
59#endif
60
61#ifndef __io_par
62#define __io_par(v) __io_ar(v)
63#endif
64
65/*
66 * "__DISABLE_TRACE_MMIO__" flag can be used to disable MMIO tracing for
67 * specific kernel drivers in case of excessive/unwanted logging.
68 *
69 * Usage: Add a #define flag at the beginning of the driver file.
70 * Ex: #define __DISABLE_TRACE_MMIO__
71 * #include <...>
72 * ...
73 */
74#if IS_ENABLED(CONFIG_TRACE_MMIO_ACCESS) && !(defined(__DISABLE_TRACE_MMIO__))
75#include <linux/tracepoint-defs.h>
76
77DECLARE_TRACEPOINT(rwmmio_write);
78DECLARE_TRACEPOINT(rwmmio_post_write);
79DECLARE_TRACEPOINT(rwmmio_read);
80DECLARE_TRACEPOINT(rwmmio_post_read);
81
82void log_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
83 unsigned long caller_addr, unsigned long caller_addr0);
84void log_post_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
85 unsigned long caller_addr, unsigned long caller_addr0);
86void log_read_mmio(u8 width, const volatile void __iomem *addr,
87 unsigned long caller_addr, unsigned long caller_addr0);
88void log_post_read_mmio(u64 val, u8 width, const volatile void __iomem *addr,
89 unsigned long caller_addr, unsigned long caller_addr0);
90
91#else
92
93static inline void log_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
94 unsigned long caller_addr, unsigned long caller_addr0) {}
95static inline void log_post_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
96 unsigned long caller_addr, unsigned long caller_addr0) {}
97static inline void log_read_mmio(u8 width, const volatile void __iomem *addr,
98 unsigned long caller_addr, unsigned long caller_addr0) {}
99static inline void log_post_read_mmio(u64 val, u8 width, const volatile void __iomem *addr,
100 unsigned long caller_addr, unsigned long caller_addr0) {}
101
102#endif /* CONFIG_TRACE_MMIO_ACCESS */
103
104/*
105 * __raw_{read,write}{b,w,l,q}() access memory in native endianness.
106 *
107 * On some architectures memory mapped IO needs to be accessed differently.
108 * On the simple architectures, we just read/write the memory location
109 * directly.
110 */
111
112#ifndef __raw_readb
113#define __raw_readb __raw_readb
114static inline u8 __raw_readb(const volatile void __iomem *addr)
115{
116 return *(const volatile u8 __force *)addr;
117}
118#endif
119
120#ifndef __raw_readw
121#define __raw_readw __raw_readw
122static inline u16 __raw_readw(const volatile void __iomem *addr)
123{
124 return *(const volatile u16 __force *)addr;
125}
126#endif
127
128#ifndef __raw_readl
129#define __raw_readl __raw_readl
130static inline u32 __raw_readl(const volatile void __iomem *addr)
131{
132 return *(const volatile u32 __force *)addr;
133}
134#endif
135
136#ifdef CONFIG_64BIT
137#ifndef __raw_readq
138#define __raw_readq __raw_readq
139static inline u64 __raw_readq(const volatile void __iomem *addr)
140{
141 return *(const volatile u64 __force *)addr;
142}
143#endif
144#endif /* CONFIG_64BIT */
145
146#ifndef __raw_writeb
147#define __raw_writeb __raw_writeb
148static inline void __raw_writeb(u8 value, volatile void __iomem *addr)
149{
150 *(volatile u8 __force *)addr = value;
151}
152#endif
153
154#ifndef __raw_writew
155#define __raw_writew __raw_writew
156static inline void __raw_writew(u16 value, volatile void __iomem *addr)
157{
158 *(volatile u16 __force *)addr = value;
159}
160#endif
161
162#ifndef __raw_writel
163#define __raw_writel __raw_writel
164static inline void __raw_writel(u32 value, volatile void __iomem *addr)
165{
166 *(volatile u32 __force *)addr = value;
167}
168#endif
169
170#ifdef CONFIG_64BIT
171#ifndef __raw_writeq
172#define __raw_writeq __raw_writeq
173static inline void __raw_writeq(u64 value, volatile void __iomem *addr)
174{
175 *(volatile u64 __force *)addr = value;
176}
177#endif
178#endif /* CONFIG_64BIT */
179
180/*
181 * {read,write}{b,w,l,q}() access little endian memory and return result in
182 * native endianness.
183 */
184
185#ifndef readb
186#define readb readb
187static inline u8 readb(const volatile void __iomem *addr)
188{
189 u8 val;
190
191 log_read_mmio(8, addr, _THIS_IP_, _RET_IP_);
192 __io_br();
193 val = __raw_readb(addr);
194 __io_ar(val);
195 log_post_read_mmio(val, 8, addr, _THIS_IP_, _RET_IP_);
196 return val;
197}
198#endif
199
200#ifndef readw
201#define readw readw
202static inline u16 readw(const volatile void __iomem *addr)
203{
204 u16 val;
205
206 log_read_mmio(16, addr, _THIS_IP_, _RET_IP_);
207 __io_br();
208 val = __le16_to_cpu((__le16 __force)__raw_readw(addr));
209 __io_ar(val);
210 log_post_read_mmio(val, 16, addr, _THIS_IP_, _RET_IP_);
211 return val;
212}
213#endif
214
215#ifndef readl
216#define readl readl
217static inline u32 readl(const volatile void __iomem *addr)
218{
219 u32 val;
220
221 log_read_mmio(32, addr, _THIS_IP_, _RET_IP_);
222 __io_br();
223 val = __le32_to_cpu((__le32 __force)__raw_readl(addr));
224 __io_ar(val);
225 log_post_read_mmio(val, 32, addr, _THIS_IP_, _RET_IP_);
226 return val;
227}
228#endif
229
230#ifdef CONFIG_64BIT
231#ifndef readq
232#define readq readq
233static inline u64 readq(const volatile void __iomem *addr)
234{
235 u64 val;
236
237 log_read_mmio(64, addr, _THIS_IP_, _RET_IP_);
238 __io_br();
239 val = __le64_to_cpu((__le64 __force)__raw_readq(addr));
240 __io_ar(val);
241 log_post_read_mmio(val, 64, addr, _THIS_IP_, _RET_IP_);
242 return val;
243}
244#endif
245#endif /* CONFIG_64BIT */
246
247#ifndef writeb
248#define writeb writeb
249static inline void writeb(u8 value, volatile void __iomem *addr)
250{
251 log_write_mmio(value, 8, addr, _THIS_IP_, _RET_IP_);
252 __io_bw();
253 __raw_writeb(value, addr);
254 __io_aw();
255 log_post_write_mmio(value, 8, addr, _THIS_IP_, _RET_IP_);
256}
257#endif
258
259#ifndef writew
260#define writew writew
261static inline void writew(u16 value, volatile void __iomem *addr)
262{
263 log_write_mmio(value, 16, addr, _THIS_IP_, _RET_IP_);
264 __io_bw();
265 __raw_writew((u16 __force)cpu_to_le16(value), addr);
266 __io_aw();
267 log_post_write_mmio(value, 16, addr, _THIS_IP_, _RET_IP_);
268}
269#endif
270
271#ifndef writel
272#define writel writel
273static inline void writel(u32 value, volatile void __iomem *addr)
274{
275 log_write_mmio(value, 32, addr, _THIS_IP_, _RET_IP_);
276 __io_bw();
277 __raw_writel((u32 __force)__cpu_to_le32(value), addr);
278 __io_aw();
279 log_post_write_mmio(value, 32, addr, _THIS_IP_, _RET_IP_);
280}
281#endif
282
283#ifdef CONFIG_64BIT
284#ifndef writeq
285#define writeq writeq
286static inline void writeq(u64 value, volatile void __iomem *addr)
287{
288 log_write_mmio(value, 64, addr, _THIS_IP_, _RET_IP_);
289 __io_bw();
290 __raw_writeq((u64 __force)__cpu_to_le64(value), addr);
291 __io_aw();
292 log_post_write_mmio(value, 64, addr, _THIS_IP_, _RET_IP_);
293}
294#endif
295#endif /* CONFIG_64BIT */
296
297/*
298 * {read,write}{b,w,l,q}_relaxed() are like the regular version, but
299 * are not guaranteed to provide ordering against spinlocks or memory
300 * accesses.
301 */
302#ifndef readb_relaxed
303#define readb_relaxed readb_relaxed
304static inline u8 readb_relaxed(const volatile void __iomem *addr)
305{
306 u8 val;
307
308 log_read_mmio(8, addr, _THIS_IP_, _RET_IP_);
309 val = __raw_readb(addr);
310 log_post_read_mmio(val, 8, addr, _THIS_IP_, _RET_IP_);
311 return val;
312}
313#endif
314
315#ifndef readw_relaxed
316#define readw_relaxed readw_relaxed
317static inline u16 readw_relaxed(const volatile void __iomem *addr)
318{
319 u16 val;
320
321 log_read_mmio(16, addr, _THIS_IP_, _RET_IP_);
322 val = __le16_to_cpu((__le16 __force)__raw_readw(addr));
323 log_post_read_mmio(val, 16, addr, _THIS_IP_, _RET_IP_);
324 return val;
325}
326#endif
327
328#ifndef readl_relaxed
329#define readl_relaxed readl_relaxed
330static inline u32 readl_relaxed(const volatile void __iomem *addr)
331{
332 u32 val;
333
334 log_read_mmio(32, addr, _THIS_IP_, _RET_IP_);
335 val = __le32_to_cpu((__le32 __force)__raw_readl(addr));
336 log_post_read_mmio(val, 32, addr, _THIS_IP_, _RET_IP_);
337 return val;
338}
339#endif
340
341#if defined(readq) && !defined(readq_relaxed)
342#define readq_relaxed readq_relaxed
343static inline u64 readq_relaxed(const volatile void __iomem *addr)
344{
345 u64 val;
346
347 log_read_mmio(64, addr, _THIS_IP_, _RET_IP_);
348 val = __le64_to_cpu((__le64 __force)__raw_readq(addr));
349 log_post_read_mmio(val, 64, addr, _THIS_IP_, _RET_IP_);
350 return val;
351}
352#endif
353
354#ifndef writeb_relaxed
355#define writeb_relaxed writeb_relaxed
356static inline void writeb_relaxed(u8 value, volatile void __iomem *addr)
357{
358 log_write_mmio(value, 8, addr, _THIS_IP_, _RET_IP_);
359 __raw_writeb(value, addr);
360 log_post_write_mmio(value, 8, addr, _THIS_IP_, _RET_IP_);
361}
362#endif
363
364#ifndef writew_relaxed
365#define writew_relaxed writew_relaxed
366static inline void writew_relaxed(u16 value, volatile void __iomem *addr)
367{
368 log_write_mmio(value, 16, addr, _THIS_IP_, _RET_IP_);
369 __raw_writew((u16 __force)cpu_to_le16(value), addr);
370 log_post_write_mmio(value, 16, addr, _THIS_IP_, _RET_IP_);
371}
372#endif
373
374#ifndef writel_relaxed
375#define writel_relaxed writel_relaxed
376static inline void writel_relaxed(u32 value, volatile void __iomem *addr)
377{
378 log_write_mmio(value, 32, addr, _THIS_IP_, _RET_IP_);
379 __raw_writel((u32 __force)__cpu_to_le32(value), addr);
380 log_post_write_mmio(value, 32, addr, _THIS_IP_, _RET_IP_);
381}
382#endif
383
384#if defined(writeq) && !defined(writeq_relaxed)
385#define writeq_relaxed writeq_relaxed
386static inline void writeq_relaxed(u64 value, volatile void __iomem *addr)
387{
388 log_write_mmio(value, 64, addr, _THIS_IP_, _RET_IP_);
389 __raw_writeq((u64 __force)__cpu_to_le64(value), addr);
390 log_post_write_mmio(value, 64, addr, _THIS_IP_, _RET_IP_);
391}
392#endif
393
394/*
395 * {read,write}s{b,w,l,q}() repeatedly access the same memory address in
396 * native endianness in 8-, 16-, 32- or 64-bit chunks (@count times).
397 */
398#ifndef readsb
399#define readsb readsb
400static inline void readsb(const volatile void __iomem *addr, void *buffer,
401 unsigned int count)
402{
403 if (count) {
404 u8 *buf = buffer;
405
406 do {
407 u8 x = __raw_readb(addr);
408 *buf++ = x;
409 } while (--count);
410 }
411}
412#endif
413
414#ifndef readsw
415#define readsw readsw
416static inline void readsw(const volatile void __iomem *addr, void *buffer,
417 unsigned int count)
418{
419 if (count) {
420 u16 *buf = buffer;
421
422 do {
423 u16 x = __raw_readw(addr);
424 *buf++ = x;
425 } while (--count);
426 }
427}
428#endif
429
430#ifndef readsl
431#define readsl readsl
432static inline void readsl(const volatile void __iomem *addr, void *buffer,
433 unsigned int count)
434{
435 if (count) {
436 u32 *buf = buffer;
437
438 do {
439 u32 x = __raw_readl(addr);
440 *buf++ = x;
441 } while (--count);
442 }
443}
444#endif
445
446#ifdef CONFIG_64BIT
447#ifndef readsq
448#define readsq readsq
449static inline void readsq(const volatile void __iomem *addr, void *buffer,
450 unsigned int count)
451{
452 if (count) {
453 u64 *buf = buffer;
454
455 do {
456 u64 x = __raw_readq(addr);
457 *buf++ = x;
458 } while (--count);
459 }
460}
461#endif
462#endif /* CONFIG_64BIT */
463
464#ifndef writesb
465#define writesb writesb
466static inline void writesb(volatile void __iomem *addr, const void *buffer,
467 unsigned int count)
468{
469 if (count) {
470 const u8 *buf = buffer;
471
472 do {
473 __raw_writeb(*buf++, addr);
474 } while (--count);
475 }
476}
477#endif
478
479#ifndef writesw
480#define writesw writesw
481static inline void writesw(volatile void __iomem *addr, const void *buffer,
482 unsigned int count)
483{
484 if (count) {
485 const u16 *buf = buffer;
486
487 do {
488 __raw_writew(*buf++, addr);
489 } while (--count);
490 }
491}
492#endif
493
494#ifndef writesl
495#define writesl writesl
496static inline void writesl(volatile void __iomem *addr, const void *buffer,
497 unsigned int count)
498{
499 if (count) {
500 const u32 *buf = buffer;
501
502 do {
503 __raw_writel(*buf++, addr);
504 } while (--count);
505 }
506}
507#endif
508
509#ifdef CONFIG_64BIT
510#ifndef writesq
511#define writesq writesq
512static inline void writesq(volatile void __iomem *addr, const void *buffer,
513 unsigned int count)
514{
515 if (count) {
516 const u64 *buf = buffer;
517
518 do {
519 __raw_writeq(*buf++, addr);
520 } while (--count);
521 }
522}
523#endif
524#endif /* CONFIG_64BIT */
525
526#ifndef PCI_IOBASE
527#define PCI_IOBASE ((void __iomem *)0)
528#endif
529
530#ifndef IO_SPACE_LIMIT
531#define IO_SPACE_LIMIT 0xffff
532#endif
533
534/*
535 * {in,out}{b,w,l}() access little endian I/O. {in,out}{b,w,l}_p() can be
536 * implemented on hardware that needs an additional delay for I/O accesses to
537 * take effect.
538 */
539
540#if !defined(inb) && !defined(_inb)
541#define _inb _inb
542static inline u8 _inb(unsigned long addr)
543{
544 u8 val;
545
546 __io_pbr();
547 val = __raw_readb(PCI_IOBASE + addr);
548 __io_par(val);
549 return val;
550}
551#endif
552
553#if !defined(inw) && !defined(_inw)
554#define _inw _inw
555static inline u16 _inw(unsigned long addr)
556{
557 u16 val;
558
559 __io_pbr();
560 val = __le16_to_cpu((__le16 __force)__raw_readw(PCI_IOBASE + addr));
561 __io_par(val);
562 return val;
563}
564#endif
565
566#if !defined(inl) && !defined(_inl)
567#define _inl _inl
568static inline u32 _inl(unsigned long addr)
569{
570 u32 val;
571
572 __io_pbr();
573 val = __le32_to_cpu((__le32 __force)__raw_readl(PCI_IOBASE + addr));
574 __io_par(val);
575 return val;
576}
577#endif
578
579#if !defined(outb) && !defined(_outb)
580#define _outb _outb
581static inline void _outb(u8 value, unsigned long addr)
582{
583 __io_pbw();
584 __raw_writeb(value, PCI_IOBASE + addr);
585 __io_paw();
586}
587#endif
588
589#if !defined(outw) && !defined(_outw)
590#define _outw _outw
591static inline void _outw(u16 value, unsigned long addr)
592{
593 __io_pbw();
594 __raw_writew((u16 __force)cpu_to_le16(value), PCI_IOBASE + addr);
595 __io_paw();
596}
597#endif
598
599#if !defined(outl) && !defined(_outl)
600#define _outl _outl
601static inline void _outl(u32 value, unsigned long addr)
602{
603 __io_pbw();
604 __raw_writel((u32 __force)cpu_to_le32(value), PCI_IOBASE + addr);
605 __io_paw();
606}
607#endif
608
609#include <linux/logic_pio.h>
610
611#ifndef inb
612#define inb _inb
613#endif
614
615#ifndef inw
616#define inw _inw
617#endif
618
619#ifndef inl
620#define inl _inl
621#endif
622
623#ifndef outb
624#define outb _outb
625#endif
626
627#ifndef outw
628#define outw _outw
629#endif
630
631#ifndef outl
632#define outl _outl
633#endif
634
635#ifndef inb_p
636#define inb_p inb_p
637static inline u8 inb_p(unsigned long addr)
638{
639 return inb(addr);
640}
641#endif
642
643#ifndef inw_p
644#define inw_p inw_p
645static inline u16 inw_p(unsigned long addr)
646{
647 return inw(addr);
648}
649#endif
650
651#ifndef inl_p
652#define inl_p inl_p
653static inline u32 inl_p(unsigned long addr)
654{
655 return inl(addr);
656}
657#endif
658
659#ifndef outb_p
660#define outb_p outb_p
661static inline void outb_p(u8 value, unsigned long addr)
662{
663 outb(value, addr);
664}
665#endif
666
667#ifndef outw_p
668#define outw_p outw_p
669static inline void outw_p(u16 value, unsigned long addr)
670{
671 outw(value, addr);
672}
673#endif
674
675#ifndef outl_p
676#define outl_p outl_p
677static inline void outl_p(u32 value, unsigned long addr)
678{
679 outl(value, addr);
680}
681#endif
682
683/*
684 * {in,out}s{b,w,l}{,_p}() are variants of the above that repeatedly access a
685 * single I/O port multiple times.
686 */
687
688#ifndef insb
689#define insb insb
690static inline void insb(unsigned long addr, void *buffer, unsigned int count)
691{
692 readsb(PCI_IOBASE + addr, buffer, count);
693}
694#endif
695
696#ifndef insw
697#define insw insw
698static inline void insw(unsigned long addr, void *buffer, unsigned int count)
699{
700 readsw(PCI_IOBASE + addr, buffer, count);
701}
702#endif
703
704#ifndef insl
705#define insl insl
706static inline void insl(unsigned long addr, void *buffer, unsigned int count)
707{
708 readsl(PCI_IOBASE + addr, buffer, count);
709}
710#endif
711
712#ifndef outsb
713#define outsb outsb
714static inline void outsb(unsigned long addr, const void *buffer,
715 unsigned int count)
716{
717 writesb(PCI_IOBASE + addr, buffer, count);
718}
719#endif
720
721#ifndef outsw
722#define outsw outsw
723static inline void outsw(unsigned long addr, const void *buffer,
724 unsigned int count)
725{
726 writesw(PCI_IOBASE + addr, buffer, count);
727}
728#endif
729
730#ifndef outsl
731#define outsl outsl
732static inline void outsl(unsigned long addr, const void *buffer,
733 unsigned int count)
734{
735 writesl(PCI_IOBASE + addr, buffer, count);
736}
737#endif
738
739#ifndef insb_p
740#define insb_p insb_p
741static inline void insb_p(unsigned long addr, void *buffer, unsigned int count)
742{
743 insb(addr, buffer, count);
744}
745#endif
746
747#ifndef insw_p
748#define insw_p insw_p
749static inline void insw_p(unsigned long addr, void *buffer, unsigned int count)
750{
751 insw(addr, buffer, count);
752}
753#endif
754
755#ifndef insl_p
756#define insl_p insl_p
757static inline void insl_p(unsigned long addr, void *buffer, unsigned int count)
758{
759 insl(addr, buffer, count);
760}
761#endif
762
763#ifndef outsb_p
764#define outsb_p outsb_p
765static inline void outsb_p(unsigned long addr, const void *buffer,
766 unsigned int count)
767{
768 outsb(addr, buffer, count);
769}
770#endif
771
772#ifndef outsw_p
773#define outsw_p outsw_p
774static inline void outsw_p(unsigned long addr, const void *buffer,
775 unsigned int count)
776{
777 outsw(addr, buffer, count);
778}
779#endif
780
781#ifndef outsl_p
782#define outsl_p outsl_p
783static inline void outsl_p(unsigned long addr, const void *buffer,
784 unsigned int count)
785{
786 outsl(addr, buffer, count);
787}
788#endif
789
790#ifndef CONFIG_GENERIC_IOMAP
791#ifndef ioread8
792#define ioread8 ioread8
793static inline u8 ioread8(const volatile void __iomem *addr)
794{
795 return readb(addr);
796}
797#endif
798
799#ifndef ioread16
800#define ioread16 ioread16
801static inline u16 ioread16(const volatile void __iomem *addr)
802{
803 return readw(addr);
804}
805#endif
806
807#ifndef ioread32
808#define ioread32 ioread32
809static inline u32 ioread32(const volatile void __iomem *addr)
810{
811 return readl(addr);
812}
813#endif
814
815#ifdef CONFIG_64BIT
816#ifndef ioread64
817#define ioread64 ioread64
818static inline u64 ioread64(const volatile void __iomem *addr)
819{
820 return readq(addr);
821}
822#endif
823#endif /* CONFIG_64BIT */
824
825#ifndef iowrite8
826#define iowrite8 iowrite8
827static inline void iowrite8(u8 value, volatile void __iomem *addr)
828{
829 writeb(value, addr);
830}
831#endif
832
833#ifndef iowrite16
834#define iowrite16 iowrite16
835static inline void iowrite16(u16 value, volatile void __iomem *addr)
836{
837 writew(value, addr);
838}
839#endif
840
841#ifndef iowrite32
842#define iowrite32 iowrite32
843static inline void iowrite32(u32 value, volatile void __iomem *addr)
844{
845 writel(value, addr);
846}
847#endif
848
849#ifdef CONFIG_64BIT
850#ifndef iowrite64
851#define iowrite64 iowrite64
852static inline void iowrite64(u64 value, volatile void __iomem *addr)
853{
854 writeq(value, addr);
855}
856#endif
857#endif /* CONFIG_64BIT */
858
859#ifndef ioread16be
860#define ioread16be ioread16be
861static inline u16 ioread16be(const volatile void __iomem *addr)
862{
863 return swab16(readw(addr));
864}
865#endif
866
867#ifndef ioread32be
868#define ioread32be ioread32be
869static inline u32 ioread32be(const volatile void __iomem *addr)
870{
871 return swab32(readl(addr));
872}
873#endif
874
875#ifdef CONFIG_64BIT
876#ifndef ioread64be
877#define ioread64be ioread64be
878static inline u64 ioread64be(const volatile void __iomem *addr)
879{
880 return swab64(readq(addr));
881}
882#endif
883#endif /* CONFIG_64BIT */
884
885#ifndef iowrite16be
886#define iowrite16be iowrite16be
887static inline void iowrite16be(u16 value, void volatile __iomem *addr)
888{
889 writew(swab16(value), addr);
890}
891#endif
892
893#ifndef iowrite32be
894#define iowrite32be iowrite32be
895static inline void iowrite32be(u32 value, volatile void __iomem *addr)
896{
897 writel(swab32(value), addr);
898}
899#endif
900
901#ifdef CONFIG_64BIT
902#ifndef iowrite64be
903#define iowrite64be iowrite64be
904static inline void iowrite64be(u64 value, volatile void __iomem *addr)
905{
906 writeq(swab64(value), addr);
907}
908#endif
909#endif /* CONFIG_64BIT */
910
911#ifndef ioread8_rep
912#define ioread8_rep ioread8_rep
913static inline void ioread8_rep(const volatile void __iomem *addr, void *buffer,
914 unsigned int count)
915{
916 readsb(addr, buffer, count);
917}
918#endif
919
920#ifndef ioread16_rep
921#define ioread16_rep ioread16_rep
922static inline void ioread16_rep(const volatile void __iomem *addr,
923 void *buffer, unsigned int count)
924{
925 readsw(addr, buffer, count);
926}
927#endif
928
929#ifndef ioread32_rep
930#define ioread32_rep ioread32_rep
931static inline void ioread32_rep(const volatile void __iomem *addr,
932 void *buffer, unsigned int count)
933{
934 readsl(addr, buffer, count);
935}
936#endif
937
938#ifdef CONFIG_64BIT
939#ifndef ioread64_rep
940#define ioread64_rep ioread64_rep
941static inline void ioread64_rep(const volatile void __iomem *addr,
942 void *buffer, unsigned int count)
943{
944 readsq(addr, buffer, count);
945}
946#endif
947#endif /* CONFIG_64BIT */
948
949#ifndef iowrite8_rep
950#define iowrite8_rep iowrite8_rep
951static inline void iowrite8_rep(volatile void __iomem *addr,
952 const void *buffer,
953 unsigned int count)
954{
955 writesb(addr, buffer, count);
956}
957#endif
958
959#ifndef iowrite16_rep
960#define iowrite16_rep iowrite16_rep
961static inline void iowrite16_rep(volatile void __iomem *addr,
962 const void *buffer,
963 unsigned int count)
964{
965 writesw(addr, buffer, count);
966}
967#endif
968
969#ifndef iowrite32_rep
970#define iowrite32_rep iowrite32_rep
971static inline void iowrite32_rep(volatile void __iomem *addr,
972 const void *buffer,
973 unsigned int count)
974{
975 writesl(addr, buffer, count);
976}
977#endif
978
979#ifdef CONFIG_64BIT
980#ifndef iowrite64_rep
981#define iowrite64_rep iowrite64_rep
982static inline void iowrite64_rep(volatile void __iomem *addr,
983 const void *buffer,
984 unsigned int count)
985{
986 writesq(addr, buffer, count);
987}
988#endif
989#endif /* CONFIG_64BIT */
990#endif /* CONFIG_GENERIC_IOMAP */
991
992#ifdef __KERNEL__
993
994#include <linux/vmalloc.h>
995#define __io_virt(x) ((void __force *)(x))
996
997/*
998 * Change virtual addresses to physical addresses and vv.
999 * These are pretty trivial
1000 */
1001#ifndef virt_to_phys
1002#define virt_to_phys virt_to_phys
1003static inline unsigned long virt_to_phys(volatile void *address)
1004{
1005 return __pa((unsigned long)address);
1006}
1007#endif
1008
1009#ifndef phys_to_virt
1010#define phys_to_virt phys_to_virt
1011static inline void *phys_to_virt(unsigned long address)
1012{
1013 return __va(address);
1014}
1015#endif
1016
1017/**
1018 * DOC: ioremap() and ioremap_*() variants
1019 *
1020 * Architectures with an MMU are expected to provide ioremap() and iounmap()
1021 * themselves or rely on GENERIC_IOREMAP. For NOMMU architectures we provide
1022 * a default nop-op implementation that expect that the physical address used
1023 * for MMIO are already marked as uncached, and can be used as kernel virtual
1024 * addresses.
1025 *
1026 * ioremap_wc() and ioremap_wt() can provide more relaxed caching attributes
1027 * for specific drivers if the architecture choses to implement them. If they
1028 * are not implemented we fall back to plain ioremap. Conversely, ioremap_np()
1029 * can provide stricter non-posted write semantics if the architecture
1030 * implements them.
1031 */
1032#ifndef CONFIG_MMU
1033#ifndef ioremap
1034#define ioremap ioremap
1035static inline void __iomem *ioremap(phys_addr_t offset, size_t size)
1036{
1037 return (void __iomem *)(unsigned long)offset;
1038}
1039#endif
1040
1041#ifndef iounmap
1042#define iounmap iounmap
1043static inline void iounmap(volatile void __iomem *addr)
1044{
1045}
1046#endif
1047#elif defined(CONFIG_GENERIC_IOREMAP)
1048#include <linux/pgtable.h>
1049
1050void __iomem *generic_ioremap_prot(phys_addr_t phys_addr, size_t size,
1051 pgprot_t prot);
1052
1053void __iomem *ioremap_prot(phys_addr_t phys_addr, size_t size,
1054 unsigned long prot);
1055void iounmap(volatile void __iomem *addr);
1056void generic_iounmap(volatile void __iomem *addr);
1057
1058#ifndef ioremap
1059#define ioremap ioremap
1060static inline void __iomem *ioremap(phys_addr_t addr, size_t size)
1061{
1062 /* _PAGE_IOREMAP needs to be supplied by the architecture */
1063 return ioremap_prot(addr, size, _PAGE_IOREMAP);
1064}
1065#endif
1066#endif /* !CONFIG_MMU || CONFIG_GENERIC_IOREMAP */
1067
1068#ifndef ioremap_wc
1069#define ioremap_wc ioremap
1070#endif
1071
1072#ifndef ioremap_wt
1073#define ioremap_wt ioremap
1074#endif
1075
1076/*
1077 * ioremap_uc is special in that we do require an explicit architecture
1078 * implementation. In general you do not want to use this function in a
1079 * driver and use plain ioremap, which is uncached by default. Similarly
1080 * architectures should not implement it unless they have a very good
1081 * reason.
1082 */
1083#ifndef ioremap_uc
1084#define ioremap_uc ioremap_uc
1085static inline void __iomem *ioremap_uc(phys_addr_t offset, size_t size)
1086{
1087 return NULL;
1088}
1089#endif
1090
1091/*
1092 * ioremap_np needs an explicit architecture implementation, as it
1093 * requests stronger semantics than regular ioremap(). Portable drivers
1094 * should instead use one of the higher-level abstractions, like
1095 * devm_ioremap_resource(), to choose the correct variant for any given
1096 * device and bus. Portable drivers with a good reason to want non-posted
1097 * write semantics should always provide an ioremap() fallback in case
1098 * ioremap_np() is not available.
1099 */
1100#ifndef ioremap_np
1101#define ioremap_np ioremap_np
1102static inline void __iomem *ioremap_np(phys_addr_t offset, size_t size)
1103{
1104 return NULL;
1105}
1106#endif
1107
1108#ifdef CONFIG_HAS_IOPORT_MAP
1109#ifndef CONFIG_GENERIC_IOMAP
1110#ifndef ioport_map
1111#define ioport_map ioport_map
1112static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
1113{
1114 port &= IO_SPACE_LIMIT;
1115 return (port > MMIO_UPPER_LIMIT) ? NULL : PCI_IOBASE + port;
1116}
1117#define ARCH_HAS_GENERIC_IOPORT_MAP
1118#endif
1119
1120#ifndef ioport_unmap
1121#define ioport_unmap ioport_unmap
1122static inline void ioport_unmap(void __iomem *p)
1123{
1124}
1125#endif
1126#else /* CONFIG_GENERIC_IOMAP */
1127extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
1128extern void ioport_unmap(void __iomem *p);
1129#endif /* CONFIG_GENERIC_IOMAP */
1130#endif /* CONFIG_HAS_IOPORT_MAP */
1131
1132#ifndef CONFIG_GENERIC_IOMAP
1133#ifndef pci_iounmap
1134#define ARCH_WANTS_GENERIC_PCI_IOUNMAP
1135#endif
1136#endif
1137
1138#ifndef xlate_dev_mem_ptr
1139#define xlate_dev_mem_ptr xlate_dev_mem_ptr
1140static inline void *xlate_dev_mem_ptr(phys_addr_t addr)
1141{
1142 return __va(addr);
1143}
1144#endif
1145
1146#ifndef unxlate_dev_mem_ptr
1147#define unxlate_dev_mem_ptr unxlate_dev_mem_ptr
1148static inline void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr)
1149{
1150}
1151#endif
1152
1153#ifndef memset_io
1154#define memset_io memset_io
1155/**
1156 * memset_io Set a range of I/O memory to a constant value
1157 * @addr: The beginning of the I/O-memory range to set
1158 * @val: The value to set the memory to
1159 * @count: The number of bytes to set
1160 *
1161 * Set a range of I/O memory to a given value.
1162 */
1163static inline void memset_io(volatile void __iomem *addr, int value,
1164 size_t size)
1165{
1166 memset(__io_virt(addr), value, size);
1167}
1168#endif
1169
1170#ifndef memcpy_fromio
1171#define memcpy_fromio memcpy_fromio
1172/**
1173 * memcpy_fromio Copy a block of data from I/O memory
1174 * @dst: The (RAM) destination for the copy
1175 * @src: The (I/O memory) source for the data
1176 * @count: The number of bytes to copy
1177 *
1178 * Copy a block of data from I/O memory.
1179 */
1180static inline void memcpy_fromio(void *buffer,
1181 const volatile void __iomem *addr,
1182 size_t size)
1183{
1184 memcpy(buffer, __io_virt(addr), size);
1185}
1186#endif
1187
1188#ifndef memcpy_toio
1189#define memcpy_toio memcpy_toio
1190/**
1191 * memcpy_toio Copy a block of data into I/O memory
1192 * @dst: The (I/O memory) destination for the copy
1193 * @src: The (RAM) source for the data
1194 * @count: The number of bytes to copy
1195 *
1196 * Copy a block of data to I/O memory.
1197 */
1198static inline void memcpy_toio(volatile void __iomem *addr, const void *buffer,
1199 size_t size)
1200{
1201 memcpy(__io_virt(addr), buffer, size);
1202}
1203#endif
1204
1205extern int devmem_is_allowed(unsigned long pfn);
1206
1207#endif /* __KERNEL__ */
1208
1209#endif /* __ASM_GENERIC_IO_H */