1/* SPDX-License-Identifier: GPL-2.0 */
  2#ifndef __ASM_ARCH_REGS_AC97_H
  3#define __ASM_ARCH_REGS_AC97_H
  4
  5/*
  6 * AC97 Controller registers
  7 */
  8
  9#define POCR		(0x0000)  	/* PCM Out Control Register */
 10#define POCR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
 11#define POCR_FSRIE	(1 << 1)	/* FIFO Service Request Interrupt Enable */
 12
 13#define PICR		(0x0004) 	/* PCM In Control Register */
 14#define PICR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
 15#define PICR_FSRIE	(1 << 1)	/* FIFO Service Request Interrupt Enable */
 16
 17#define MCCR		(0x0008)  	/* Mic In Control Register */
 18#define MCCR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
 19#define MCCR_FSRIE	(1 << 1)	/* FIFO Service Request Interrupt Enable */
 20
 21#define GCR		(0x000C) 	 /* Global Control Register */
 22#ifdef CONFIG_PXA3xx
 23#define GCR_CLKBPB	(1 << 31)	/* Internal clock enable */
 24#endif
 25#define GCR_nDMAEN	(1 << 24)	/* non DMA Enable */
 26#define GCR_CDONE_IE	(1 << 19)	/* Command Done Interrupt Enable */
 27#define GCR_SDONE_IE	(1 << 18)	/* Status Done Interrupt Enable */
 28#define GCR_SECRDY_IEN	(1 << 9)	/* Secondary Ready Interrupt Enable */
 29#define GCR_PRIRDY_IEN	(1 << 8)	/* Primary Ready Interrupt Enable */
 30#define GCR_SECRES_IEN	(1 << 5)	/* Secondary Resume Interrupt Enable */
 31#define GCR_PRIRES_IEN	(1 << 4)	/* Primary Resume Interrupt Enable */
 32#define GCR_ACLINK_OFF	(1 << 3)	/* AC-link Shut Off */
 33#define GCR_WARM_RST	(1 << 2)	/* AC97 Warm Reset */
 34#define GCR_COLD_RST	(1 << 1)	/* AC'97 Cold Reset (0 = active) */
 35#define GCR_GIE		(1 << 0)	/* Codec GPI Interrupt Enable */
 36
 37#define POSR		(0x0010)  	/* PCM Out Status Register */
 38#define POSR_FIFOE	(1 << 4)	/* FIFO error */
 39#define POSR_FSR	(1 << 2)	/* FIFO Service Request */
 40
 41#define PISR		(0x0014)  	/* PCM In Status Register */
 42#define PISR_FIFOE	(1 << 4)	/* FIFO error */
 43#define PISR_EOC	(1 << 3)	/* DMA End-of-Chain (exclusive clear) */
 44#define PISR_FSR	(1 << 2)	/* FIFO Service Request */
 45
 46#define MCSR		(0x0018)  	/* Mic In Status Register */
 47#define MCSR_FIFOE	(1 << 4)	/* FIFO error */
 48#define MCSR_EOC	(1 << 3)	/* DMA End-of-Chain (exclusive clear) */
 49#define MCSR_FSR	(1 << 2)	/* FIFO Service Request */
 50
 51#define GSR		(0x001C)  	/* Global Status Register */
 52#define GSR_CDONE	(1 << 19)	/* Command Done */
 53#define GSR_SDONE	(1 << 18)	/* Status Done */
 54#define GSR_RDCS	(1 << 15)	/* Read Completion Status */
 55#define GSR_BIT3SLT12	(1 << 14)	/* Bit 3 of slot 12 */
 56#define GSR_BIT2SLT12	(1 << 13)	/* Bit 2 of slot 12 */
 57#define GSR_BIT1SLT12	(1 << 12)	/* Bit 1 of slot 12 */
 58#define GSR_SECRES	(1 << 11)	/* Secondary Resume Interrupt */
 59#define GSR_PRIRES	(1 << 10)	/* Primary Resume Interrupt */
 60#define GSR_SCR		(1 << 9)	/* Secondary Codec Ready */
 61#define GSR_PCR		(1 << 8)	/*  Primary Codec Ready */
 62#define GSR_MCINT	(1 << 7)	/* Mic In Interrupt */
 63#define GSR_POINT	(1 << 6)	/* PCM Out Interrupt */
 64#define GSR_PIINT	(1 << 5)	/* PCM In Interrupt */
 65#define GSR_ACOFFD	(1 << 3)	/* AC-link Shut Off Done */
 66#define GSR_MOINT	(1 << 2)	/* Modem Out Interrupt */
 67#define GSR_MIINT	(1 << 1)	/* Modem In Interrupt */
 68#define GSR_GSCI	(1 << 0)	/* Codec GPI Status Change Interrupt */
 69
 70#define CAR		(0x0020)  	/* CODEC Access Register */
 71#define CAR_CAIP	(1 << 0)	/* Codec Access In Progress */
 72
 73#define PCDR		(0x0040)  	/* PCM FIFO Data Register */
 74#define MCDR		(0x0060)  	/* Mic-in FIFO Data Register */
 75
 76#define MOCR		(0x0100)  	/* Modem Out Control Register */
 77#define MOCR_FEIE	(1 << 3)	/* FIFO Error */
 78#define MOCR_FSRIE	(1 << 1)	/* FIFO Service Request Interrupt Enable */
 79
 80#define MICR		(0x0108)  	/* Modem In Control Register */
 81#define MICR_FEIE	(1 << 3)	/* FIFO Error */
 82#define MICR_FSRIE	(1 << 1)	/* FIFO Service Request Interrupt Enable */
 83
 84#define MOSR		(0x0110)  	/* Modem Out Status Register */
 85#define MOSR_FIFOE	(1 << 4)	/* FIFO error */
 86#define MOSR_FSR	(1 << 2)	/* FIFO Service Request */
 87
 88#define MISR		(0x0118)  	/* Modem In Status Register */
 89#define MISR_FIFOE	(1 << 4)	/* FIFO error */
 90#define MISR_EOC	(1 << 3)	/* DMA End-of-Chain (exclusive clear) */
 91#define MISR_FSR	(1 << 2)	/* FIFO Service Request */
 92
 93#define MODR		(0x0140)  	/* Modem FIFO Data Register */
 94
 95#define PAC_REG_BASE	(0x0200)  	/* Primary Audio Codec */
 96#define SAC_REG_BASE	(0x0300)  	/* Secondary Audio Codec */
 97#define PMC_REG_BASE	(0x0400)  	/* Primary Modem Codec */
 98#define SMC_REG_BASE	(0x0500)  	/* Secondary Modem Codec */
 99
100#endif /* __ASM_ARCH_REGS_AC97_H */