Loading...
1/*
2 * arch/arm/include/asm/assembler.h
3 *
4 * Copyright (C) 1996-2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This file contains arm architecture specific defines
11 * for the different processors.
12 *
13 * Do not include any C declarations in this file - it is included by
14 * assembler source.
15 */
16#ifndef __ASM_ASSEMBLER_H__
17#define __ASM_ASSEMBLER_H__
18
19#ifndef __ASSEMBLY__
20#error "Only include this from assembly code"
21#endif
22
23#include <asm/ptrace.h>
24#include <asm/domain.h>
25#include <asm/opcodes-virt.h>
26#include <asm/asm-offsets.h>
27#include <asm/page.h>
28#include <asm/thread_info.h>
29
30#define IOMEM(x) (x)
31
32/*
33 * Endian independent macros for shifting bytes within registers.
34 */
35#ifndef __ARMEB__
36#define lspull lsr
37#define lspush lsl
38#define get_byte_0 lsl #0
39#define get_byte_1 lsr #8
40#define get_byte_2 lsr #16
41#define get_byte_3 lsr #24
42#define put_byte_0 lsl #0
43#define put_byte_1 lsl #8
44#define put_byte_2 lsl #16
45#define put_byte_3 lsl #24
46#else
47#define lspull lsl
48#define lspush lsr
49#define get_byte_0 lsr #24
50#define get_byte_1 lsr #16
51#define get_byte_2 lsr #8
52#define get_byte_3 lsl #0
53#define put_byte_0 lsl #24
54#define put_byte_1 lsl #16
55#define put_byte_2 lsl #8
56#define put_byte_3 lsl #0
57#endif
58
59/* Select code for any configuration running in BE8 mode */
60#ifdef CONFIG_CPU_ENDIAN_BE8
61#define ARM_BE8(code...) code
62#else
63#define ARM_BE8(code...)
64#endif
65
66/*
67 * Data preload for architectures that support it
68 */
69#if __LINUX_ARM_ARCH__ >= 5
70#define PLD(code...) code
71#else
72#define PLD(code...)
73#endif
74
75/*
76 * This can be used to enable code to cacheline align the destination
77 * pointer when bulk writing to memory. Experiments on StrongARM and
78 * XScale didn't show this a worthwhile thing to do when the cache is not
79 * set to write-allocate (this would need further testing on XScale when WA
80 * is used).
81 *
82 * On Feroceon there is much to gain however, regardless of cache mode.
83 */
84#ifdef CONFIG_CPU_FEROCEON
85#define CALGN(code...) code
86#else
87#define CALGN(code...)
88#endif
89
90/*
91 * Enable and disable interrupts
92 */
93#if __LINUX_ARM_ARCH__ >= 6
94 .macro disable_irq_notrace
95 cpsid i
96 .endm
97
98 .macro enable_irq_notrace
99 cpsie i
100 .endm
101#else
102 .macro disable_irq_notrace
103 msr cpsr_c, #PSR_I_BIT | SVC_MODE
104 .endm
105
106 .macro enable_irq_notrace
107 msr cpsr_c, #SVC_MODE
108 .endm
109#endif
110
111 .macro asm_trace_hardirqs_off, save=1
112#if defined(CONFIG_TRACE_IRQFLAGS)
113 .if \save
114 stmdb sp!, {r0-r3, ip, lr}
115 .endif
116 bl trace_hardirqs_off
117 .if \save
118 ldmia sp!, {r0-r3, ip, lr}
119 .endif
120#endif
121 .endm
122
123 .macro asm_trace_hardirqs_on, cond=al, save=1
124#if defined(CONFIG_TRACE_IRQFLAGS)
125 /*
126 * actually the registers should be pushed and pop'd conditionally, but
127 * after bl the flags are certainly clobbered
128 */
129 .if \save
130 stmdb sp!, {r0-r3, ip, lr}
131 .endif
132 bl\cond trace_hardirqs_on
133 .if \save
134 ldmia sp!, {r0-r3, ip, lr}
135 .endif
136#endif
137 .endm
138
139 .macro disable_irq, save=1
140 disable_irq_notrace
141 asm_trace_hardirqs_off \save
142 .endm
143
144 .macro enable_irq
145 asm_trace_hardirqs_on
146 enable_irq_notrace
147 .endm
148/*
149 * Save the current IRQ state and disable IRQs. Note that this macro
150 * assumes FIQs are enabled, and that the processor is in SVC mode.
151 */
152 .macro save_and_disable_irqs, oldcpsr
153#ifdef CONFIG_CPU_V7M
154 mrs \oldcpsr, primask
155#else
156 mrs \oldcpsr, cpsr
157#endif
158 disable_irq
159 .endm
160
161 .macro save_and_disable_irqs_notrace, oldcpsr
162#ifdef CONFIG_CPU_V7M
163 mrs \oldcpsr, primask
164#else
165 mrs \oldcpsr, cpsr
166#endif
167 disable_irq_notrace
168 .endm
169
170/*
171 * Restore interrupt state previously stored in a register. We don't
172 * guarantee that this will preserve the flags.
173 */
174 .macro restore_irqs_notrace, oldcpsr
175#ifdef CONFIG_CPU_V7M
176 msr primask, \oldcpsr
177#else
178 msr cpsr_c, \oldcpsr
179#endif
180 .endm
181
182 .macro restore_irqs, oldcpsr
183 tst \oldcpsr, #PSR_I_BIT
184 asm_trace_hardirqs_on cond=eq
185 restore_irqs_notrace \oldcpsr
186 .endm
187
188/*
189 * Assembly version of "adr rd, BSYM(sym)". This should only be used to
190 * reference local symbols in the same assembly file which are to be
191 * resolved by the assembler. Other usage is undefined.
192 */
193 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
194 .macro badr\c, rd, sym
195#ifdef CONFIG_THUMB2_KERNEL
196 adr\c \rd, \sym + 1
197#else
198 adr\c \rd, \sym
199#endif
200 .endm
201 .endr
202
203/*
204 * Get current thread_info.
205 */
206 .macro get_thread_info, rd
207 ARM( mov \rd, sp, lsr #THREAD_SIZE_ORDER + PAGE_SHIFT )
208 THUMB( mov \rd, sp )
209 THUMB( lsr \rd, \rd, #THREAD_SIZE_ORDER + PAGE_SHIFT )
210 mov \rd, \rd, lsl #THREAD_SIZE_ORDER + PAGE_SHIFT
211 .endm
212
213/*
214 * Increment/decrement the preempt count.
215 */
216#ifdef CONFIG_PREEMPT_COUNT
217 .macro inc_preempt_count, ti, tmp
218 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
219 add \tmp, \tmp, #1 @ increment it
220 str \tmp, [\ti, #TI_PREEMPT]
221 .endm
222
223 .macro dec_preempt_count, ti, tmp
224 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
225 sub \tmp, \tmp, #1 @ decrement it
226 str \tmp, [\ti, #TI_PREEMPT]
227 .endm
228
229 .macro dec_preempt_count_ti, ti, tmp
230 get_thread_info \ti
231 dec_preempt_count \ti, \tmp
232 .endm
233#else
234 .macro inc_preempt_count, ti, tmp
235 .endm
236
237 .macro dec_preempt_count, ti, tmp
238 .endm
239
240 .macro dec_preempt_count_ti, ti, tmp
241 .endm
242#endif
243
244#define USER(x...) \
2459999: x; \
246 .pushsection __ex_table,"a"; \
247 .align 3; \
248 .long 9999b,9001f; \
249 .popsection
250
251#ifdef CONFIG_SMP
252#define ALT_SMP(instr...) \
2539998: instr
254/*
255 * Note: if you get assembler errors from ALT_UP() when building with
256 * CONFIG_THUMB2_KERNEL, you almost certainly need to use
257 * ALT_SMP( W(instr) ... )
258 */
259#define ALT_UP(instr...) \
260 .pushsection ".alt.smp.init", "a" ;\
261 .long 9998b ;\
2629997: instr ;\
263 .if . - 9997b == 2 ;\
264 nop ;\
265 .endif ;\
266 .if . - 9997b != 4 ;\
267 .error "ALT_UP() content must assemble to exactly 4 bytes";\
268 .endif ;\
269 .popsection
270#define ALT_UP_B(label) \
271 .equ up_b_offset, label - 9998b ;\
272 .pushsection ".alt.smp.init", "a" ;\
273 .long 9998b ;\
274 W(b) . + up_b_offset ;\
275 .popsection
276#else
277#define ALT_SMP(instr...)
278#define ALT_UP(instr...) instr
279#define ALT_UP_B(label) b label
280#endif
281
282/*
283 * Instruction barrier
284 */
285 .macro instr_sync
286#if __LINUX_ARM_ARCH__ >= 7
287 isb
288#elif __LINUX_ARM_ARCH__ == 6
289 mcr p15, 0, r0, c7, c5, 4
290#endif
291 .endm
292
293/*
294 * SMP data memory barrier
295 */
296 .macro smp_dmb mode
297#ifdef CONFIG_SMP
298#if __LINUX_ARM_ARCH__ >= 7
299 .ifeqs "\mode","arm"
300 ALT_SMP(dmb ish)
301 .else
302 ALT_SMP(W(dmb) ish)
303 .endif
304#elif __LINUX_ARM_ARCH__ == 6
305 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
306#else
307#error Incompatible SMP platform
308#endif
309 .ifeqs "\mode","arm"
310 ALT_UP(nop)
311 .else
312 ALT_UP(W(nop))
313 .endif
314#endif
315 .endm
316
317#if defined(CONFIG_CPU_V7M)
318 /*
319 * setmode is used to assert to be in svc mode during boot. For v7-M
320 * this is done in __v7m_setup, so setmode can be empty here.
321 */
322 .macro setmode, mode, reg
323 .endm
324#elif defined(CONFIG_THUMB2_KERNEL)
325 .macro setmode, mode, reg
326 mov \reg, #\mode
327 msr cpsr_c, \reg
328 .endm
329#else
330 .macro setmode, mode, reg
331 msr cpsr_c, #\mode
332 .endm
333#endif
334
335/*
336 * Helper macro to enter SVC mode cleanly and mask interrupts. reg is
337 * a scratch register for the macro to overwrite.
338 *
339 * This macro is intended for forcing the CPU into SVC mode at boot time.
340 * you cannot return to the original mode.
341 */
342.macro safe_svcmode_maskall reg:req
343#if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M)
344 mrs \reg , cpsr
345 eor \reg, \reg, #HYP_MODE
346 tst \reg, #MODE_MASK
347 bic \reg , \reg , #MODE_MASK
348 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
349THUMB( orr \reg , \reg , #PSR_T_BIT )
350 bne 1f
351 orr \reg, \reg, #PSR_A_BIT
352 badr lr, 2f
353 msr spsr_cxsf, \reg
354 __MSR_ELR_HYP(14)
355 __ERET
3561: msr cpsr_c, \reg
3572:
358#else
359/*
360 * workaround for possibly broken pre-v6 hardware
361 * (akita, Sharp Zaurus C-1000, PXA270-based)
362 */
363 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
364#endif
365.endm
366
367/*
368 * STRT/LDRT access macros with ARM and Thumb-2 variants
369 */
370#ifdef CONFIG_THUMB2_KERNEL
371
372 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
3739999:
374 .if \inc == 1
375 \instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
376 .elseif \inc == 4
377 \instr\cond\()\t\().w \reg, [\ptr, #\off]
378 .else
379 .error "Unsupported inc macro argument"
380 .endif
381
382 .pushsection __ex_table,"a"
383 .align 3
384 .long 9999b, \abort
385 .popsection
386 .endm
387
388 .macro usracc, instr, reg, ptr, inc, cond, rept, abort
389 @ explicit IT instruction needed because of the label
390 @ introduced by the USER macro
391 .ifnc \cond,al
392 .if \rept == 1
393 itt \cond
394 .elseif \rept == 2
395 ittt \cond
396 .else
397 .error "Unsupported rept macro argument"
398 .endif
399 .endif
400
401 @ Slightly optimised to avoid incrementing the pointer twice
402 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
403 .if \rept == 2
404 usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
405 .endif
406
407 add\cond \ptr, #\rept * \inc
408 .endm
409
410#else /* !CONFIG_THUMB2_KERNEL */
411
412 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
413 .rept \rept
4149999:
415 .if \inc == 1
416 \instr\cond\()b\()\t \reg, [\ptr], #\inc
417 .elseif \inc == 4
418 \instr\cond\()\t \reg, [\ptr], #\inc
419 .else
420 .error "Unsupported inc macro argument"
421 .endif
422
423 .pushsection __ex_table,"a"
424 .align 3
425 .long 9999b, \abort
426 .popsection
427 .endr
428 .endm
429
430#endif /* CONFIG_THUMB2_KERNEL */
431
432 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
433 usracc str, \reg, \ptr, \inc, \cond, \rept, \abort
434 .endm
435
436 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
437 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
438 .endm
439
440/* Utility macro for declaring string literals */
441 .macro string name:req, string
442 .type \name , #object
443\name:
444 .asciz "\string"
445 .size \name , . - \name
446 .endm
447
448 .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req
449#ifndef CONFIG_CPU_USE_DOMAINS
450 adds \tmp, \addr, #\size - 1
451 sbcccs \tmp, \tmp, \limit
452 bcs \bad
453#endif
454 .endm
455
456 .macro uaccess_disable, tmp, isb=1
457#ifdef CONFIG_CPU_SW_DOMAIN_PAN
458 /*
459 * Whenever we re-enter userspace, the domains should always be
460 * set appropriately.
461 */
462 mov \tmp, #DACR_UACCESS_DISABLE
463 mcr p15, 0, \tmp, c3, c0, 0 @ Set domain register
464 .if \isb
465 instr_sync
466 .endif
467#endif
468 .endm
469
470 .macro uaccess_enable, tmp, isb=1
471#ifdef CONFIG_CPU_SW_DOMAIN_PAN
472 /*
473 * Whenever we re-enter userspace, the domains should always be
474 * set appropriately.
475 */
476 mov \tmp, #DACR_UACCESS_ENABLE
477 mcr p15, 0, \tmp, c3, c0, 0
478 .if \isb
479 instr_sync
480 .endif
481#endif
482 .endm
483
484 .macro uaccess_save, tmp
485#ifdef CONFIG_CPU_SW_DOMAIN_PAN
486 mrc p15, 0, \tmp, c3, c0, 0
487 str \tmp, [sp, #SVC_DACR]
488#endif
489 .endm
490
491 .macro uaccess_restore
492#ifdef CONFIG_CPU_SW_DOMAIN_PAN
493 ldr r0, [sp, #SVC_DACR]
494 mcr p15, 0, r0, c3, c0, 0
495#endif
496 .endm
497
498 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
499 .macro ret\c, reg
500#if __LINUX_ARM_ARCH__ < 6
501 mov\c pc, \reg
502#else
503 .ifeqs "\reg", "lr"
504 bx\c \reg
505 .else
506 mov\c pc, \reg
507 .endif
508#endif
509 .endm
510 .endr
511
512 .macro ret.w, reg
513 ret \reg
514#ifdef CONFIG_THUMB2_KERNEL
515 nop
516#endif
517 .endm
518
519#endif /* __ASM_ASSEMBLER_H__ */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * arch/arm/include/asm/assembler.h
4 *
5 * Copyright (C) 1996-2000 Russell King
6 *
7 * This file contains arm architecture specific defines
8 * for the different processors.
9 *
10 * Do not include any C declarations in this file - it is included by
11 * assembler source.
12 */
13#ifndef __ASM_ASSEMBLER_H__
14#define __ASM_ASSEMBLER_H__
15
16#ifndef __ASSEMBLY__
17#error "Only include this from assembly code"
18#endif
19
20#include <asm/ptrace.h>
21#include <asm/opcodes-virt.h>
22#include <asm/asm-offsets.h>
23#include <asm/page.h>
24#include <asm/thread_info.h>
25#include <asm/uaccess-asm.h>
26
27#define IOMEM(x) (x)
28
29/*
30 * Endian independent macros for shifting bytes within registers.
31 */
32#ifndef __ARMEB__
33#define lspull lsr
34#define lspush lsl
35#define get_byte_0 lsl #0
36#define get_byte_1 lsr #8
37#define get_byte_2 lsr #16
38#define get_byte_3 lsr #24
39#define put_byte_0 lsl #0
40#define put_byte_1 lsl #8
41#define put_byte_2 lsl #16
42#define put_byte_3 lsl #24
43#else
44#define lspull lsl
45#define lspush lsr
46#define get_byte_0 lsr #24
47#define get_byte_1 lsr #16
48#define get_byte_2 lsr #8
49#define get_byte_3 lsl #0
50#define put_byte_0 lsl #24
51#define put_byte_1 lsl #16
52#define put_byte_2 lsl #8
53#define put_byte_3 lsl #0
54#endif
55
56/* Select code for any configuration running in BE8 mode */
57#ifdef CONFIG_CPU_ENDIAN_BE8
58#define ARM_BE8(code...) code
59#else
60#define ARM_BE8(code...)
61#endif
62
63/*
64 * Data preload for architectures that support it
65 */
66#if __LINUX_ARM_ARCH__ >= 5
67#define PLD(code...) code
68#else
69#define PLD(code...)
70#endif
71
72/*
73 * This can be used to enable code to cacheline align the destination
74 * pointer when bulk writing to memory. Experiments on StrongARM and
75 * XScale didn't show this a worthwhile thing to do when the cache is not
76 * set to write-allocate (this would need further testing on XScale when WA
77 * is used).
78 *
79 * On Feroceon there is much to gain however, regardless of cache mode.
80 */
81#ifdef CONFIG_CPU_FEROCEON
82#define CALGN(code...) code
83#else
84#define CALGN(code...)
85#endif
86
87#define IMM12_MASK 0xfff
88
89/* the frame pointer used for stack unwinding */
90ARM( fpreg .req r11 )
91THUMB( fpreg .req r7 )
92
93/*
94 * Enable and disable interrupts
95 */
96#if __LINUX_ARM_ARCH__ >= 6
97 .macro disable_irq_notrace
98 cpsid i
99 .endm
100
101 .macro enable_irq_notrace
102 cpsie i
103 .endm
104#else
105 .macro disable_irq_notrace
106 msr cpsr_c, #PSR_I_BIT | SVC_MODE
107 .endm
108
109 .macro enable_irq_notrace
110 msr cpsr_c, #SVC_MODE
111 .endm
112#endif
113
114#if __LINUX_ARM_ARCH__ < 7
115 .macro dsb, args
116 mcr p15, 0, r0, c7, c10, 4
117 .endm
118
119 .macro isb, args
120 mcr p15, 0, r0, c7, c5, 4
121 .endm
122#endif
123
124 .macro asm_trace_hardirqs_off, save=1
125#if defined(CONFIG_TRACE_IRQFLAGS)
126 .if \save
127 stmdb sp!, {r0-r3, ip, lr}
128 .endif
129 bl trace_hardirqs_off
130 .if \save
131 ldmia sp!, {r0-r3, ip, lr}
132 .endif
133#endif
134 .endm
135
136 .macro asm_trace_hardirqs_on, cond=al, save=1
137#if defined(CONFIG_TRACE_IRQFLAGS)
138 /*
139 * actually the registers should be pushed and pop'd conditionally, but
140 * after bl the flags are certainly clobbered
141 */
142 .if \save
143 stmdb sp!, {r0-r3, ip, lr}
144 .endif
145 bl\cond trace_hardirqs_on
146 .if \save
147 ldmia sp!, {r0-r3, ip, lr}
148 .endif
149#endif
150 .endm
151
152 .macro disable_irq, save=1
153 disable_irq_notrace
154 asm_trace_hardirqs_off \save
155 .endm
156
157 .macro enable_irq
158 asm_trace_hardirqs_on
159 enable_irq_notrace
160 .endm
161/*
162 * Save the current IRQ state and disable IRQs. Note that this macro
163 * assumes FIQs are enabled, and that the processor is in SVC mode.
164 */
165 .macro save_and_disable_irqs, oldcpsr
166#ifdef CONFIG_CPU_V7M
167 mrs \oldcpsr, primask
168#else
169 mrs \oldcpsr, cpsr
170#endif
171 disable_irq
172 .endm
173
174 .macro save_and_disable_irqs_notrace, oldcpsr
175#ifdef CONFIG_CPU_V7M
176 mrs \oldcpsr, primask
177#else
178 mrs \oldcpsr, cpsr
179#endif
180 disable_irq_notrace
181 .endm
182
183/*
184 * Restore interrupt state previously stored in a register. We don't
185 * guarantee that this will preserve the flags.
186 */
187 .macro restore_irqs_notrace, oldcpsr
188#ifdef CONFIG_CPU_V7M
189 msr primask, \oldcpsr
190#else
191 msr cpsr_c, \oldcpsr
192#endif
193 .endm
194
195 .macro restore_irqs, oldcpsr
196 tst \oldcpsr, #PSR_I_BIT
197 asm_trace_hardirqs_on cond=eq
198 restore_irqs_notrace \oldcpsr
199 .endm
200
201/*
202 * Assembly version of "adr rd, BSYM(sym)". This should only be used to
203 * reference local symbols in the same assembly file which are to be
204 * resolved by the assembler. Other usage is undefined.
205 */
206 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
207 .macro badr\c, rd, sym
208#ifdef CONFIG_THUMB2_KERNEL
209 adr\c \rd, \sym + 1
210#else
211 adr\c \rd, \sym
212#endif
213 .endm
214 .endr
215
216/*
217 * Get current thread_info.
218 */
219 .macro get_thread_info, rd
220 /* thread_info is the first member of struct task_struct */
221 get_current \rd
222 .endm
223
224/*
225 * Increment/decrement the preempt count.
226 */
227#ifdef CONFIG_PREEMPT_COUNT
228 .macro inc_preempt_count, ti, tmp
229 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
230 add \tmp, \tmp, #1 @ increment it
231 str \tmp, [\ti, #TI_PREEMPT]
232 .endm
233
234 .macro dec_preempt_count, ti, tmp
235 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
236 sub \tmp, \tmp, #1 @ decrement it
237 str \tmp, [\ti, #TI_PREEMPT]
238 .endm
239#else
240 .macro inc_preempt_count, ti, tmp
241 .endm
242
243 .macro dec_preempt_count, ti, tmp
244 .endm
245#endif
246
247#define USERL(l, x...) \
2489999: x; \
249 .pushsection __ex_table,"a"; \
250 .align 3; \
251 .long 9999b,l; \
252 .popsection
253
254#define USER(x...) USERL(9001f, x)
255
256#ifdef CONFIG_SMP
257#define ALT_SMP(instr...) \
2589998: instr
259/*
260 * Note: if you get assembler errors from ALT_UP() when building with
261 * CONFIG_THUMB2_KERNEL, you almost certainly need to use
262 * ALT_SMP( W(instr) ... )
263 */
264#define ALT_UP(instr...) \
265 .pushsection ".alt.smp.init", "a" ;\
266 .align 2 ;\
267 .long 9998b - . ;\
2689997: instr ;\
269 .if . - 9997b == 2 ;\
270 nop ;\
271 .endif ;\
272 .if . - 9997b != 4 ;\
273 .error "ALT_UP() content must assemble to exactly 4 bytes";\
274 .endif ;\
275 .popsection
276#define ALT_UP_B(label) \
277 .pushsection ".alt.smp.init", "a" ;\
278 .align 2 ;\
279 .long 9998b - . ;\
280 W(b) . + (label - 9998b) ;\
281 .popsection
282#else
283#define ALT_SMP(instr...)
284#define ALT_UP(instr...) instr
285#define ALT_UP_B(label) b label
286#endif
287
288 /*
289 * this_cpu_offset - load the per-CPU offset of this CPU into
290 * register 'rd'
291 */
292 .macro this_cpu_offset, rd:req
293#ifdef CONFIG_SMP
294ALT_SMP(mrc p15, 0, \rd, c13, c0, 4)
295#ifdef CONFIG_CPU_V6
296ALT_UP_B(.L1_\@)
297.L0_\@:
298 .subsection 1
299.L1_\@: ldr_va \rd, __per_cpu_offset
300 b .L0_\@
301 .previous
302#endif
303#else
304 mov \rd, #0
305#endif
306 .endm
307
308 /*
309 * set_current - store the task pointer of this CPU's current task
310 */
311 .macro set_current, rn:req, tmp:req
312#if defined(CONFIG_CURRENT_POINTER_IN_TPIDRURO) || defined(CONFIG_SMP)
3139998: mcr p15, 0, \rn, c13, c0, 3 @ set TPIDRURO register
314#ifdef CONFIG_CPU_V6
315ALT_UP_B(.L0_\@)
316 .subsection 1
317.L0_\@: str_va \rn, __current, \tmp
318 b .L1_\@
319 .previous
320.L1_\@:
321#endif
322#else
323 str_va \rn, __current, \tmp
324#endif
325 .endm
326
327 /*
328 * get_current - load the task pointer of this CPU's current task
329 */
330 .macro get_current, rd:req
331#if defined(CONFIG_CURRENT_POINTER_IN_TPIDRURO) || defined(CONFIG_SMP)
3329998: mrc p15, 0, \rd, c13, c0, 3 @ get TPIDRURO register
333#ifdef CONFIG_CPU_V6
334ALT_UP_B(.L0_\@)
335 .subsection 1
336.L0_\@: ldr_va \rd, __current
337 b .L1_\@
338 .previous
339.L1_\@:
340#endif
341#else
342 ldr_va \rd, __current
343#endif
344 .endm
345
346 /*
347 * reload_current - reload the task pointer of this CPU's current task
348 * into the TLS register
349 */
350 .macro reload_current, t1:req, t2:req
351#if defined(CONFIG_CURRENT_POINTER_IN_TPIDRURO) || defined(CONFIG_SMP)
352#ifdef CONFIG_CPU_V6
353ALT_SMP(nop)
354ALT_UP_B(.L0_\@)
355#endif
356 ldr_this_cpu \t1, __entry_task, \t1, \t2
357 mcr p15, 0, \t1, c13, c0, 3 @ store in TPIDRURO
358.L0_\@:
359#endif
360 .endm
361
362/*
363 * Instruction barrier
364 */
365 .macro instr_sync
366#if __LINUX_ARM_ARCH__ >= 7
367 isb
368#elif __LINUX_ARM_ARCH__ == 6
369 mcr p15, 0, r0, c7, c5, 4
370#endif
371 .endm
372
373/*
374 * SMP data memory barrier
375 */
376 .macro smp_dmb mode
377#ifdef CONFIG_SMP
378#if __LINUX_ARM_ARCH__ >= 7
379 .ifeqs "\mode","arm"
380 ALT_SMP(dmb ish)
381 .else
382 ALT_SMP(W(dmb) ish)
383 .endif
384#elif __LINUX_ARM_ARCH__ == 6
385 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
386#else
387#error Incompatible SMP platform
388#endif
389 .ifeqs "\mode","arm"
390 ALT_UP(nop)
391 .else
392 ALT_UP(W(nop))
393 .endif
394#endif
395 .endm
396
397/*
398 * Raw SMP data memory barrier
399 */
400 .macro __smp_dmb mode
401#if __LINUX_ARM_ARCH__ >= 7
402 .ifeqs "\mode","arm"
403 dmb ish
404 .else
405 W(dmb) ish
406 .endif
407#elif __LINUX_ARM_ARCH__ == 6
408 mcr p15, 0, r0, c7, c10, 5 @ dmb
409#else
410 .error "Incompatible SMP platform"
411#endif
412 .endm
413
414#if defined(CONFIG_CPU_V7M)
415 /*
416 * setmode is used to assert to be in svc mode during boot. For v7-M
417 * this is done in __v7m_setup, so setmode can be empty here.
418 */
419 .macro setmode, mode, reg
420 .endm
421#elif defined(CONFIG_THUMB2_KERNEL)
422 .macro setmode, mode, reg
423 mov \reg, #\mode
424 msr cpsr_c, \reg
425 .endm
426#else
427 .macro setmode, mode, reg
428 msr cpsr_c, #\mode
429 .endm
430#endif
431
432/*
433 * Helper macro to enter SVC mode cleanly and mask interrupts. reg is
434 * a scratch register for the macro to overwrite.
435 *
436 * This macro is intended for forcing the CPU into SVC mode at boot time.
437 * you cannot return to the original mode.
438 */
439.macro safe_svcmode_maskall reg:req
440#if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M)
441 mrs \reg , cpsr
442 eor \reg, \reg, #HYP_MODE
443 tst \reg, #MODE_MASK
444 bic \reg , \reg , #MODE_MASK
445 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
446THUMB( orr \reg , \reg , #PSR_T_BIT )
447 bne 1f
448 orr \reg, \reg, #PSR_A_BIT
449 badr lr, 2f
450 msr spsr_cxsf, \reg
451 __MSR_ELR_HYP(14)
452 __ERET
4531: msr cpsr_c, \reg
4542:
455#else
456/*
457 * workaround for possibly broken pre-v6 hardware
458 * (akita, Sharp Zaurus C-1000, PXA270-based)
459 */
460 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
461#endif
462.endm
463
464/*
465 * STRT/LDRT access macros with ARM and Thumb-2 variants
466 */
467#ifdef CONFIG_THUMB2_KERNEL
468
469 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
4709999:
471 .if \inc == 1
472 \instr\()b\t\cond\().w \reg, [\ptr, #\off]
473 .elseif \inc == 4
474 \instr\t\cond\().w \reg, [\ptr, #\off]
475 .else
476 .error "Unsupported inc macro argument"
477 .endif
478
479 .pushsection __ex_table,"a"
480 .align 3
481 .long 9999b, \abort
482 .popsection
483 .endm
484
485 .macro usracc, instr, reg, ptr, inc, cond, rept, abort
486 @ explicit IT instruction needed because of the label
487 @ introduced by the USER macro
488 .ifnc \cond,al
489 .if \rept == 1
490 itt \cond
491 .elseif \rept == 2
492 ittt \cond
493 .else
494 .error "Unsupported rept macro argument"
495 .endif
496 .endif
497
498 @ Slightly optimised to avoid incrementing the pointer twice
499 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
500 .if \rept == 2
501 usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
502 .endif
503
504 add\cond \ptr, #\rept * \inc
505 .endm
506
507#else /* !CONFIG_THUMB2_KERNEL */
508
509 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
510 .rept \rept
5119999:
512 .if \inc == 1
513 \instr\()b\t\cond \reg, [\ptr], #\inc
514 .elseif \inc == 4
515 \instr\t\cond \reg, [\ptr], #\inc
516 .else
517 .error "Unsupported inc macro argument"
518 .endif
519
520 .pushsection __ex_table,"a"
521 .align 3
522 .long 9999b, \abort
523 .popsection
524 .endr
525 .endm
526
527#endif /* CONFIG_THUMB2_KERNEL */
528
529 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
530 usracc str, \reg, \ptr, \inc, \cond, \rept, \abort
531 .endm
532
533 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
534 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
535 .endm
536
537/* Utility macro for declaring string literals */
538 .macro string name:req, string
539 .type \name , #object
540\name:
541 .asciz "\string"
542 .size \name , . - \name
543 .endm
544
545 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
546 .macro ret\c, reg
547#if __LINUX_ARM_ARCH__ < 6
548 mov\c pc, \reg
549#else
550 .ifeqs "\reg", "lr"
551 bx\c \reg
552 .else
553 mov\c pc, \reg
554 .endif
555#endif
556 .endm
557 .endr
558
559 .macro ret.w, reg
560 ret \reg
561#ifdef CONFIG_THUMB2_KERNEL
562 nop
563#endif
564 .endm
565
566 .macro bug, msg, line
567#ifdef CONFIG_THUMB2_KERNEL
5681: .inst 0xde02
569#else
5701: .inst 0xe7f001f2
571#endif
572#ifdef CONFIG_DEBUG_BUGVERBOSE
573 .pushsection .rodata.str, "aMS", %progbits, 1
5742: .asciz "\msg"
575 .popsection
576 .pushsection __bug_table, "aw"
577 .align 2
578 .word 1b, 2b
579 .hword \line
580 .popsection
581#endif
582 .endm
583
584#ifdef CONFIG_KPROBES
585#define _ASM_NOKPROBE(entry) \
586 .pushsection "_kprobe_blacklist", "aw" ; \
587 .balign 4 ; \
588 .long entry; \
589 .popsection
590#else
591#define _ASM_NOKPROBE(entry)
592#endif
593
594 .macro __adldst_l, op, reg, sym, tmp, c
595 .if __LINUX_ARM_ARCH__ < 7
596 ldr\c \tmp, .La\@
597 .subsection 1
598 .align 2
599.La\@: .long \sym - .Lpc\@
600 .previous
601 .else
602 .ifnb \c
603 THUMB( ittt \c )
604 .endif
605 movw\c \tmp, #:lower16:\sym - .Lpc\@
606 movt\c \tmp, #:upper16:\sym - .Lpc\@
607 .endif
608
609#ifndef CONFIG_THUMB2_KERNEL
610 .set .Lpc\@, . + 8 // PC bias
611 .ifc \op, add
612 add\c \reg, \tmp, pc
613 .else
614 \op\c \reg, [pc, \tmp]
615 .endif
616#else
617.Lb\@: add\c \tmp, \tmp, pc
618 /*
619 * In Thumb-2 builds, the PC bias depends on whether we are currently
620 * emitting into a .arm or a .thumb section. The size of the add opcode
621 * above will be 2 bytes when emitting in Thumb mode and 4 bytes when
622 * emitting in ARM mode, so let's use this to account for the bias.
623 */
624 .set .Lpc\@, . + (. - .Lb\@)
625
626 .ifnc \op, add
627 \op\c \reg, [\tmp]
628 .endif
629#endif
630 .endm
631
632 /*
633 * mov_l - move a constant value or [relocated] address into a register
634 */
635 .macro mov_l, dst:req, imm:req, cond
636 .if __LINUX_ARM_ARCH__ < 7
637 ldr\cond \dst, =\imm
638 .else
639 movw\cond \dst, #:lower16:\imm
640 movt\cond \dst, #:upper16:\imm
641 .endif
642 .endm
643
644 /*
645 * adr_l - adr pseudo-op with unlimited range
646 *
647 * @dst: destination register
648 * @sym: name of the symbol
649 * @cond: conditional opcode suffix
650 */
651 .macro adr_l, dst:req, sym:req, cond
652 __adldst_l add, \dst, \sym, \dst, \cond
653 .endm
654
655 /*
656 * ldr_l - ldr <literal> pseudo-op with unlimited range
657 *
658 * @dst: destination register
659 * @sym: name of the symbol
660 * @cond: conditional opcode suffix
661 */
662 .macro ldr_l, dst:req, sym:req, cond
663 __adldst_l ldr, \dst, \sym, \dst, \cond
664 .endm
665
666 /*
667 * str_l - str <literal> pseudo-op with unlimited range
668 *
669 * @src: source register
670 * @sym: name of the symbol
671 * @tmp: mandatory scratch register
672 * @cond: conditional opcode suffix
673 */
674 .macro str_l, src:req, sym:req, tmp:req, cond
675 __adldst_l str, \src, \sym, \tmp, \cond
676 .endm
677
678 .macro __ldst_va, op, reg, tmp, sym, cond, offset
679#if __LINUX_ARM_ARCH__ >= 7 || \
680 !defined(CONFIG_ARM_HAS_GROUP_RELOCS) || \
681 (defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS))
682 mov_l \tmp, \sym, \cond
683#else
684 /*
685 * Avoid a literal load, by emitting a sequence of ADD/LDR instructions
686 * with the appropriate relocations. The combined sequence has a range
687 * of -/+ 256 MiB, which should be sufficient for the core kernel and
688 * for modules loaded into the module region.
689 */
690 .globl \sym
691 .reloc .L0_\@, R_ARM_ALU_PC_G0_NC, \sym
692 .reloc .L1_\@, R_ARM_ALU_PC_G1_NC, \sym
693 .reloc .L2_\@, R_ARM_LDR_PC_G2, \sym
694.L0_\@: sub\cond \tmp, pc, #8 - \offset
695.L1_\@: sub\cond \tmp, \tmp, #4 - \offset
696.L2_\@:
697#endif
698 \op\cond \reg, [\tmp, #\offset]
699 .endm
700
701 /*
702 * ldr_va - load a 32-bit word from the virtual address of \sym
703 */
704 .macro ldr_va, rd:req, sym:req, cond, tmp, offset=0
705 .ifnb \tmp
706 __ldst_va ldr, \rd, \tmp, \sym, \cond, \offset
707 .else
708 __ldst_va ldr, \rd, \rd, \sym, \cond, \offset
709 .endif
710 .endm
711
712 /*
713 * str_va - store a 32-bit word to the virtual address of \sym
714 */
715 .macro str_va, rn:req, sym:req, tmp:req, cond
716 __ldst_va str, \rn, \tmp, \sym, \cond, 0
717 .endm
718
719 /*
720 * ldr_this_cpu_armv6 - Load a 32-bit word from the per-CPU variable 'sym',
721 * without using a temp register. Supported in ARM mode
722 * only.
723 */
724 .macro ldr_this_cpu_armv6, rd:req, sym:req
725 this_cpu_offset \rd
726 .globl \sym
727 .reloc .L0_\@, R_ARM_ALU_PC_G0_NC, \sym
728 .reloc .L1_\@, R_ARM_ALU_PC_G1_NC, \sym
729 .reloc .L2_\@, R_ARM_LDR_PC_G2, \sym
730 add \rd, \rd, pc
731.L0_\@: sub \rd, \rd, #4
732.L1_\@: sub \rd, \rd, #0
733.L2_\@: ldr \rd, [\rd, #4]
734 .endm
735
736 /*
737 * ldr_this_cpu - Load a 32-bit word from the per-CPU variable 'sym'
738 * into register 'rd', which may be the stack pointer,
739 * using 't1' and 't2' as general temp registers. These
740 * are permitted to overlap with 'rd' if != sp
741 */
742 .macro ldr_this_cpu, rd:req, sym:req, t1:req, t2:req
743#ifndef CONFIG_SMP
744 ldr_va \rd, \sym, tmp=\t1
745#elif __LINUX_ARM_ARCH__ >= 7 || \
746 !defined(CONFIG_ARM_HAS_GROUP_RELOCS) || \
747 (defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS))
748 this_cpu_offset \t1
749 mov_l \t2, \sym
750 ldr \rd, [\t1, \t2]
751#else
752 ldr_this_cpu_armv6 \rd, \sym
753#endif
754 .endm
755
756 /*
757 * rev_l - byte-swap a 32-bit value
758 *
759 * @val: source/destination register
760 * @tmp: scratch register
761 */
762 .macro rev_l, val:req, tmp:req
763 .if __LINUX_ARM_ARCH__ < 6
764 eor \tmp, \val, \val, ror #16
765 bic \tmp, \tmp, #0x00ff0000
766 mov \val, \val, ror #8
767 eor \val, \val, \tmp, lsr #8
768 .else
769 rev \val, \val
770 .endif
771 .endm
772
773 .if __LINUX_ARM_ARCH__ < 6
774 .set .Lrev_l_uses_tmp, 1
775 .else
776 .set .Lrev_l_uses_tmp, 0
777 .endif
778
779 /*
780 * bl_r - branch and link to register
781 *
782 * @dst: target to branch to
783 * @c: conditional opcode suffix
784 */
785 .macro bl_r, dst:req, c
786 .if __LINUX_ARM_ARCH__ < 6
787 mov\c lr, pc
788 mov\c pc, \dst
789 .else
790 blx\c \dst
791 .endif
792 .endm
793
794#endif /* __ASM_ASSEMBLER_H__ */