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1/*
2 * core.c - DesignWare HS OTG Controller common routines
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37/*
38 * The Core code provides basic services for accessing and managing the
39 * DWC_otg hardware. These services are used by both the Host Controller
40 * Driver and the Peripheral Controller Driver.
41 */
42#include <linux/kernel.h>
43#include <linux/module.h>
44#include <linux/moduleparam.h>
45#include <linux/spinlock.h>
46#include <linux/interrupt.h>
47#include <linux/dma-mapping.h>
48#include <linux/delay.h>
49#include <linux/io.h>
50#include <linux/slab.h>
51#include <linux/usb.h>
52
53#include <linux/usb/hcd.h>
54#include <linux/usb/ch11.h>
55
56#include "core.h"
57#include "hcd.h"
58
59/**
60 * dwc2_backup_global_registers() - Backup global controller registers.
61 * When suspending usb bus, registers needs to be backuped
62 * if controller power is disabled once suspended.
63 *
64 * @hsotg: Programming view of the DWC_otg controller
65 */
66static int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
67{
68 struct dwc2_gregs_backup *gr;
69 int i;
70
71 /* Backup global regs */
72 gr = &hsotg->gr_backup;
73
74 gr->gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
75 gr->gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
76 gr->gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
77 gr->gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
78 gr->grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
79 gr->gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
80 gr->hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
81 gr->gdfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
82 for (i = 0; i < MAX_EPS_CHANNELS; i++)
83 gr->dtxfsiz[i] = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
84
85 gr->valid = true;
86 return 0;
87}
88
89/**
90 * dwc2_restore_global_registers() - Restore controller global registers.
91 * When resuming usb bus, device registers needs to be restored
92 * if controller power were disabled.
93 *
94 * @hsotg: Programming view of the DWC_otg controller
95 */
96static int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
97{
98 struct dwc2_gregs_backup *gr;
99 int i;
100
101 dev_dbg(hsotg->dev, "%s\n", __func__);
102
103 /* Restore global regs */
104 gr = &hsotg->gr_backup;
105 if (!gr->valid) {
106 dev_err(hsotg->dev, "%s: no global registers to restore\n",
107 __func__);
108 return -EINVAL;
109 }
110 gr->valid = false;
111
112 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
113 dwc2_writel(gr->gotgctl, hsotg->regs + GOTGCTL);
114 dwc2_writel(gr->gintmsk, hsotg->regs + GINTMSK);
115 dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG);
116 dwc2_writel(gr->gahbcfg, hsotg->regs + GAHBCFG);
117 dwc2_writel(gr->grxfsiz, hsotg->regs + GRXFSIZ);
118 dwc2_writel(gr->gnptxfsiz, hsotg->regs + GNPTXFSIZ);
119 dwc2_writel(gr->hptxfsiz, hsotg->regs + HPTXFSIZ);
120 dwc2_writel(gr->gdfifocfg, hsotg->regs + GDFIFOCFG);
121 for (i = 0; i < MAX_EPS_CHANNELS; i++)
122 dwc2_writel(gr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i));
123
124 return 0;
125}
126
127/**
128 * dwc2_exit_hibernation() - Exit controller from Partial Power Down.
129 *
130 * @hsotg: Programming view of the DWC_otg controller
131 * @restore: Controller registers need to be restored
132 */
133int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore)
134{
135 u32 pcgcctl;
136 int ret = 0;
137
138 if (!hsotg->params.hibernation)
139 return -ENOTSUPP;
140
141 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
142 pcgcctl &= ~PCGCTL_STOPPCLK;
143 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
144
145 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
146 pcgcctl &= ~PCGCTL_PWRCLMP;
147 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
148
149 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
150 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
151 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
152
153 udelay(100);
154 if (restore) {
155 ret = dwc2_restore_global_registers(hsotg);
156 if (ret) {
157 dev_err(hsotg->dev, "%s: failed to restore registers\n",
158 __func__);
159 return ret;
160 }
161 if (dwc2_is_host_mode(hsotg)) {
162 ret = dwc2_restore_host_registers(hsotg);
163 if (ret) {
164 dev_err(hsotg->dev, "%s: failed to restore host registers\n",
165 __func__);
166 return ret;
167 }
168 } else {
169 ret = dwc2_restore_device_registers(hsotg);
170 if (ret) {
171 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
172 __func__);
173 return ret;
174 }
175 }
176 }
177
178 return ret;
179}
180
181/**
182 * dwc2_enter_hibernation() - Put controller in Partial Power Down.
183 *
184 * @hsotg: Programming view of the DWC_otg controller
185 */
186int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg)
187{
188 u32 pcgcctl;
189 int ret = 0;
190
191 if (!hsotg->params.hibernation)
192 return -ENOTSUPP;
193
194 /* Backup all registers */
195 ret = dwc2_backup_global_registers(hsotg);
196 if (ret) {
197 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
198 __func__);
199 return ret;
200 }
201
202 if (dwc2_is_host_mode(hsotg)) {
203 ret = dwc2_backup_host_registers(hsotg);
204 if (ret) {
205 dev_err(hsotg->dev, "%s: failed to backup host registers\n",
206 __func__);
207 return ret;
208 }
209 } else {
210 ret = dwc2_backup_device_registers(hsotg);
211 if (ret) {
212 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
213 __func__);
214 return ret;
215 }
216 }
217
218 /*
219 * Clear any pending interrupts since dwc2 will not be able to
220 * clear them after entering hibernation.
221 */
222 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
223
224 /* Put the controller in low power state */
225 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
226
227 pcgcctl |= PCGCTL_PWRCLMP;
228 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
229 ndelay(20);
230
231 pcgcctl |= PCGCTL_RSTPDWNMODULE;
232 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
233 ndelay(20);
234
235 pcgcctl |= PCGCTL_STOPPCLK;
236 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
237
238 return ret;
239}
240
241/**
242 * dwc2_wait_for_mode() - Waits for the controller mode.
243 * @hsotg: Programming view of the DWC_otg controller.
244 * @host_mode: If true, waits for host mode, otherwise device mode.
245 */
246static void dwc2_wait_for_mode(struct dwc2_hsotg *hsotg,
247 bool host_mode)
248{
249 ktime_t start;
250 ktime_t end;
251 unsigned int timeout = 110;
252
253 dev_vdbg(hsotg->dev, "Waiting for %s mode\n",
254 host_mode ? "host" : "device");
255
256 start = ktime_get();
257
258 while (1) {
259 s64 ms;
260
261 if (dwc2_is_host_mode(hsotg) == host_mode) {
262 dev_vdbg(hsotg->dev, "%s mode set\n",
263 host_mode ? "Host" : "Device");
264 break;
265 }
266
267 end = ktime_get();
268 ms = ktime_to_ms(ktime_sub(end, start));
269
270 if (ms >= (s64)timeout) {
271 dev_warn(hsotg->dev, "%s: Couldn't set %s mode\n",
272 __func__, host_mode ? "host" : "device");
273 break;
274 }
275
276 usleep_range(1000, 2000);
277 }
278}
279
280/**
281 * dwc2_iddig_filter_enabled() - Returns true if the IDDIG debounce
282 * filter is enabled.
283 */
284static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg)
285{
286 u32 gsnpsid;
287 u32 ghwcfg4;
288
289 if (!dwc2_hw_is_otg(hsotg))
290 return false;
291
292 /* Check if core configuration includes the IDDIG filter. */
293 ghwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4);
294 if (!(ghwcfg4 & GHWCFG4_IDDIG_FILT_EN))
295 return false;
296
297 /*
298 * Check if the IDDIG debounce filter is bypassed. Available
299 * in core version >= 3.10a.
300 */
301 gsnpsid = dwc2_readl(hsotg->regs + GSNPSID);
302 if (gsnpsid >= DWC2_CORE_REV_3_10a) {
303 u32 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
304
305 if (gotgctl & GOTGCTL_DBNCE_FLTR_BYPASS)
306 return false;
307 }
308
309 return true;
310}
311
312/*
313 * Do core a soft reset of the core. Be careful with this because it
314 * resets all the internal state machines of the core.
315 */
316int dwc2_core_reset(struct dwc2_hsotg *hsotg)
317{
318 u32 greset;
319 int count = 0;
320 bool wait_for_host_mode = false;
321
322 dev_vdbg(hsotg->dev, "%s()\n", __func__);
323
324 /*
325 * If the current mode is host, either due to the force mode
326 * bit being set (which persists after core reset) or the
327 * connector id pin, a core soft reset will temporarily reset
328 * the mode to device. A delay from the IDDIG debounce filter
329 * will occur before going back to host mode.
330 *
331 * Determine whether we will go back into host mode after a
332 * reset and account for this delay after the reset.
333 */
334 if (dwc2_iddig_filter_enabled(hsotg)) {
335 u32 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
336 u32 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
337
338 if (!(gotgctl & GOTGCTL_CONID_B) ||
339 (gusbcfg & GUSBCFG_FORCEHOSTMODE)) {
340 wait_for_host_mode = true;
341 }
342 }
343
344 /* Core Soft Reset */
345 greset = dwc2_readl(hsotg->regs + GRSTCTL);
346 greset |= GRSTCTL_CSFTRST;
347 dwc2_writel(greset, hsotg->regs + GRSTCTL);
348 do {
349 udelay(1);
350 greset = dwc2_readl(hsotg->regs + GRSTCTL);
351 if (++count > 50) {
352 dev_warn(hsotg->dev,
353 "%s() HANG! Soft Reset GRSTCTL=%0x\n",
354 __func__, greset);
355 return -EBUSY;
356 }
357 } while (greset & GRSTCTL_CSFTRST);
358
359 /* Wait for AHB master IDLE state */
360 count = 0;
361 do {
362 udelay(1);
363 greset = dwc2_readl(hsotg->regs + GRSTCTL);
364 if (++count > 50) {
365 dev_warn(hsotg->dev,
366 "%s() HANG! AHB Idle GRSTCTL=%0x\n",
367 __func__, greset);
368 return -EBUSY;
369 }
370 } while (!(greset & GRSTCTL_AHBIDLE));
371
372 if (wait_for_host_mode)
373 dwc2_wait_for_mode(hsotg, true);
374
375 return 0;
376}
377
378/*
379 * Force the mode of the controller.
380 *
381 * Forcing the mode is needed for two cases:
382 *
383 * 1) If the dr_mode is set to either HOST or PERIPHERAL we force the
384 * controller to stay in a particular mode regardless of ID pin
385 * changes. We do this usually after a core reset.
386 *
387 * 2) During probe we want to read reset values of the hw
388 * configuration registers that are only available in either host or
389 * device mode. We may need to force the mode if the current mode does
390 * not allow us to access the register in the mode that we want.
391 *
392 * In either case it only makes sense to force the mode if the
393 * controller hardware is OTG capable.
394 *
395 * Checks are done in this function to determine whether doing a force
396 * would be valid or not.
397 *
398 * If a force is done, it requires a IDDIG debounce filter delay if
399 * the filter is configured and enabled. We poll the current mode of
400 * the controller to account for this delay.
401 */
402static bool dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
403{
404 u32 gusbcfg;
405 u32 set;
406 u32 clear;
407
408 dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device");
409
410 /*
411 * Force mode has no effect if the hardware is not OTG.
412 */
413 if (!dwc2_hw_is_otg(hsotg))
414 return false;
415
416 /*
417 * If dr_mode is either peripheral or host only, there is no
418 * need to ever force the mode to the opposite mode.
419 */
420 if (WARN_ON(host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL))
421 return false;
422
423 if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST))
424 return false;
425
426 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
427
428 set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE;
429 clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE;
430
431 gusbcfg &= ~clear;
432 gusbcfg |= set;
433 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
434
435 dwc2_wait_for_mode(hsotg, host);
436 return true;
437}
438
439/**
440 * dwc2_clear_force_mode() - Clears the force mode bits.
441 *
442 * After clearing the bits, wait up to 100 ms to account for any
443 * potential IDDIG filter delay. We can't know if we expect this delay
444 * or not because the value of the connector ID status is affected by
445 * the force mode. We only need to call this once during probe if
446 * dr_mode == OTG.
447 */
448void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg)
449{
450 u32 gusbcfg;
451
452 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
453 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
454 gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
455 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
456
457 if (dwc2_iddig_filter_enabled(hsotg))
458 usleep_range(100000, 110000);
459}
460
461/*
462 * Sets or clears force mode based on the dr_mode parameter.
463 */
464void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
465{
466 bool ret;
467
468 switch (hsotg->dr_mode) {
469 case USB_DR_MODE_HOST:
470 ret = dwc2_force_mode(hsotg, true);
471 /*
472 * NOTE: This is required for some rockchip soc based
473 * platforms on their host-only dwc2.
474 */
475 if (!ret)
476 msleep(50);
477
478 break;
479 case USB_DR_MODE_PERIPHERAL:
480 dwc2_force_mode(hsotg, false);
481 break;
482 case USB_DR_MODE_OTG:
483 dwc2_clear_force_mode(hsotg);
484 break;
485 default:
486 dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n",
487 __func__, hsotg->dr_mode);
488 break;
489 }
490}
491
492/*
493 * Do core a soft reset of the core. Be careful with this because it
494 * resets all the internal state machines of the core.
495 *
496 * Additionally this will apply force mode as per the hsotg->dr_mode
497 * parameter.
498 */
499int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg)
500{
501 int retval;
502
503 retval = dwc2_core_reset(hsotg);
504 if (retval)
505 return retval;
506
507 dwc2_force_dr_mode(hsotg);
508 return 0;
509}
510
511/**
512 * dwc2_dump_host_registers() - Prints the host registers
513 *
514 * @hsotg: Programming view of DWC_otg controller
515 *
516 * NOTE: This function will be removed once the peripheral controller code
517 * is integrated and the driver is stable
518 */
519void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
520{
521#ifdef DEBUG
522 u32 __iomem *addr;
523 int i;
524
525 dev_dbg(hsotg->dev, "Host Global Registers\n");
526 addr = hsotg->regs + HCFG;
527 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n",
528 (unsigned long)addr, dwc2_readl(addr));
529 addr = hsotg->regs + HFIR;
530 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n",
531 (unsigned long)addr, dwc2_readl(addr));
532 addr = hsotg->regs + HFNUM;
533 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n",
534 (unsigned long)addr, dwc2_readl(addr));
535 addr = hsotg->regs + HPTXSTS;
536 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n",
537 (unsigned long)addr, dwc2_readl(addr));
538 addr = hsotg->regs + HAINT;
539 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n",
540 (unsigned long)addr, dwc2_readl(addr));
541 addr = hsotg->regs + HAINTMSK;
542 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n",
543 (unsigned long)addr, dwc2_readl(addr));
544 if (hsotg->params.dma_desc_enable > 0) {
545 addr = hsotg->regs + HFLBADDR;
546 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
547 (unsigned long)addr, dwc2_readl(addr));
548 }
549
550 addr = hsotg->regs + HPRT0;
551 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n",
552 (unsigned long)addr, dwc2_readl(addr));
553
554 for (i = 0; i < hsotg->params.host_channels; i++) {
555 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
556 addr = hsotg->regs + HCCHAR(i);
557 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n",
558 (unsigned long)addr, dwc2_readl(addr));
559 addr = hsotg->regs + HCSPLT(i);
560 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n",
561 (unsigned long)addr, dwc2_readl(addr));
562 addr = hsotg->regs + HCINT(i);
563 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n",
564 (unsigned long)addr, dwc2_readl(addr));
565 addr = hsotg->regs + HCINTMSK(i);
566 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n",
567 (unsigned long)addr, dwc2_readl(addr));
568 addr = hsotg->regs + HCTSIZ(i);
569 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n",
570 (unsigned long)addr, dwc2_readl(addr));
571 addr = hsotg->regs + HCDMA(i);
572 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n",
573 (unsigned long)addr, dwc2_readl(addr));
574 if (hsotg->params.dma_desc_enable > 0) {
575 addr = hsotg->regs + HCDMAB(i);
576 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n",
577 (unsigned long)addr, dwc2_readl(addr));
578 }
579 }
580#endif
581}
582
583/**
584 * dwc2_dump_global_registers() - Prints the core global registers
585 *
586 * @hsotg: Programming view of DWC_otg controller
587 *
588 * NOTE: This function will be removed once the peripheral controller code
589 * is integrated and the driver is stable
590 */
591void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
592{
593#ifdef DEBUG
594 u32 __iomem *addr;
595
596 dev_dbg(hsotg->dev, "Core Global Registers\n");
597 addr = hsotg->regs + GOTGCTL;
598 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n",
599 (unsigned long)addr, dwc2_readl(addr));
600 addr = hsotg->regs + GOTGINT;
601 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n",
602 (unsigned long)addr, dwc2_readl(addr));
603 addr = hsotg->regs + GAHBCFG;
604 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n",
605 (unsigned long)addr, dwc2_readl(addr));
606 addr = hsotg->regs + GUSBCFG;
607 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n",
608 (unsigned long)addr, dwc2_readl(addr));
609 addr = hsotg->regs + GRSTCTL;
610 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n",
611 (unsigned long)addr, dwc2_readl(addr));
612 addr = hsotg->regs + GINTSTS;
613 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n",
614 (unsigned long)addr, dwc2_readl(addr));
615 addr = hsotg->regs + GINTMSK;
616 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n",
617 (unsigned long)addr, dwc2_readl(addr));
618 addr = hsotg->regs + GRXSTSR;
619 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n",
620 (unsigned long)addr, dwc2_readl(addr));
621 addr = hsotg->regs + GRXFSIZ;
622 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n",
623 (unsigned long)addr, dwc2_readl(addr));
624 addr = hsotg->regs + GNPTXFSIZ;
625 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n",
626 (unsigned long)addr, dwc2_readl(addr));
627 addr = hsotg->regs + GNPTXSTS;
628 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n",
629 (unsigned long)addr, dwc2_readl(addr));
630 addr = hsotg->regs + GI2CCTL;
631 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n",
632 (unsigned long)addr, dwc2_readl(addr));
633 addr = hsotg->regs + GPVNDCTL;
634 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n",
635 (unsigned long)addr, dwc2_readl(addr));
636 addr = hsotg->regs + GGPIO;
637 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n",
638 (unsigned long)addr, dwc2_readl(addr));
639 addr = hsotg->regs + GUID;
640 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n",
641 (unsigned long)addr, dwc2_readl(addr));
642 addr = hsotg->regs + GSNPSID;
643 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n",
644 (unsigned long)addr, dwc2_readl(addr));
645 addr = hsotg->regs + GHWCFG1;
646 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n",
647 (unsigned long)addr, dwc2_readl(addr));
648 addr = hsotg->regs + GHWCFG2;
649 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n",
650 (unsigned long)addr, dwc2_readl(addr));
651 addr = hsotg->regs + GHWCFG3;
652 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n",
653 (unsigned long)addr, dwc2_readl(addr));
654 addr = hsotg->regs + GHWCFG4;
655 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n",
656 (unsigned long)addr, dwc2_readl(addr));
657 addr = hsotg->regs + GLPMCFG;
658 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n",
659 (unsigned long)addr, dwc2_readl(addr));
660 addr = hsotg->regs + GPWRDN;
661 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n",
662 (unsigned long)addr, dwc2_readl(addr));
663 addr = hsotg->regs + GDFIFOCFG;
664 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n",
665 (unsigned long)addr, dwc2_readl(addr));
666 addr = hsotg->regs + HPTXFSIZ;
667 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n",
668 (unsigned long)addr, dwc2_readl(addr));
669
670 addr = hsotg->regs + PCGCTL;
671 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n",
672 (unsigned long)addr, dwc2_readl(addr));
673#endif
674}
675
676/**
677 * dwc2_flush_tx_fifo() - Flushes a Tx FIFO
678 *
679 * @hsotg: Programming view of DWC_otg controller
680 * @num: Tx FIFO to flush
681 */
682void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
683{
684 u32 greset;
685 int count = 0;
686
687 dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
688
689 greset = GRSTCTL_TXFFLSH;
690 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
691 dwc2_writel(greset, hsotg->regs + GRSTCTL);
692
693 do {
694 greset = dwc2_readl(hsotg->regs + GRSTCTL);
695 if (++count > 10000) {
696 dev_warn(hsotg->dev,
697 "%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
698 __func__, greset,
699 dwc2_readl(hsotg->regs + GNPTXSTS));
700 break;
701 }
702 udelay(1);
703 } while (greset & GRSTCTL_TXFFLSH);
704
705 /* Wait for at least 3 PHY Clocks */
706 udelay(1);
707}
708
709/**
710 * dwc2_flush_rx_fifo() - Flushes the Rx FIFO
711 *
712 * @hsotg: Programming view of DWC_otg controller
713 */
714void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
715{
716 u32 greset;
717 int count = 0;
718
719 dev_vdbg(hsotg->dev, "%s()\n", __func__);
720
721 greset = GRSTCTL_RXFFLSH;
722 dwc2_writel(greset, hsotg->regs + GRSTCTL);
723
724 do {
725 greset = dwc2_readl(hsotg->regs + GRSTCTL);
726 if (++count > 10000) {
727 dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n",
728 __func__, greset);
729 break;
730 }
731 udelay(1);
732 } while (greset & GRSTCTL_RXFFLSH);
733
734 /* Wait for at least 3 PHY Clocks */
735 udelay(1);
736}
737
738/*
739 * Forces either host or device mode if the controller is not
740 * currently in that mode.
741 *
742 * Returns true if the mode was forced.
743 */
744bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host)
745{
746 if (host && dwc2_is_host_mode(hsotg))
747 return false;
748 else if (!host && dwc2_is_device_mode(hsotg))
749 return false;
750
751 return dwc2_force_mode(hsotg, host);
752}
753
754u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg)
755{
756 return hsotg->params.otg_ver == 1 ? 0x0200 : 0x0103;
757}
758
759bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
760{
761 if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff)
762 return false;
763 else
764 return true;
765}
766
767/**
768 * dwc2_enable_global_interrupts() - Enables the controller's Global
769 * Interrupt in the AHB Config register
770 *
771 * @hsotg: Programming view of DWC_otg controller
772 */
773void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
774{
775 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
776
777 ahbcfg |= GAHBCFG_GLBL_INTR_EN;
778 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
779}
780
781/**
782 * dwc2_disable_global_interrupts() - Disables the controller's Global
783 * Interrupt in the AHB Config register
784 *
785 * @hsotg: Programming view of DWC_otg controller
786 */
787void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
788{
789 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
790
791 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
792 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
793}
794
795/* Returns the controller's GHWCFG2.OTG_MODE. */
796unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg)
797{
798 u32 ghwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
799
800 return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >>
801 GHWCFG2_OP_MODE_SHIFT;
802}
803
804/* Returns true if the controller is capable of DRD. */
805bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg)
806{
807 unsigned op_mode = dwc2_op_mode(hsotg);
808
809 return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) ||
810 (op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) ||
811 (op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE);
812}
813
814/* Returns true if the controller is host-only. */
815bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg)
816{
817 unsigned op_mode = dwc2_op_mode(hsotg);
818
819 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) ||
820 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST);
821}
822
823/* Returns true if the controller is device-only. */
824bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg)
825{
826 unsigned op_mode = dwc2_op_mode(hsotg);
827
828 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
829 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE);
830}
831
832MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
833MODULE_AUTHOR("Synopsys, Inc.");
834MODULE_LICENSE("Dual BSD/GPL");
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * core.c - DesignWare HS OTG Controller common routines
4 *
5 * Copyright (C) 2004-2013 Synopsys, Inc.
6 */
7
8/*
9 * The Core code provides basic services for accessing and managing the
10 * DWC_otg hardware. These services are used by both the Host Controller
11 * Driver and the Peripheral Controller Driver.
12 */
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/spinlock.h>
17#include <linux/interrupt.h>
18#include <linux/dma-mapping.h>
19#include <linux/delay.h>
20#include <linux/io.h>
21#include <linux/slab.h>
22#include <linux/usb.h>
23
24#include <linux/usb/hcd.h>
25#include <linux/usb/ch11.h>
26
27#include "core.h"
28#include "hcd.h"
29
30/**
31 * dwc2_backup_global_registers() - Backup global controller registers.
32 * When suspending usb bus, registers needs to be backuped
33 * if controller power is disabled once suspended.
34 *
35 * @hsotg: Programming view of the DWC_otg controller
36 */
37int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
38{
39 struct dwc2_gregs_backup *gr;
40
41 dev_dbg(hsotg->dev, "%s\n", __func__);
42
43 /* Backup global regs */
44 gr = &hsotg->gr_backup;
45
46 gr->gotgctl = dwc2_readl(hsotg, GOTGCTL);
47 gr->gintmsk = dwc2_readl(hsotg, GINTMSK);
48 gr->gahbcfg = dwc2_readl(hsotg, GAHBCFG);
49 gr->gusbcfg = dwc2_readl(hsotg, GUSBCFG);
50 gr->grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
51 gr->gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
52 gr->gdfifocfg = dwc2_readl(hsotg, GDFIFOCFG);
53 gr->pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);
54 gr->glpmcfg = dwc2_readl(hsotg, GLPMCFG);
55 gr->gi2cctl = dwc2_readl(hsotg, GI2CCTL);
56 gr->pcgcctl = dwc2_readl(hsotg, PCGCTL);
57
58 gr->valid = true;
59 return 0;
60}
61
62/**
63 * dwc2_restore_global_registers() - Restore controller global registers.
64 * When resuming usb bus, device registers needs to be restored
65 * if controller power were disabled.
66 *
67 * @hsotg: Programming view of the DWC_otg controller
68 */
69int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
70{
71 struct dwc2_gregs_backup *gr;
72
73 dev_dbg(hsotg->dev, "%s\n", __func__);
74
75 /* Restore global regs */
76 gr = &hsotg->gr_backup;
77 if (!gr->valid) {
78 dev_err(hsotg->dev, "%s: no global registers to restore\n",
79 __func__);
80 return -EINVAL;
81 }
82 gr->valid = false;
83
84 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
85 dwc2_writel(hsotg, gr->gotgctl, GOTGCTL);
86 dwc2_writel(hsotg, gr->gintmsk, GINTMSK);
87 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
88 dwc2_writel(hsotg, gr->gahbcfg, GAHBCFG);
89 dwc2_writel(hsotg, gr->grxfsiz, GRXFSIZ);
90 dwc2_writel(hsotg, gr->gnptxfsiz, GNPTXFSIZ);
91 dwc2_writel(hsotg, gr->gdfifocfg, GDFIFOCFG);
92 dwc2_writel(hsotg, gr->pcgcctl1, PCGCCTL1);
93 dwc2_writel(hsotg, gr->glpmcfg, GLPMCFG);
94 dwc2_writel(hsotg, gr->pcgcctl, PCGCTL);
95 dwc2_writel(hsotg, gr->gi2cctl, GI2CCTL);
96
97 return 0;
98}
99
100/**
101 * dwc2_exit_partial_power_down() - Exit controller from Partial Power Down.
102 *
103 * @hsotg: Programming view of the DWC_otg controller
104 * @rem_wakeup: indicates whether resume is initiated by Reset.
105 * @restore: Controller registers need to be restored
106 */
107int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, int rem_wakeup,
108 bool restore)
109{
110 struct dwc2_gregs_backup *gr;
111
112 gr = &hsotg->gr_backup;
113
114 /*
115 * Restore host or device regisers with the same mode core enterted
116 * to partial power down by checking "GOTGCTL_CURMODE_HOST" backup
117 * value of the "gotgctl" register.
118 */
119 if (gr->gotgctl & GOTGCTL_CURMODE_HOST)
120 return dwc2_host_exit_partial_power_down(hsotg, rem_wakeup,
121 restore);
122 else
123 return dwc2_gadget_exit_partial_power_down(hsotg, restore);
124}
125
126/**
127 * dwc2_enter_partial_power_down() - Put controller in Partial Power Down.
128 *
129 * @hsotg: Programming view of the DWC_otg controller
130 */
131int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg)
132{
133 if (dwc2_is_host_mode(hsotg))
134 return dwc2_host_enter_partial_power_down(hsotg);
135 else
136 return dwc2_gadget_enter_partial_power_down(hsotg);
137}
138
139/**
140 * dwc2_restore_essential_regs() - Restore essiential regs of core.
141 *
142 * @hsotg: Programming view of the DWC_otg controller
143 * @rmode: Restore mode, enabled in case of remote-wakeup.
144 * @is_host: Host or device mode.
145 */
146static void dwc2_restore_essential_regs(struct dwc2_hsotg *hsotg, int rmode,
147 int is_host)
148{
149 u32 pcgcctl;
150 struct dwc2_gregs_backup *gr;
151 struct dwc2_dregs_backup *dr;
152 struct dwc2_hregs_backup *hr;
153
154 gr = &hsotg->gr_backup;
155 dr = &hsotg->dr_backup;
156 hr = &hsotg->hr_backup;
157
158 dev_dbg(hsotg->dev, "%s: restoring essential regs\n", __func__);
159
160 /* Load restore values for [31:14] bits */
161 pcgcctl = (gr->pcgcctl & 0xffffc000);
162 /* If High Speed */
163 if (is_host) {
164 if (!(pcgcctl & PCGCTL_P2HD_PRT_SPD_MASK))
165 pcgcctl |= BIT(17);
166 } else {
167 if (!(pcgcctl & PCGCTL_P2HD_DEV_ENUM_SPD_MASK))
168 pcgcctl |= BIT(17);
169 }
170 dwc2_writel(hsotg, pcgcctl, PCGCTL);
171
172 /* Umnask global Interrupt in GAHBCFG and restore it */
173 dwc2_writel(hsotg, gr->gahbcfg | GAHBCFG_GLBL_INTR_EN, GAHBCFG);
174
175 /* Clear all pending interupts */
176 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
177
178 /* Unmask restore done interrupt */
179 dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTMSK);
180
181 /* Restore GUSBCFG and HCFG/DCFG */
182 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
183
184 if (is_host) {
185 dwc2_writel(hsotg, hr->hcfg, HCFG);
186 if (rmode)
187 pcgcctl |= PCGCTL_RESTOREMODE;
188 dwc2_writel(hsotg, pcgcctl, PCGCTL);
189 udelay(10);
190
191 pcgcctl |= PCGCTL_ESS_REG_RESTORED;
192 dwc2_writel(hsotg, pcgcctl, PCGCTL);
193 udelay(10);
194 } else {
195 dwc2_writel(hsotg, dr->dcfg, DCFG);
196 if (!rmode)
197 pcgcctl |= PCGCTL_RESTOREMODE | PCGCTL_RSTPDWNMODULE;
198 dwc2_writel(hsotg, pcgcctl, PCGCTL);
199 udelay(10);
200
201 pcgcctl |= PCGCTL_ESS_REG_RESTORED;
202 dwc2_writel(hsotg, pcgcctl, PCGCTL);
203 udelay(10);
204 }
205}
206
207/**
208 * dwc2_hib_restore_common() - Common part of restore routine.
209 *
210 * @hsotg: Programming view of the DWC_otg controller
211 * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup.
212 * @is_host: Host or device mode.
213 */
214void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup,
215 int is_host)
216{
217 u32 gpwrdn;
218
219 /* Switch-on voltage to the core */
220 gpwrdn = dwc2_readl(hsotg, GPWRDN);
221 gpwrdn &= ~GPWRDN_PWRDNSWTCH;
222 dwc2_writel(hsotg, gpwrdn, GPWRDN);
223 udelay(10);
224
225 /* Reset core */
226 gpwrdn = dwc2_readl(hsotg, GPWRDN);
227 gpwrdn &= ~GPWRDN_PWRDNRSTN;
228 dwc2_writel(hsotg, gpwrdn, GPWRDN);
229 udelay(10);
230
231 /* Enable restore from PMU */
232 gpwrdn = dwc2_readl(hsotg, GPWRDN);
233 gpwrdn |= GPWRDN_RESTORE;
234 dwc2_writel(hsotg, gpwrdn, GPWRDN);
235 udelay(10);
236
237 /* Disable Power Down Clamp */
238 gpwrdn = dwc2_readl(hsotg, GPWRDN);
239 gpwrdn &= ~GPWRDN_PWRDNCLMP;
240 dwc2_writel(hsotg, gpwrdn, GPWRDN);
241 udelay(50);
242
243 if (!is_host && rem_wakeup)
244 udelay(70);
245
246 /* Deassert reset core */
247 gpwrdn = dwc2_readl(hsotg, GPWRDN);
248 gpwrdn |= GPWRDN_PWRDNRSTN;
249 dwc2_writel(hsotg, gpwrdn, GPWRDN);
250 udelay(10);
251
252 /* Disable PMU interrupt */
253 gpwrdn = dwc2_readl(hsotg, GPWRDN);
254 gpwrdn &= ~GPWRDN_PMUINTSEL;
255 dwc2_writel(hsotg, gpwrdn, GPWRDN);
256 udelay(10);
257
258 /* Set Restore Essential Regs bit in PCGCCTL register */
259 dwc2_restore_essential_regs(hsotg, rem_wakeup, is_host);
260
261 /*
262 * Wait For Restore_done Interrupt. This mechanism of polling the
263 * interrupt is introduced to avoid any possible race conditions
264 */
265 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, GINTSTS_RESTOREDONE,
266 20000)) {
267 dev_dbg(hsotg->dev,
268 "%s: Restore Done wasn't generated here\n",
269 __func__);
270 } else {
271 dev_dbg(hsotg->dev, "restore done generated here\n");
272
273 /*
274 * To avoid restore done interrupt storm after restore is
275 * generated clear GINTSTS_RESTOREDONE bit.
276 */
277 dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTSTS);
278 }
279}
280
281/**
282 * dwc2_wait_for_mode() - Waits for the controller mode.
283 * @hsotg: Programming view of the DWC_otg controller.
284 * @host_mode: If true, waits for host mode, otherwise device mode.
285 */
286static void dwc2_wait_for_mode(struct dwc2_hsotg *hsotg,
287 bool host_mode)
288{
289 ktime_t start;
290 ktime_t end;
291 unsigned int timeout = 110;
292
293 dev_vdbg(hsotg->dev, "Waiting for %s mode\n",
294 host_mode ? "host" : "device");
295
296 start = ktime_get();
297
298 while (1) {
299 s64 ms;
300
301 if (dwc2_is_host_mode(hsotg) == host_mode) {
302 dev_vdbg(hsotg->dev, "%s mode set\n",
303 host_mode ? "Host" : "Device");
304 break;
305 }
306
307 end = ktime_get();
308 ms = ktime_to_ms(ktime_sub(end, start));
309
310 if (ms >= (s64)timeout) {
311 dev_warn(hsotg->dev, "%s: Couldn't set %s mode\n",
312 __func__, host_mode ? "host" : "device");
313 break;
314 }
315
316 usleep_range(1000, 2000);
317 }
318}
319
320/**
321 * dwc2_iddig_filter_enabled() - Returns true if the IDDIG debounce
322 * filter is enabled.
323 *
324 * @hsotg: Programming view of DWC_otg controller
325 */
326static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg)
327{
328 u32 gsnpsid;
329 u32 ghwcfg4;
330
331 if (!dwc2_hw_is_otg(hsotg))
332 return false;
333
334 /* Check if core configuration includes the IDDIG filter. */
335 ghwcfg4 = dwc2_readl(hsotg, GHWCFG4);
336 if (!(ghwcfg4 & GHWCFG4_IDDIG_FILT_EN))
337 return false;
338
339 /*
340 * Check if the IDDIG debounce filter is bypassed. Available
341 * in core version >= 3.10a.
342 */
343 gsnpsid = dwc2_readl(hsotg, GSNPSID);
344 if (gsnpsid >= DWC2_CORE_REV_3_10a) {
345 u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);
346
347 if (gotgctl & GOTGCTL_DBNCE_FLTR_BYPASS)
348 return false;
349 }
350
351 return true;
352}
353
354/*
355 * dwc2_enter_hibernation() - Common function to enter hibernation.
356 *
357 * @hsotg: Programming view of the DWC_otg controller
358 * @is_host: True if core is in host mode.
359 *
360 * Return: 0 if successful, negative error code otherwise
361 */
362int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host)
363{
364 if (is_host)
365 return dwc2_host_enter_hibernation(hsotg);
366 else
367 return dwc2_gadget_enter_hibernation(hsotg);
368}
369
370/*
371 * dwc2_exit_hibernation() - Common function to exit from hibernation.
372 *
373 * @hsotg: Programming view of the DWC_otg controller
374 * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup.
375 * @reset: Enabled in case of restore with reset.
376 * @is_host: True if core is in host mode.
377 *
378 * Return: 0 if successful, negative error code otherwise
379 */
380int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
381 int reset, int is_host)
382{
383 if (is_host)
384 return dwc2_host_exit_hibernation(hsotg, rem_wakeup, reset);
385 else
386 return dwc2_gadget_exit_hibernation(hsotg, rem_wakeup, reset);
387}
388
389/*
390 * Do core a soft reset of the core. Be careful with this because it
391 * resets all the internal state machines of the core.
392 */
393int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait)
394{
395 u32 greset;
396 bool wait_for_host_mode = false;
397
398 dev_vdbg(hsotg->dev, "%s()\n", __func__);
399
400 /*
401 * If the current mode is host, either due to the force mode
402 * bit being set (which persists after core reset) or the
403 * connector id pin, a core soft reset will temporarily reset
404 * the mode to device. A delay from the IDDIG debounce filter
405 * will occur before going back to host mode.
406 *
407 * Determine whether we will go back into host mode after a
408 * reset and account for this delay after the reset.
409 */
410 if (dwc2_iddig_filter_enabled(hsotg)) {
411 u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);
412 u32 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
413
414 if (!(gotgctl & GOTGCTL_CONID_B) ||
415 (gusbcfg & GUSBCFG_FORCEHOSTMODE)) {
416 wait_for_host_mode = true;
417 }
418 }
419
420 /* Core Soft Reset */
421 greset = dwc2_readl(hsotg, GRSTCTL);
422 greset |= GRSTCTL_CSFTRST;
423 dwc2_writel(hsotg, greset, GRSTCTL);
424
425 if ((hsotg->hw_params.snpsid & DWC2_CORE_REV_MASK) <
426 (DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) {
427 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL,
428 GRSTCTL_CSFTRST, 10000)) {
429 dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST\n",
430 __func__);
431 return -EBUSY;
432 }
433 } else {
434 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL,
435 GRSTCTL_CSFTRST_DONE, 10000)) {
436 dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST_DONE\n",
437 __func__);
438 return -EBUSY;
439 }
440 greset = dwc2_readl(hsotg, GRSTCTL);
441 greset &= ~GRSTCTL_CSFTRST;
442 greset |= GRSTCTL_CSFTRST_DONE;
443 dwc2_writel(hsotg, greset, GRSTCTL);
444 }
445
446 /*
447 * Switching from device mode to host mode by disconnecting
448 * device cable core enters and exits form hibernation.
449 * However, the fifo map remains not cleared. It results
450 * to a WARNING (WARNING: CPU: 5 PID: 0 at drivers/usb/dwc2/
451 * gadget.c:307 dwc2_hsotg_init_fifo+0x12/0x152 [dwc2])
452 * if in host mode we disconnect the micro a to b host
453 * cable. Because core reset occurs.
454 * To avoid the WARNING, fifo_map should be cleared
455 * in dwc2_core_reset() function by taking into account configs.
456 * fifo_map must be cleared only if driver is configured in
457 * "CONFIG_USB_DWC2_PERIPHERAL" or "CONFIG_USB_DWC2_DUAL_ROLE"
458 * mode.
459 */
460 dwc2_clear_fifo_map(hsotg);
461
462 /* Wait for AHB master IDLE state */
463 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000)) {
464 dev_warn(hsotg->dev, "%s: HANG! AHB Idle timeout GRSTCTL GRSTCTL_AHBIDLE\n",
465 __func__);
466 return -EBUSY;
467 }
468
469 if (wait_for_host_mode && !skip_wait)
470 dwc2_wait_for_mode(hsotg, true);
471
472 return 0;
473}
474
475/**
476 * dwc2_force_mode() - Force the mode of the controller.
477 *
478 * Forcing the mode is needed for two cases:
479 *
480 * 1) If the dr_mode is set to either HOST or PERIPHERAL we force the
481 * controller to stay in a particular mode regardless of ID pin
482 * changes. We do this once during probe.
483 *
484 * 2) During probe we want to read reset values of the hw
485 * configuration registers that are only available in either host or
486 * device mode. We may need to force the mode if the current mode does
487 * not allow us to access the register in the mode that we want.
488 *
489 * In either case it only makes sense to force the mode if the
490 * controller hardware is OTG capable.
491 *
492 * Checks are done in this function to determine whether doing a force
493 * would be valid or not.
494 *
495 * If a force is done, it requires a IDDIG debounce filter delay if
496 * the filter is configured and enabled. We poll the current mode of
497 * the controller to account for this delay.
498 *
499 * @hsotg: Programming view of DWC_otg controller
500 * @host: Host mode flag
501 */
502void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
503{
504 u32 gusbcfg;
505 u32 set;
506 u32 clear;
507
508 dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device");
509
510 /*
511 * Force mode has no effect if the hardware is not OTG.
512 */
513 if (!dwc2_hw_is_otg(hsotg))
514 return;
515
516 /*
517 * If dr_mode is either peripheral or host only, there is no
518 * need to ever force the mode to the opposite mode.
519 */
520 if (WARN_ON(host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL))
521 return;
522
523 if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST))
524 return;
525
526 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
527
528 set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE;
529 clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE;
530
531 gusbcfg &= ~clear;
532 gusbcfg |= set;
533 dwc2_writel(hsotg, gusbcfg, GUSBCFG);
534
535 dwc2_wait_for_mode(hsotg, host);
536 return;
537}
538
539/**
540 * dwc2_clear_force_mode() - Clears the force mode bits.
541 *
542 * After clearing the bits, wait up to 100 ms to account for any
543 * potential IDDIG filter delay. We can't know if we expect this delay
544 * or not because the value of the connector ID status is affected by
545 * the force mode. We only need to call this once during probe if
546 * dr_mode == OTG.
547 *
548 * @hsotg: Programming view of DWC_otg controller
549 */
550static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg)
551{
552 u32 gusbcfg;
553
554 if (!dwc2_hw_is_otg(hsotg))
555 return;
556
557 dev_dbg(hsotg->dev, "Clearing force mode bits\n");
558
559 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
560 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
561 gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
562 dwc2_writel(hsotg, gusbcfg, GUSBCFG);
563
564 if (dwc2_iddig_filter_enabled(hsotg))
565 msleep(100);
566}
567
568/*
569 * Sets or clears force mode based on the dr_mode parameter.
570 */
571void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
572{
573 switch (hsotg->dr_mode) {
574 case USB_DR_MODE_HOST:
575 /*
576 * NOTE: This is required for some rockchip soc based
577 * platforms on their host-only dwc2.
578 */
579 if (!dwc2_hw_is_otg(hsotg))
580 msleep(50);
581
582 break;
583 case USB_DR_MODE_PERIPHERAL:
584 dwc2_force_mode(hsotg, false);
585 break;
586 case USB_DR_MODE_OTG:
587 dwc2_clear_force_mode(hsotg);
588 break;
589 default:
590 dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n",
591 __func__, hsotg->dr_mode);
592 break;
593 }
594}
595
596/*
597 * dwc2_enable_acg - enable active clock gating feature
598 */
599void dwc2_enable_acg(struct dwc2_hsotg *hsotg)
600{
601 if (hsotg->params.acg_enable) {
602 u32 pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);
603
604 dev_dbg(hsotg->dev, "Enabling Active Clock Gating\n");
605 pcgcctl1 |= PCGCCTL1_GATEEN;
606 dwc2_writel(hsotg, pcgcctl1, PCGCCTL1);
607 }
608}
609
610/**
611 * dwc2_dump_host_registers() - Prints the host registers
612 *
613 * @hsotg: Programming view of DWC_otg controller
614 *
615 * NOTE: This function will be removed once the peripheral controller code
616 * is integrated and the driver is stable
617 */
618void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
619{
620#ifdef DEBUG
621 u32 __iomem *addr;
622 int i;
623
624 dev_dbg(hsotg->dev, "Host Global Registers\n");
625 addr = hsotg->regs + HCFG;
626 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n",
627 (unsigned long)addr, dwc2_readl(hsotg, HCFG));
628 addr = hsotg->regs + HFIR;
629 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n",
630 (unsigned long)addr, dwc2_readl(hsotg, HFIR));
631 addr = hsotg->regs + HFNUM;
632 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n",
633 (unsigned long)addr, dwc2_readl(hsotg, HFNUM));
634 addr = hsotg->regs + HPTXSTS;
635 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n",
636 (unsigned long)addr, dwc2_readl(hsotg, HPTXSTS));
637 addr = hsotg->regs + HAINT;
638 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n",
639 (unsigned long)addr, dwc2_readl(hsotg, HAINT));
640 addr = hsotg->regs + HAINTMSK;
641 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n",
642 (unsigned long)addr, dwc2_readl(hsotg, HAINTMSK));
643 if (hsotg->params.dma_desc_enable) {
644 addr = hsotg->regs + HFLBADDR;
645 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
646 (unsigned long)addr, dwc2_readl(hsotg, HFLBADDR));
647 }
648
649 addr = hsotg->regs + HPRT0;
650 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n",
651 (unsigned long)addr, dwc2_readl(hsotg, HPRT0));
652
653 for (i = 0; i < hsotg->params.host_channels; i++) {
654 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
655 addr = hsotg->regs + HCCHAR(i);
656 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n",
657 (unsigned long)addr, dwc2_readl(hsotg, HCCHAR(i)));
658 addr = hsotg->regs + HCSPLT(i);
659 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n",
660 (unsigned long)addr, dwc2_readl(hsotg, HCSPLT(i)));
661 addr = hsotg->regs + HCINT(i);
662 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n",
663 (unsigned long)addr, dwc2_readl(hsotg, HCINT(i)));
664 addr = hsotg->regs + HCINTMSK(i);
665 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n",
666 (unsigned long)addr, dwc2_readl(hsotg, HCINTMSK(i)));
667 addr = hsotg->regs + HCTSIZ(i);
668 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n",
669 (unsigned long)addr, dwc2_readl(hsotg, HCTSIZ(i)));
670 addr = hsotg->regs + HCDMA(i);
671 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n",
672 (unsigned long)addr, dwc2_readl(hsotg, HCDMA(i)));
673 if (hsotg->params.dma_desc_enable) {
674 addr = hsotg->regs + HCDMAB(i);
675 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n",
676 (unsigned long)addr, dwc2_readl(hsotg,
677 HCDMAB(i)));
678 }
679 }
680#endif
681}
682
683/**
684 * dwc2_dump_global_registers() - Prints the core global registers
685 *
686 * @hsotg: Programming view of DWC_otg controller
687 *
688 * NOTE: This function will be removed once the peripheral controller code
689 * is integrated and the driver is stable
690 */
691void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
692{
693#ifdef DEBUG
694 u32 __iomem *addr;
695
696 dev_dbg(hsotg->dev, "Core Global Registers\n");
697 addr = hsotg->regs + GOTGCTL;
698 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n",
699 (unsigned long)addr, dwc2_readl(hsotg, GOTGCTL));
700 addr = hsotg->regs + GOTGINT;
701 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n",
702 (unsigned long)addr, dwc2_readl(hsotg, GOTGINT));
703 addr = hsotg->regs + GAHBCFG;
704 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n",
705 (unsigned long)addr, dwc2_readl(hsotg, GAHBCFG));
706 addr = hsotg->regs + GUSBCFG;
707 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n",
708 (unsigned long)addr, dwc2_readl(hsotg, GUSBCFG));
709 addr = hsotg->regs + GRSTCTL;
710 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n",
711 (unsigned long)addr, dwc2_readl(hsotg, GRSTCTL));
712 addr = hsotg->regs + GINTSTS;
713 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n",
714 (unsigned long)addr, dwc2_readl(hsotg, GINTSTS));
715 addr = hsotg->regs + GINTMSK;
716 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n",
717 (unsigned long)addr, dwc2_readl(hsotg, GINTMSK));
718 addr = hsotg->regs + GRXSTSR;
719 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n",
720 (unsigned long)addr, dwc2_readl(hsotg, GRXSTSR));
721 addr = hsotg->regs + GRXFSIZ;
722 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n",
723 (unsigned long)addr, dwc2_readl(hsotg, GRXFSIZ));
724 addr = hsotg->regs + GNPTXFSIZ;
725 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n",
726 (unsigned long)addr, dwc2_readl(hsotg, GNPTXFSIZ));
727 addr = hsotg->regs + GNPTXSTS;
728 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n",
729 (unsigned long)addr, dwc2_readl(hsotg, GNPTXSTS));
730 addr = hsotg->regs + GI2CCTL;
731 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n",
732 (unsigned long)addr, dwc2_readl(hsotg, GI2CCTL));
733 addr = hsotg->regs + GPVNDCTL;
734 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n",
735 (unsigned long)addr, dwc2_readl(hsotg, GPVNDCTL));
736 addr = hsotg->regs + GGPIO;
737 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n",
738 (unsigned long)addr, dwc2_readl(hsotg, GGPIO));
739 addr = hsotg->regs + GUID;
740 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n",
741 (unsigned long)addr, dwc2_readl(hsotg, GUID));
742 addr = hsotg->regs + GSNPSID;
743 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n",
744 (unsigned long)addr, dwc2_readl(hsotg, GSNPSID));
745 addr = hsotg->regs + GHWCFG1;
746 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n",
747 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG1));
748 addr = hsotg->regs + GHWCFG2;
749 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n",
750 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG2));
751 addr = hsotg->regs + GHWCFG3;
752 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n",
753 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG3));
754 addr = hsotg->regs + GHWCFG4;
755 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n",
756 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG4));
757 addr = hsotg->regs + GLPMCFG;
758 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n",
759 (unsigned long)addr, dwc2_readl(hsotg, GLPMCFG));
760 addr = hsotg->regs + GPWRDN;
761 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n",
762 (unsigned long)addr, dwc2_readl(hsotg, GPWRDN));
763 addr = hsotg->regs + GDFIFOCFG;
764 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n",
765 (unsigned long)addr, dwc2_readl(hsotg, GDFIFOCFG));
766 addr = hsotg->regs + HPTXFSIZ;
767 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n",
768 (unsigned long)addr, dwc2_readl(hsotg, HPTXFSIZ));
769
770 addr = hsotg->regs + PCGCTL;
771 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n",
772 (unsigned long)addr, dwc2_readl(hsotg, PCGCTL));
773#endif
774}
775
776/**
777 * dwc2_flush_tx_fifo() - Flushes a Tx FIFO
778 *
779 * @hsotg: Programming view of DWC_otg controller
780 * @num: Tx FIFO to flush
781 */
782void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
783{
784 u32 greset;
785
786 dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
787
788 /* Wait for AHB master IDLE state */
789 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000))
790 dev_warn(hsotg->dev, "%s: HANG! AHB Idle GRSCTL\n",
791 __func__);
792
793 greset = GRSTCTL_TXFFLSH;
794 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
795 dwc2_writel(hsotg, greset, GRSTCTL);
796
797 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 10000))
798 dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_TXFFLSH\n",
799 __func__);
800
801 /* Wait for at least 3 PHY Clocks */
802 udelay(1);
803}
804
805/**
806 * dwc2_flush_rx_fifo() - Flushes the Rx FIFO
807 *
808 * @hsotg: Programming view of DWC_otg controller
809 */
810void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
811{
812 u32 greset;
813
814 dev_vdbg(hsotg->dev, "%s()\n", __func__);
815
816 /* Wait for AHB master IDLE state */
817 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000))
818 dev_warn(hsotg->dev, "%s: HANG! AHB Idle GRSCTL\n",
819 __func__);
820
821 greset = GRSTCTL_RXFFLSH;
822 dwc2_writel(hsotg, greset, GRSTCTL);
823
824 /* Wait for RxFIFO flush done */
825 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_RXFFLSH, 10000))
826 dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_RXFFLSH\n",
827 __func__);
828
829 /* Wait for at least 3 PHY Clocks */
830 udelay(1);
831}
832
833bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
834{
835 if (dwc2_readl(hsotg, GSNPSID) == 0xffffffff)
836 return false;
837 else
838 return true;
839}
840
841/**
842 * dwc2_enable_global_interrupts() - Enables the controller's Global
843 * Interrupt in the AHB Config register
844 *
845 * @hsotg: Programming view of DWC_otg controller
846 */
847void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
848{
849 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
850
851 ahbcfg |= GAHBCFG_GLBL_INTR_EN;
852 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
853}
854
855/**
856 * dwc2_disable_global_interrupts() - Disables the controller's Global
857 * Interrupt in the AHB Config register
858 *
859 * @hsotg: Programming view of DWC_otg controller
860 */
861void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
862{
863 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
864
865 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
866 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
867}
868
869/* Returns the controller's GHWCFG2.OTG_MODE. */
870unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg)
871{
872 u32 ghwcfg2 = dwc2_readl(hsotg, GHWCFG2);
873
874 return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >>
875 GHWCFG2_OP_MODE_SHIFT;
876}
877
878/* Returns true if the controller is capable of DRD. */
879bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg)
880{
881 unsigned int op_mode = dwc2_op_mode(hsotg);
882
883 return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) ||
884 (op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) ||
885 (op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE);
886}
887
888/* Returns true if the controller is host-only. */
889bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg)
890{
891 unsigned int op_mode = dwc2_op_mode(hsotg);
892
893 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) ||
894 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST);
895}
896
897/* Returns true if the controller is device-only. */
898bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg)
899{
900 unsigned int op_mode = dwc2_op_mode(hsotg);
901
902 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
903 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE);
904}
905
906/**
907 * dwc2_hsotg_wait_bit_set - Waits for bit to be set.
908 * @hsotg: Programming view of DWC_otg controller.
909 * @offset: Register's offset where bit/bits must be set.
910 * @mask: Mask of the bit/bits which must be set.
911 * @timeout: Timeout to wait.
912 *
913 * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout.
914 */
915int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,
916 u32 timeout)
917{
918 u32 i;
919
920 for (i = 0; i < timeout; i++) {
921 if (dwc2_readl(hsotg, offset) & mask)
922 return 0;
923 udelay(1);
924 }
925
926 return -ETIMEDOUT;
927}
928
929/**
930 * dwc2_hsotg_wait_bit_clear - Waits for bit to be clear.
931 * @hsotg: Programming view of DWC_otg controller.
932 * @offset: Register's offset where bit/bits must be set.
933 * @mask: Mask of the bit/bits which must be set.
934 * @timeout: Timeout to wait.
935 *
936 * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout.
937 */
938int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,
939 u32 timeout)
940{
941 u32 i;
942
943 for (i = 0; i < timeout; i++) {
944 if (!(dwc2_readl(hsotg, offset) & mask))
945 return 0;
946 udelay(1);
947 }
948
949 return -ETIMEDOUT;
950}
951
952/*
953 * Initializes the FSLSPClkSel field of the HCFG register depending on the
954 * PHY type
955 */
956void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
957{
958 u32 hcfg, val;
959
960 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
961 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
962 hsotg->params.ulpi_fs_ls) ||
963 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
964 /* Full speed PHY */
965 val = HCFG_FSLSPCLKSEL_48_MHZ;
966 } else {
967 /* High speed PHY running at full speed or high speed */
968 val = HCFG_FSLSPCLKSEL_30_60_MHZ;
969 }
970
971 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
972 hcfg = dwc2_readl(hsotg, HCFG);
973 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
974 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
975 dwc2_writel(hsotg, hcfg, HCFG);
976}
977
978static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
979{
980 u32 usbcfg, ggpio, i2cctl;
981 int retval = 0;
982
983 /*
984 * core_init() is now called on every switch so only call the
985 * following for the first time through
986 */
987 if (select_phy) {
988 dev_dbg(hsotg->dev, "FS PHY selected\n");
989
990 usbcfg = dwc2_readl(hsotg, GUSBCFG);
991 if (!(usbcfg & GUSBCFG_PHYSEL)) {
992 usbcfg |= GUSBCFG_PHYSEL;
993 dwc2_writel(hsotg, usbcfg, GUSBCFG);
994
995 /* Reset after a PHY select */
996 retval = dwc2_core_reset(hsotg, false);
997
998 if (retval) {
999 dev_err(hsotg->dev,
1000 "%s: Reset failed, aborting", __func__);
1001 return retval;
1002 }
1003 }
1004
1005 if (hsotg->params.activate_stm_fs_transceiver) {
1006 ggpio = dwc2_readl(hsotg, GGPIO);
1007 if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) {
1008 dev_dbg(hsotg->dev, "Activating transceiver\n");
1009 /*
1010 * STM32F4x9 uses the GGPIO register as general
1011 * core configuration register.
1012 */
1013 ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
1014 dwc2_writel(hsotg, ggpio, GGPIO);
1015 }
1016 }
1017 }
1018
1019 /*
1020 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
1021 * do this on HNP Dev/Host mode switches (done in dev_init and
1022 * host_init).
1023 */
1024 if (dwc2_is_host_mode(hsotg))
1025 dwc2_init_fs_ls_pclk_sel(hsotg);
1026
1027 if (hsotg->params.i2c_enable) {
1028 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
1029
1030 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
1031 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1032 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
1033 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1034
1035 /* Program GI2CCTL.I2CEn */
1036 i2cctl = dwc2_readl(hsotg, GI2CCTL);
1037 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
1038 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
1039 i2cctl &= ~GI2CCTL_I2CEN;
1040 dwc2_writel(hsotg, i2cctl, GI2CCTL);
1041 i2cctl |= GI2CCTL_I2CEN;
1042 dwc2_writel(hsotg, i2cctl, GI2CCTL);
1043 }
1044
1045 return retval;
1046}
1047
1048static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
1049{
1050 u32 usbcfg, usbcfg_old;
1051 int retval = 0;
1052
1053 if (!select_phy)
1054 return 0;
1055
1056 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1057 usbcfg_old = usbcfg;
1058
1059 /*
1060 * HS PHY parameters. These parameters are preserved during soft reset
1061 * so only program the first time. Do a soft reset immediately after
1062 * setting phyif.
1063 */
1064 switch (hsotg->params.phy_type) {
1065 case DWC2_PHY_TYPE_PARAM_ULPI:
1066 /* ULPI interface */
1067 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
1068 usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
1069 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
1070 if (hsotg->params.phy_ulpi_ddr)
1071 usbcfg |= GUSBCFG_DDRSEL;
1072
1073 /* Set external VBUS indicator as needed. */
1074 if (hsotg->params.oc_disable)
1075 usbcfg |= (GUSBCFG_ULPI_INT_VBUS_IND |
1076 GUSBCFG_INDICATORPASSTHROUGH);
1077 break;
1078 case DWC2_PHY_TYPE_PARAM_UTMI:
1079 /* UTMI+ interface */
1080 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
1081 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
1082 if (hsotg->params.phy_utmi_width == 16)
1083 usbcfg |= GUSBCFG_PHYIF16;
1084 break;
1085 default:
1086 dev_err(hsotg->dev, "FS PHY selected at HS!\n");
1087 break;
1088 }
1089
1090 if (usbcfg != usbcfg_old) {
1091 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1092
1093 /* Reset after setting the PHY parameters */
1094 retval = dwc2_core_reset(hsotg, false);
1095 if (retval) {
1096 dev_err(hsotg->dev,
1097 "%s: Reset failed, aborting", __func__);
1098 return retval;
1099 }
1100 }
1101
1102 return retval;
1103}
1104
1105static void dwc2_set_turnaround_time(struct dwc2_hsotg *hsotg)
1106{
1107 u32 usbcfg;
1108
1109 if (hsotg->params.phy_type != DWC2_PHY_TYPE_PARAM_UTMI)
1110 return;
1111
1112 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1113
1114 usbcfg &= ~GUSBCFG_USBTRDTIM_MASK;
1115 if (hsotg->params.phy_utmi_width == 16)
1116 usbcfg |= 5 << GUSBCFG_USBTRDTIM_SHIFT;
1117 else
1118 usbcfg |= 9 << GUSBCFG_USBTRDTIM_SHIFT;
1119
1120 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1121}
1122
1123int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
1124{
1125 u32 usbcfg;
1126 u32 otgctl;
1127 int retval = 0;
1128
1129 if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
1130 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) &&
1131 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
1132 /* If FS/LS mode with FS/LS PHY */
1133 retval = dwc2_fs_phy_init(hsotg, select_phy);
1134 if (retval)
1135 return retval;
1136 } else {
1137 /* High speed PHY */
1138 retval = dwc2_hs_phy_init(hsotg, select_phy);
1139 if (retval)
1140 return retval;
1141
1142 if (dwc2_is_device_mode(hsotg))
1143 dwc2_set_turnaround_time(hsotg);
1144 }
1145
1146 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
1147 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
1148 hsotg->params.ulpi_fs_ls) {
1149 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
1150 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1151 usbcfg |= GUSBCFG_ULPI_FS_LS;
1152 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
1153 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1154 } else {
1155 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1156 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
1157 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
1158 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1159 }
1160
1161 if (!hsotg->params.activate_ingenic_overcurrent_detection) {
1162 if (dwc2_is_host_mode(hsotg)) {
1163 otgctl = readl(hsotg->regs + GOTGCTL);
1164 otgctl |= GOTGCTL_VBVALOEN | GOTGCTL_VBVALOVAL;
1165 writel(otgctl, hsotg->regs + GOTGCTL);
1166 }
1167 }
1168
1169 return retval;
1170}
1171
1172MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
1173MODULE_AUTHOR("Synopsys, Inc.");
1174MODULE_LICENSE("Dual BSD/GPL");