1/* Renesas R-Car CAN FD device driver
   2 *
   3 * Copyright (C) 2015 Renesas Electronics Corp.
   4 *
   5 * This program is free software; you can redistribute  it and/or modify it
   6 * under  the terms of  the GNU General  Public License as published by the
   7 * Free Software Foundation;  either version 2 of the  License, or (at your
   8 * option) any later version.
   9 */
  10
  11/* The R-Car CAN FD controller can operate in either one of the below two modes
  12 *  - CAN FD only mode
  13 *  - Classical CAN (CAN 2.0) only mode
  14 *
  15 * This driver puts the controller in CAN FD only mode by default. In this
  16 * mode, the controller acts as a CAN FD node that can also interoperate with
  17 * CAN 2.0 nodes.
  18 *
  19 * To switch the controller to Classical CAN (CAN 2.0) only mode, add
  20 * "renesas,no-can-fd" optional property to the device tree node. A h/w reset is
  21 * also required to switch modes.
  22 *
  23 * Note: The h/w manual register naming convention is clumsy and not acceptable
  24 * to use as it is in the driver. However, those names are added as comments
  25 * wherever it is modified to a readable name.
  26 */
  27
  28#include <linux/module.h>
  29#include <linux/moduleparam.h>
  30#include <linux/kernel.h>
  31#include <linux/types.h>
  32#include <linux/interrupt.h>
  33#include <linux/errno.h>
 
  34#include <linux/netdevice.h>
  35#include <linux/platform_device.h>
  36#include <linux/can/led.h>
  37#include <linux/can/dev.h>
  38#include <linux/clk.h>
  39#include <linux/of.h>
  40#include <linux/of_device.h>
  41#include <linux/bitmap.h>
  42#include <linux/bitops.h>
  43#include <linux/iopoll.h>
 
  44
  45#define RCANFD_DRV_NAME			"rcar_canfd"
  46
  47/* Global register bits */
  48
  49/* RSCFDnCFDGRMCFG */
  50#define RCANFD_GRMCFG_RCMC		BIT(0)
  51
  52/* RSCFDnCFDGCFG / RSCFDnGCFG */
  53#define RCANFD_GCFG_EEFE		BIT(6)
  54#define RCANFD_GCFG_CMPOC		BIT(5)	/* CAN FD only */
  55#define RCANFD_GCFG_DCS			BIT(4)
  56#define RCANFD_GCFG_DCE			BIT(1)
  57#define RCANFD_GCFG_TPRI		BIT(0)
  58
  59/* RSCFDnCFDGCTR / RSCFDnGCTR */
  60#define RCANFD_GCTR_TSRST		BIT(16)
  61#define RCANFD_GCTR_CFMPOFIE		BIT(11)	/* CAN FD only */
  62#define RCANFD_GCTR_THLEIE		BIT(10)
  63#define RCANFD_GCTR_MEIE		BIT(9)
  64#define RCANFD_GCTR_DEIE		BIT(8)
  65#define RCANFD_GCTR_GSLPR		BIT(2)
  66#define RCANFD_GCTR_GMDC_MASK		(0x3)
  67#define RCANFD_GCTR_GMDC_GOPM		(0x0)
  68#define RCANFD_GCTR_GMDC_GRESET		(0x1)
  69#define RCANFD_GCTR_GMDC_GTEST		(0x2)
  70
  71/* RSCFDnCFDGSTS / RSCFDnGSTS */
  72#define RCANFD_GSTS_GRAMINIT		BIT(3)
  73#define RCANFD_GSTS_GSLPSTS		BIT(2)
  74#define RCANFD_GSTS_GHLTSTS		BIT(1)
  75#define RCANFD_GSTS_GRSTSTS		BIT(0)
  76/* Non-operational status */
  77#define RCANFD_GSTS_GNOPM		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
  78
  79/* RSCFDnCFDGERFL / RSCFDnGERFL */
  80#define RCANFD_GERFL_EEF1		BIT(17)
  81#define RCANFD_GERFL_EEF0		BIT(16)
  82#define RCANFD_GERFL_CMPOF		BIT(3)	/* CAN FD only */
  83#define RCANFD_GERFL_THLES		BIT(2)
  84#define RCANFD_GERFL_MES		BIT(1)
  85#define RCANFD_GERFL_DEF		BIT(0)
  86
  87#define RCANFD_GERFL_ERR(gpriv, x)	((x) & (RCANFD_GERFL_EEF1 |\
  88					RCANFD_GERFL_EEF0 | RCANFD_GERFL_MES |\
  89					(gpriv->fdmode ?\
  90					 RCANFD_GERFL_CMPOF : 0)))
 
  91
  92/* AFL Rx rules registers */
  93
  94/* RSCFDnCFDGAFLCFG0 / RSCFDnGAFLCFG0 */
  95#define RCANFD_GAFLCFG_SETRNC(n, x)	(((x) & 0xff) << (24 - n * 8))
  96#define RCANFD_GAFLCFG_GETRNC(n, x)	(((x) >> (24 - n * 8)) & 0xff)
 
 
 
 
 
  97
  98/* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
  99#define RCANFD_GAFLECTR_AFLDAE		BIT(8)
 100#define RCANFD_GAFLECTR_AFLPN(x)	((x) & 0x1f)
 101
 102/* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
 103#define RCANFD_GAFLID_GAFLLB		BIT(29)
 104
 105/* RSCFDnCFDGAFLP1_j / RSCFDnGAFLP1_j */
 106#define RCANFD_GAFLP1_GAFLFDP(x)	(1 << (x))
 107
 108/* Channel register bits */
 109
 110/* RSCFDnCmCFG - Classical CAN only */
 111#define RCANFD_CFG_SJW(x)		(((x) & 0x3) << 24)
 112#define RCANFD_CFG_TSEG2(x)		(((x) & 0x7) << 20)
 113#define RCANFD_CFG_TSEG1(x)		(((x) & 0xf) << 16)
 114#define RCANFD_CFG_BRP(x)		(((x) & 0x3ff) << 0)
 115
 116/* RSCFDnCFDCmNCFG - CAN FD only */
 117#define RCANFD_NCFG_NTSEG2(x)		(((x) & 0x1f) << 24)
 118#define RCANFD_NCFG_NTSEG1(x)		(((x) & 0x7f) << 16)
 119#define RCANFD_NCFG_NSJW(x)		(((x) & 0x1f) << 11)
 
 
 
 
 
 
 120#define RCANFD_NCFG_NBRP(x)		(((x) & 0x3ff) << 0)
 121
 122/* RSCFDnCFDCmCTR / RSCFDnCmCTR */
 123#define RCANFD_CCTR_CTME		BIT(24)
 124#define RCANFD_CCTR_ERRD		BIT(23)
 125#define RCANFD_CCTR_BOM_MASK		(0x3 << 21)
 126#define RCANFD_CCTR_BOM_ISO		(0x0 << 21)
 127#define RCANFD_CCTR_BOM_BENTRY		(0x1 << 21)
 128#define RCANFD_CCTR_BOM_BEND		(0x2 << 21)
 129#define RCANFD_CCTR_TDCVFIE		BIT(19)
 130#define RCANFD_CCTR_SOCOIE		BIT(18)
 131#define RCANFD_CCTR_EOCOIE		BIT(17)
 132#define RCANFD_CCTR_TAIE		BIT(16)
 133#define RCANFD_CCTR_ALIE		BIT(15)
 134#define RCANFD_CCTR_BLIE		BIT(14)
 135#define RCANFD_CCTR_OLIE		BIT(13)
 136#define RCANFD_CCTR_BORIE		BIT(12)
 137#define RCANFD_CCTR_BOEIE		BIT(11)
 138#define RCANFD_CCTR_EPIE		BIT(10)
 139#define RCANFD_CCTR_EWIE		BIT(9)
 140#define RCANFD_CCTR_BEIE		BIT(8)
 141#define RCANFD_CCTR_CSLPR		BIT(2)
 142#define RCANFD_CCTR_CHMDC_MASK		(0x3)
 143#define RCANFD_CCTR_CHDMC_COPM		(0x0)
 144#define RCANFD_CCTR_CHDMC_CRESET	(0x1)
 145#define RCANFD_CCTR_CHDMC_CHLT		(0x2)
 146
 147/* RSCFDnCFDCmSTS / RSCFDnCmSTS */
 148#define RCANFD_CSTS_COMSTS		BIT(7)
 149#define RCANFD_CSTS_RECSTS		BIT(6)
 150#define RCANFD_CSTS_TRMSTS		BIT(5)
 151#define RCANFD_CSTS_BOSTS		BIT(4)
 152#define RCANFD_CSTS_EPSTS		BIT(3)
 153#define RCANFD_CSTS_SLPSTS		BIT(2)
 154#define RCANFD_CSTS_HLTSTS		BIT(1)
 155#define RCANFD_CSTS_CRSTSTS		BIT(0)
 156
 157#define RCANFD_CSTS_TECCNT(x)		(((x) >> 24) & 0xff)
 158#define RCANFD_CSTS_RECCNT(x)		(((x) >> 16) & 0xff)
 159
 160/* RSCFDnCFDCmERFL / RSCFDnCmERFL */
 161#define RCANFD_CERFL_ADERR		BIT(14)
 162#define RCANFD_CERFL_B0ERR		BIT(13)
 163#define RCANFD_CERFL_B1ERR		BIT(12)
 164#define RCANFD_CERFL_CERR		BIT(11)
 165#define RCANFD_CERFL_AERR		BIT(10)
 166#define RCANFD_CERFL_FERR		BIT(9)
 167#define RCANFD_CERFL_SERR		BIT(8)
 168#define RCANFD_CERFL_ALF		BIT(7)
 169#define RCANFD_CERFL_BLF		BIT(6)
 170#define RCANFD_CERFL_OVLF		BIT(5)
 171#define RCANFD_CERFL_BORF		BIT(4)
 172#define RCANFD_CERFL_BOEF		BIT(3)
 173#define RCANFD_CERFL_EPF		BIT(2)
 174#define RCANFD_CERFL_EWF		BIT(1)
 175#define RCANFD_CERFL_BEF		BIT(0)
 176
 177#define RCANFD_CERFL_ERR(x)		((x) & (0x7fff)) /* above bits 14:0 */
 178
 179/* RSCFDnCFDCmDCFG */
 180#define RCANFD_DCFG_DSJW(x)		(((x) & 0x7) << 24)
 181#define RCANFD_DCFG_DTSEG2(x)		(((x) & 0x7) << 20)
 182#define RCANFD_DCFG_DTSEG1(x)		(((x) & 0xf) << 16)
 
 
 
 
 
 183#define RCANFD_DCFG_DBRP(x)		(((x) & 0xff) << 0)
 184
 185/* RSCFDnCFDCmFDCFG */
 
 
 186#define RCANFD_FDCFG_TDCE		BIT(9)
 187#define RCANFD_FDCFG_TDCOC		BIT(8)
 188#define RCANFD_FDCFG_TDCO(x)		(((x) & 0x7f) >> 16)
 189
 190/* RSCFDnCFDRFCCx */
 191#define RCANFD_RFCC_RFIM		BIT(12)
 192#define RCANFD_RFCC_RFDC(x)		(((x) & 0x7) << 8)
 193#define RCANFD_RFCC_RFPLS(x)		(((x) & 0x7) << 4)
 194#define RCANFD_RFCC_RFIE		BIT(1)
 195#define RCANFD_RFCC_RFE			BIT(0)
 196
 197/* RSCFDnCFDRFSTSx */
 198#define RCANFD_RFSTS_RFIF		BIT(3)
 199#define RCANFD_RFSTS_RFMLT		BIT(2)
 200#define RCANFD_RFSTS_RFFLL		BIT(1)
 201#define RCANFD_RFSTS_RFEMP		BIT(0)
 202
 203/* RSCFDnCFDRFIDx */
 204#define RCANFD_RFID_RFIDE		BIT(31)
 205#define RCANFD_RFID_RFRTR		BIT(30)
 206
 207/* RSCFDnCFDRFPTRx */
 208#define RCANFD_RFPTR_RFDLC(x)		(((x) >> 28) & 0xf)
 209#define RCANFD_RFPTR_RFPTR(x)		(((x) >> 16) & 0xfff)
 210#define RCANFD_RFPTR_RFTS(x)		(((x) >> 0) & 0xffff)
 211
 212/* RSCFDnCFDRFFDSTSx */
 213#define RCANFD_RFFDSTS_RFFDF		BIT(2)
 214#define RCANFD_RFFDSTS_RFBRS		BIT(1)
 215#define RCANFD_RFFDSTS_RFESI		BIT(0)
 216
 217/* Common FIFO bits */
 218
 219/* RSCFDnCFDCFCCk */
 220#define RCANFD_CFCC_CFTML(x)		(((x) & 0xf) << 20)
 221#define RCANFD_CFCC_CFM(x)		(((x) & 0x3) << 16)
 222#define RCANFD_CFCC_CFIM		BIT(12)
 223#define RCANFD_CFCC_CFDC(x)		(((x) & 0x7) << 8)
 224#define RCANFD_CFCC_CFPLS(x)		(((x) & 0x7) << 4)
 225#define RCANFD_CFCC_CFTXIE		BIT(2)
 226#define RCANFD_CFCC_CFE			BIT(0)
 227
 228/* RSCFDnCFDCFSTSk */
 229#define RCANFD_CFSTS_CFMC(x)		(((x) >> 8) & 0xff)
 230#define RCANFD_CFSTS_CFTXIF		BIT(4)
 231#define RCANFD_CFSTS_CFMLT		BIT(2)
 232#define RCANFD_CFSTS_CFFLL		BIT(1)
 233#define RCANFD_CFSTS_CFEMP		BIT(0)
 234
 235/* RSCFDnCFDCFIDk */
 236#define RCANFD_CFID_CFIDE		BIT(31)
 237#define RCANFD_CFID_CFRTR		BIT(30)
 238#define RCANFD_CFID_CFID_MASK(x)	((x) & 0x1fffffff)
 239
 240/* RSCFDnCFDCFPTRk */
 241#define RCANFD_CFPTR_CFDLC(x)		(((x) & 0xf) << 28)
 242#define RCANFD_CFPTR_CFPTR(x)		(((x) & 0xfff) << 16)
 243#define RCANFD_CFPTR_CFTS(x)		(((x) & 0xff) << 0)
 244
 245/* RSCFDnCFDCFFDCSTSk */
 246#define RCANFD_CFFDCSTS_CFFDF		BIT(2)
 247#define RCANFD_CFFDCSTS_CFBRS		BIT(1)
 248#define RCANFD_CFFDCSTS_CFESI		BIT(0)
 249
 250/* This controller supports either Classical CAN only mode or CAN FD only mode.
 251 * These modes are supported in two separate set of register maps & names.
 252 * However, some of the register offsets are common for both modes. Those
 253 * offsets are listed below as Common registers.
 254 *
 255 * The CAN FD only mode specific registers & Classical CAN only mode specific
 256 * registers are listed separately. Their register names starts with
 257 * RCANFD_F_xxx & RCANFD_C_xxx respectively.
 258 */
 259
 260/* Common registers */
 261
 262/* RSCFDnCFDCmNCFG / RSCFDnCmCFG */
 263#define RCANFD_CCFG(m)			(0x0000 + (0x10 * (m)))
 264/* RSCFDnCFDCmCTR / RSCFDnCmCTR */
 265#define RCANFD_CCTR(m)			(0x0004 + (0x10 * (m)))
 266/* RSCFDnCFDCmSTS / RSCFDnCmSTS */
 267#define RCANFD_CSTS(m)			(0x0008 + (0x10 * (m)))
 268/* RSCFDnCFDCmERFL / RSCFDnCmERFL */
 269#define RCANFD_CERFL(m)			(0x000C + (0x10 * (m)))
 270
 271/* RSCFDnCFDGCFG / RSCFDnGCFG */
 272#define RCANFD_GCFG			(0x0084)
 273/* RSCFDnCFDGCTR / RSCFDnGCTR */
 274#define RCANFD_GCTR			(0x0088)
 275/* RSCFDnCFDGCTS / RSCFDnGCTS */
 276#define RCANFD_GSTS			(0x008c)
 277/* RSCFDnCFDGERFL / RSCFDnGERFL */
 278#define RCANFD_GERFL			(0x0090)
 279/* RSCFDnCFDGTSC / RSCFDnGTSC */
 280#define RCANFD_GTSC			(0x0094)
 281/* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
 282#define RCANFD_GAFLECTR			(0x0098)
 283/* RSCFDnCFDGAFLCFG0 / RSCFDnGAFLCFG0 */
 284#define RCANFD_GAFLCFG0			(0x009c)
 285/* RSCFDnCFDGAFLCFG1 / RSCFDnGAFLCFG1 */
 286#define RCANFD_GAFLCFG1			(0x00a0)
 287/* RSCFDnCFDRMNB / RSCFDnRMNB */
 288#define RCANFD_RMNB			(0x00a4)
 289/* RSCFDnCFDRMND / RSCFDnRMND */
 290#define RCANFD_RMND(y)			(0x00a8 + (0x04 * (y)))
 291
 292/* RSCFDnCFDRFCCx / RSCFDnRFCCx */
 293#define RCANFD_RFCC(x)			(0x00b8 + (0x04 * (x)))
 294/* RSCFDnCFDRFSTSx / RSCFDnRFSTSx */
 295#define RCANFD_RFSTS(x)			(0x00d8 + (0x04 * (x)))
 296/* RSCFDnCFDRFPCTRx / RSCFDnRFPCTRx */
 297#define RCANFD_RFPCTR(x)		(0x00f8 + (0x04 * (x)))
 298
 299/* Common FIFO Control registers */
 300
 301/* RSCFDnCFDCFCCx / RSCFDnCFCCx */
 302#define RCANFD_CFCC(ch, idx)		(0x0118 + (0x0c * (ch)) + \
 303					 (0x04 * (idx)))
 304/* RSCFDnCFDCFSTSx / RSCFDnCFSTSx */
 305#define RCANFD_CFSTS(ch, idx)		(0x0178 + (0x0c * (ch)) + \
 306					 (0x04 * (idx)))
 307/* RSCFDnCFDCFPCTRx / RSCFDnCFPCTRx */
 308#define RCANFD_CFPCTR(ch, idx)		(0x01d8 + (0x0c * (ch)) + \
 309					 (0x04 * (idx)))
 310
 311/* RSCFDnCFDFESTS / RSCFDnFESTS */
 312#define RCANFD_FESTS			(0x0238)
 313/* RSCFDnCFDFFSTS / RSCFDnFFSTS */
 314#define RCANFD_FFSTS			(0x023c)
 315/* RSCFDnCFDFMSTS / RSCFDnFMSTS */
 316#define RCANFD_FMSTS			(0x0240)
 317/* RSCFDnCFDRFISTS / RSCFDnRFISTS */
 318#define RCANFD_RFISTS			(0x0244)
 319/* RSCFDnCFDCFRISTS / RSCFDnCFRISTS */
 320#define RCANFD_CFRISTS			(0x0248)
 321/* RSCFDnCFDCFTISTS / RSCFDnCFTISTS */
 322#define RCANFD_CFTISTS			(0x024c)
 323
 324/* RSCFDnCFDTMCp / RSCFDnTMCp */
 325#define RCANFD_TMC(p)			(0x0250 + (0x01 * (p)))
 326/* RSCFDnCFDTMSTSp / RSCFDnTMSTSp */
 327#define RCANFD_TMSTS(p)			(0x02d0 + (0x01 * (p)))
 328
 329/* RSCFDnCFDTMTRSTSp / RSCFDnTMTRSTSp */
 330#define RCANFD_TMTRSTS(y)		(0x0350 + (0x04 * (y)))
 331/* RSCFDnCFDTMTARSTSp / RSCFDnTMTARSTSp */
 332#define RCANFD_TMTARSTS(y)		(0x0360 + (0x04 * (y)))
 333/* RSCFDnCFDTMTCSTSp / RSCFDnTMTCSTSp */
 334#define RCANFD_TMTCSTS(y)		(0x0370 + (0x04 * (y)))
 335/* RSCFDnCFDTMTASTSp / RSCFDnTMTASTSp */
 336#define RCANFD_TMTASTS(y)		(0x0380 + (0x04 * (y)))
 337/* RSCFDnCFDTMIECy / RSCFDnTMIECy */
 338#define RCANFD_TMIEC(y)			(0x0390 + (0x04 * (y)))
 339
 340/* RSCFDnCFDTXQCCm / RSCFDnTXQCCm */
 341#define RCANFD_TXQCC(m)			(0x03a0 + (0x04 * (m)))
 342/* RSCFDnCFDTXQSTSm / RSCFDnTXQSTSm */
 343#define RCANFD_TXQSTS(m)		(0x03c0 + (0x04 * (m)))
 344/* RSCFDnCFDTXQPCTRm / RSCFDnTXQPCTRm */
 345#define RCANFD_TXQPCTR(m)		(0x03e0 + (0x04 * (m)))
 346
 347/* RSCFDnCFDTHLCCm / RSCFDnTHLCCm */
 348#define RCANFD_THLCC(m)			(0x0400 + (0x04 * (m)))
 349/* RSCFDnCFDTHLSTSm / RSCFDnTHLSTSm */
 350#define RCANFD_THLSTS(m)		(0x0420 + (0x04 * (m)))
 351/* RSCFDnCFDTHLPCTRm / RSCFDnTHLPCTRm */
 352#define RCANFD_THLPCTR(m)		(0x0440 + (0x04 * (m)))
 353
 354/* RSCFDnCFDGTINTSTS0 / RSCFDnGTINTSTS0 */
 355#define RCANFD_GTINTSTS0		(0x0460)
 356/* RSCFDnCFDGTINTSTS1 / RSCFDnGTINTSTS1 */
 357#define RCANFD_GTINTSTS1		(0x0464)
 358/* RSCFDnCFDGTSTCFG / RSCFDnGTSTCFG */
 359#define RCANFD_GTSTCFG			(0x0468)
 360/* RSCFDnCFDGTSTCTR / RSCFDnGTSTCTR */
 361#define RCANFD_GTSTCTR			(0x046c)
 362/* RSCFDnCFDGLOCKK / RSCFDnGLOCKK */
 363#define RCANFD_GLOCKK			(0x047c)
 364/* RSCFDnCFDGRMCFG */
 365#define RCANFD_GRMCFG			(0x04fc)
 366
 367/* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
 368#define RCANFD_GAFLID(offset, j)	((offset) + (0x10 * (j)))
 369/* RSCFDnCFDGAFLMj / RSCFDnGAFLMj */
 370#define RCANFD_GAFLM(offset, j)		((offset) + 0x04 + (0x10 * (j)))
 371/* RSCFDnCFDGAFLP0j / RSCFDnGAFLP0j */
 372#define RCANFD_GAFLP0(offset, j)	((offset) + 0x08 + (0x10 * (j)))
 373/* RSCFDnCFDGAFLP1j / RSCFDnGAFLP1j */
 374#define RCANFD_GAFLP1(offset, j)	((offset) + 0x0c + (0x10 * (j)))
 375
 376/* Classical CAN only mode register map */
 377
 378/* RSCFDnGAFLXXXj offset */
 379#define RCANFD_C_GAFL_OFFSET		(0x0500)
 380
 381/* RSCFDnRMXXXq -> RCANFD_C_RMXXX(q) */
 382#define RCANFD_C_RMID(q)		(0x0600 + (0x10 * (q)))
 383#define RCANFD_C_RMPTR(q)		(0x0604 + (0x10 * (q)))
 384#define RCANFD_C_RMDF0(q)		(0x0608 + (0x10 * (q)))
 385#define RCANFD_C_RMDF1(q)		(0x060c + (0x10 * (q)))
 386
 387/* RSCFDnRFXXx -> RCANFD_C_RFXX(x) */
 388#define RCANFD_C_RFOFFSET		(0x0e00)
 389#define RCANFD_C_RFID(x)		(RCANFD_C_RFOFFSET + (0x10 * (x)))
 390#define RCANFD_C_RFPTR(x)		(RCANFD_C_RFOFFSET + 0x04 + \
 391					 (0x10 * (x)))
 392#define RCANFD_C_RFDF(x, df)		(RCANFD_C_RFOFFSET + 0x08 + \
 393					 (0x10 * (x)) + (0x04 * (df)))
 394
 395/* RSCFDnCFXXk -> RCANFD_C_CFXX(ch, k) */
 396#define RCANFD_C_CFOFFSET		(0x0e80)
 397#define RCANFD_C_CFID(ch, idx)		(RCANFD_C_CFOFFSET + (0x30 * (ch)) + \
 398					 (0x10 * (idx)))
 399#define RCANFD_C_CFPTR(ch, idx)		(RCANFD_C_CFOFFSET + 0x04 + \
 400					 (0x30 * (ch)) + (0x10 * (idx)))
 401#define RCANFD_C_CFDF(ch, idx, df)	(RCANFD_C_CFOFFSET + 0x08 + \
 402					 (0x30 * (ch)) + (0x10 * (idx)) + \
 403					 (0x04 * (df)))
 
 
 404
 405/* RSCFDnTMXXp -> RCANFD_C_TMXX(p) */
 406#define RCANFD_C_TMID(p)		(0x1000 + (0x10 * (p)))
 407#define RCANFD_C_TMPTR(p)		(0x1004 + (0x10 * (p)))
 408#define RCANFD_C_TMDF0(p)		(0x1008 + (0x10 * (p)))
 409#define RCANFD_C_TMDF1(p)		(0x100c + (0x10 * (p)))
 410
 411/* RSCFDnTHLACCm */
 412#define RCANFD_C_THLACC(m)		(0x1800 + (0x04 * (m)))
 413/* RSCFDnRPGACCr */
 414#define RCANFD_C_RPGACC(r)		(0x1900 + (0x04 * (r)))
 415
 416/* CAN FD mode specific regsiter map */
 
 
 
 
 
 
 417
 418/* RSCFDnCFDCmXXX -> RCANFD_F_XXX(m) */
 419#define RCANFD_F_DCFG(m)		(0x0500 + (0x20 * (m)))
 420#define RCANFD_F_CFDCFG(m)		(0x0504 + (0x20 * (m)))
 421#define RCANFD_F_CFDCTR(m)		(0x0508 + (0x20 * (m)))
 422#define RCANFD_F_CFDSTS(m)		(0x050c + (0x20 * (m)))
 423#define RCANFD_F_CFDCRC(m)		(0x0510 + (0x20 * (m)))
 424
 425/* RSCFDnCFDGAFLXXXj offset */
 426#define RCANFD_F_GAFL_OFFSET		(0x1000)
 427
 428/* RSCFDnCFDRMXXXq -> RCANFD_F_RMXXX(q) */
 429#define RCANFD_F_RMID(q)		(0x2000 + (0x20 * (q)))
 430#define RCANFD_F_RMPTR(q)		(0x2004 + (0x20 * (q)))
 431#define RCANFD_F_RMFDSTS(q)		(0x2008 + (0x20 * (q)))
 432#define RCANFD_F_RMDF(q, b)		(0x200c + (0x04 * (b)) + (0x20 * (q)))
 433
 434/* RSCFDnCFDRFXXx -> RCANFD_F_RFXX(x) */
 435#define RCANFD_F_RFOFFSET		(0x3000)
 436#define RCANFD_F_RFID(x)		(RCANFD_F_RFOFFSET + (0x80 * (x)))
 437#define RCANFD_F_RFPTR(x)		(RCANFD_F_RFOFFSET + 0x04 + \
 438					 (0x80 * (x)))
 439#define RCANFD_F_RFFDSTS(x)		(RCANFD_F_RFOFFSET + 0x08 + \
 440					 (0x80 * (x)))
 441#define RCANFD_F_RFDF(x, df)		(RCANFD_F_RFOFFSET + 0x0c + \
 442					 (0x80 * (x)) + (0x04 * (df)))
 443
 444/* RSCFDnCFDCFXXk -> RCANFD_F_CFXX(ch, k) */
 445#define RCANFD_F_CFOFFSET		(0x3400)
 446#define RCANFD_F_CFID(ch, idx)		(RCANFD_F_CFOFFSET + (0x180 * (ch)) + \
 447					 (0x80 * (idx)))
 448#define RCANFD_F_CFPTR(ch, idx)		(RCANFD_F_CFOFFSET + 0x04 + \
 449					 (0x180 * (ch)) + (0x80 * (idx)))
 450#define RCANFD_F_CFFDCSTS(ch, idx)	(RCANFD_F_CFOFFSET + 0x08 + \
 451					 (0x180 * (ch)) + (0x80 * (idx)))
 452#define RCANFD_F_CFDF(ch, idx, df)	(RCANFD_F_CFOFFSET + 0x0c + \
 453					 (0x180 * (ch)) + (0x80 * (idx)) + \
 454					 (0x04 * (df)))
 
 
 
 
 455
 456/* RSCFDnCFDTMXXp -> RCANFD_F_TMXX(p) */
 457#define RCANFD_F_TMID(p)		(0x4000 + (0x20 * (p)))
 458#define RCANFD_F_TMPTR(p)		(0x4004 + (0x20 * (p)))
 459#define RCANFD_F_TMFDCTR(p)		(0x4008 + (0x20 * (p)))
 460#define RCANFD_F_TMDF(p, b)		(0x400c + (0x20 * (p)) + (0x04 * (b)))
 461
 462/* RSCFDnCFDTHLACCm */
 463#define RCANFD_F_THLACC(m)		(0x6000 + (0x04 * (m)))
 464/* RSCFDnCFDRPGACCr */
 465#define RCANFD_F_RPGACC(r)		(0x6400 + (0x04 * (r)))
 466
 467/* Constants */
 468#define RCANFD_FIFO_DEPTH		8	/* Tx FIFO depth */
 469#define RCANFD_NAPI_WEIGHT		8	/* Rx poll quota */
 470
 471#define RCANFD_NUM_CHANNELS		2	/* Two channels max */
 472#define RCANFD_CHANNELS_MASK		BIT((RCANFD_NUM_CHANNELS) - 1)
 473
 474#define RCANFD_GAFL_PAGENUM(entry)	((entry) / 16)
 475#define RCANFD_CHANNEL_NUMRULES		1	/* only one rule per channel */
 476
 477/* Rx FIFO is a global resource of the controller. There are 8 such FIFOs
 478 * available. Each channel gets a dedicated Rx FIFO (i.e.) the channel
 479 * number is added to RFFIFO index.
 480 */
 481#define RCANFD_RFFIFO_IDX		0
 482
 483/* Tx/Rx or Common FIFO is a per channel resource. Each channel has 3 Common
 484 * FIFOs dedicated to them. Use the first (index 0) FIFO out of the 3 for Tx.
 485 */
 486#define RCANFD_CFFIFO_IDX		0
 487
 488/* fCAN clock select register settings */
 489enum rcar_canfd_fcanclk {
 490	RCANFD_CANFDCLK = 0,		/* CANFD clock */
 491	RCANFD_EXTCLK,			/* Externally input clock */
 492};
 493
 494struct rcar_canfd_global;
 495
 
 
 
 
 
 
 
 
 496/* Channel priv data */
 497struct rcar_canfd_channel {
 498	struct can_priv can;			/* Must be the first member */
 499	struct net_device *ndev;
 500	struct rcar_canfd_global *gpriv;	/* Controller reference */
 501	void __iomem *base;			/* Register base address */
 502	struct napi_struct napi;
 503	u8  tx_len[RCANFD_FIFO_DEPTH];		/* For net stats */
 504	u32 tx_head;				/* Incremented on xmit */
 505	u32 tx_tail;				/* Incremented on xmit done */
 506	u32 channel;				/* Channel number */
 507	spinlock_t tx_lock;			/* To protect tx path */
 508};
 509
 510/* Global priv data */
 511struct rcar_canfd_global {
 512	struct rcar_canfd_channel *ch[RCANFD_NUM_CHANNELS];
 513	void __iomem *base;		/* Register base address */
 514	struct platform_device *pdev;	/* Respective platform device */
 515	struct clk *clkp;		/* Peripheral clock */
 516	struct clk *can_clk;		/* fCAN clock */
 517	enum rcar_canfd_fcanclk fcan;	/* CANFD or Ext clock */
 518	unsigned long channels_mask;	/* Enabled channels mask */
 519	bool fdmode;			/* CAN FD or Classical CAN only mode */
 
 
 
 520};
 521
 522/* CAN FD mode nominal rate constants */
 523static const struct can_bittiming_const rcar_canfd_nom_bittiming_const = {
 524	.name = RCANFD_DRV_NAME,
 525	.tseg1_min = 2,
 526	.tseg1_max = 128,
 527	.tseg2_min = 2,
 528	.tseg2_max = 32,
 529	.sjw_max = 32,
 530	.brp_min = 1,
 531	.brp_max = 1024,
 532	.brp_inc = 1,
 533};
 534
 535/* CAN FD mode data rate constants */
 536static const struct can_bittiming_const rcar_canfd_data_bittiming_const = {
 537	.name = RCANFD_DRV_NAME,
 538	.tseg1_min = 2,
 539	.tseg1_max = 16,
 540	.tseg2_min = 2,
 541	.tseg2_max = 8,
 542	.sjw_max = 8,
 543	.brp_min = 1,
 544	.brp_max = 256,
 545	.brp_inc = 1,
 546};
 547
 548/* Classical CAN mode bitrate constants */
 549static const struct can_bittiming_const rcar_canfd_bittiming_const = {
 550	.name = RCANFD_DRV_NAME,
 551	.tseg1_min = 4,
 552	.tseg1_max = 16,
 553	.tseg2_min = 2,
 554	.tseg2_max = 8,
 555	.sjw_max = 4,
 556	.brp_min = 1,
 557	.brp_max = 1024,
 558	.brp_inc = 1,
 559};
 560
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 561/* Helper functions */
 
 
 
 
 
 
 
 
 
 
 
 562static inline void rcar_canfd_update(u32 mask, u32 val, u32 __iomem *reg)
 563{
 564	u32 data = readl(reg);
 565
 566	data &= ~mask;
 567	data |= (val & mask);
 568	writel(data, reg);
 569}
 570
 571static inline u32 rcar_canfd_read(void __iomem *base, u32 offset)
 572{
 573	return readl(base + (offset));
 574}
 575
 576static inline void rcar_canfd_write(void __iomem *base, u32 offset, u32 val)
 577{
 578	writel(val, base + (offset));
 579}
 580
 581static void rcar_canfd_set_bit(void __iomem *base, u32 reg, u32 val)
 582{
 583	rcar_canfd_update(val, val, base + (reg));
 584}
 585
 586static void rcar_canfd_clear_bit(void __iomem *base, u32 reg, u32 val)
 587{
 588	rcar_canfd_update(val, 0, base + (reg));
 589}
 590
 591static void rcar_canfd_update_bit(void __iomem *base, u32 reg,
 592				  u32 mask, u32 val)
 593{
 594	rcar_canfd_update(mask, val, base + (reg));
 595}
 596
 597static void rcar_canfd_get_data(struct rcar_canfd_channel *priv,
 598				struct canfd_frame *cf, u32 off)
 599{
 600	u32 i, lwords;
 601
 602	lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
 603	for (i = 0; i < lwords; i++)
 604		*((u32 *)cf->data + i) =
 605			rcar_canfd_read(priv->base, off + (i * sizeof(u32)));
 606}
 607
 608static void rcar_canfd_put_data(struct rcar_canfd_channel *priv,
 609				struct canfd_frame *cf, u32 off)
 610{
 611	u32 i, lwords;
 612
 613	lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
 614	for (i = 0; i < lwords; i++)
 615		rcar_canfd_write(priv->base, off + (i * sizeof(u32)),
 616				 *((u32 *)cf->data + i));
 617}
 618
 619static void rcar_canfd_tx_failure_cleanup(struct net_device *ndev)
 620{
 621	u32 i;
 622
 623	for (i = 0; i < RCANFD_FIFO_DEPTH; i++)
 624		can_free_echo_skb(ndev, i);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 625}
 626
 627static int rcar_canfd_reset_controller(struct rcar_canfd_global *gpriv)
 628{
 629	u32 sts, ch;
 630	int err;
 631
 632	/* Check RAMINIT flag as CAN RAM initialization takes place
 633	 * after the MCU reset
 634	 */
 635	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
 636				 !(sts & RCANFD_GSTS_GRAMINIT), 2, 500000);
 637	if (err) {
 638		dev_dbg(&gpriv->pdev->dev, "global raminit failed\n");
 639		return err;
 640	}
 641
 642	/* Transition to Global Reset mode */
 643	rcar_canfd_clear_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
 644	rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR,
 645			      RCANFD_GCTR_GMDC_MASK, RCANFD_GCTR_GMDC_GRESET);
 646
 647	/* Ensure Global reset mode */
 648	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
 649				 (sts & RCANFD_GSTS_GRSTSTS), 2, 500000);
 650	if (err) {
 651		dev_dbg(&gpriv->pdev->dev, "global reset failed\n");
 652		return err;
 653	}
 654
 655	/* Reset Global error flags */
 656	rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0x0);
 657
 658	/* Set the controller into appropriate mode */
 659	if (gpriv->fdmode)
 660		rcar_canfd_set_bit(gpriv->base, RCANFD_GRMCFG,
 661				   RCANFD_GRMCFG_RCMC);
 662	else
 663		rcar_canfd_clear_bit(gpriv->base, RCANFD_GRMCFG,
 664				     RCANFD_GRMCFG_RCMC);
 665
 666	/* Transition all Channels to reset mode */
 667	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
 668		rcar_canfd_clear_bit(gpriv->base,
 669				     RCANFD_CCTR(ch), RCANFD_CCTR_CSLPR);
 670
 671		rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
 672				      RCANFD_CCTR_CHMDC_MASK,
 673				      RCANFD_CCTR_CHDMC_CRESET);
 674
 675		/* Ensure Channel reset mode */
 676		err = readl_poll_timeout((gpriv->base + RCANFD_CSTS(ch)), sts,
 677					 (sts & RCANFD_CSTS_CRSTSTS),
 678					 2, 500000);
 679		if (err) {
 680			dev_dbg(&gpriv->pdev->dev,
 681				"channel %u reset failed\n", ch);
 682			return err;
 683		}
 684	}
 685	return 0;
 686}
 687
 688static void rcar_canfd_configure_controller(struct rcar_canfd_global *gpriv)
 689{
 690	u32 cfg, ch;
 691
 692	/* Global configuration settings */
 693
 694	/* ECC Error flag Enable */
 695	cfg = RCANFD_GCFG_EEFE;
 696
 697	if (gpriv->fdmode)
 698		/* Truncate payload to configured message size RFPLS */
 699		cfg |= RCANFD_GCFG_CMPOC;
 700
 701	/* Set External Clock if selected */
 702	if (gpriv->fcan != RCANFD_CANFDCLK)
 703		cfg |= RCANFD_GCFG_DCS;
 704
 705	rcar_canfd_set_bit(gpriv->base, RCANFD_GCFG, cfg);
 706
 707	/* Channel configuration settings */
 708	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
 709		rcar_canfd_set_bit(gpriv->base, RCANFD_CCTR(ch),
 710				   RCANFD_CCTR_ERRD);
 711		rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
 712				      RCANFD_CCTR_BOM_MASK,
 713				      RCANFD_CCTR_BOM_BENTRY);
 714	}
 715}
 716
 717static void rcar_canfd_configure_afl_rules(struct rcar_canfd_global *gpriv,
 718					   u32 ch)
 719{
 720	u32 cfg;
 721	int offset, start, page, num_rules = RCANFD_CHANNEL_NUMRULES;
 722	u32 ridx = ch + RCANFD_RFFIFO_IDX;
 723
 724	if (ch == 0) {
 725		start = 0; /* Channel 0 always starts from 0th rule */
 726	} else {
 727		/* Get number of Channel 0 rules and adjust */
 728		cfg = rcar_canfd_read(gpriv->base, RCANFD_GAFLCFG0);
 729		start = RCANFD_GAFLCFG_GETRNC(0, cfg);
 730	}
 731
 732	/* Enable write access to entry */
 733	page = RCANFD_GAFL_PAGENUM(start);
 734	rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLECTR,
 735			   (RCANFD_GAFLECTR_AFLPN(page) |
 736			    RCANFD_GAFLECTR_AFLDAE));
 737
 738	/* Write number of rules for channel */
 739	rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLCFG0,
 740			   RCANFD_GAFLCFG_SETRNC(ch, num_rules));
 741	if (gpriv->fdmode)
 
 
 742		offset = RCANFD_F_GAFL_OFFSET;
 743	else
 744		offset = RCANFD_C_GAFL_OFFSET;
 745
 746	/* Accept all IDs */
 747	rcar_canfd_write(gpriv->base, RCANFD_GAFLID(offset, start), 0);
 748	/* IDE or RTR is not considered for matching */
 749	rcar_canfd_write(gpriv->base, RCANFD_GAFLM(offset, start), 0);
 750	/* Any data length accepted */
 751	rcar_canfd_write(gpriv->base, RCANFD_GAFLP0(offset, start), 0);
 752	/* Place the msg in corresponding Rx FIFO entry */
 753	rcar_canfd_write(gpriv->base, RCANFD_GAFLP1(offset, start),
 754			 RCANFD_GAFLP1_GAFLFDP(ridx));
 755
 756	/* Disable write access to page */
 757	rcar_canfd_clear_bit(gpriv->base,
 758			     RCANFD_GAFLECTR, RCANFD_GAFLECTR_AFLDAE);
 759}
 760
 761static void rcar_canfd_configure_rx(struct rcar_canfd_global *gpriv, u32 ch)
 762{
 763	/* Rx FIFO is used for reception */
 764	u32 cfg;
 765	u16 rfdc, rfpls;
 766
 767	/* Select Rx FIFO based on channel */
 768	u32 ridx = ch + RCANFD_RFFIFO_IDX;
 769
 770	rfdc = 2;		/* b010 - 8 messages Rx FIFO depth */
 771	if (gpriv->fdmode)
 772		rfpls = 7;	/* b111 - Max 64 bytes payload */
 773	else
 774		rfpls = 0;	/* b000 - Max 8 bytes payload */
 775
 776	cfg = (RCANFD_RFCC_RFIM | RCANFD_RFCC_RFDC(rfdc) |
 777		RCANFD_RFCC_RFPLS(rfpls) | RCANFD_RFCC_RFIE);
 778	rcar_canfd_write(gpriv->base, RCANFD_RFCC(ridx), cfg);
 779}
 780
 781static void rcar_canfd_configure_tx(struct rcar_canfd_global *gpriv, u32 ch)
 782{
 783	/* Tx/Rx(Common) FIFO configured in Tx mode is
 784	 * used for transmission
 785	 *
 786	 * Each channel has 3 Common FIFO dedicated to them.
 787	 * Use the 1st (index 0) out of 3
 788	 */
 789	u32 cfg;
 790	u16 cftml, cfm, cfdc, cfpls;
 791
 792	cftml = 0;		/* 0th buffer */
 793	cfm = 1;		/* b01 - Transmit mode */
 794	cfdc = 2;		/* b010 - 8 messages Tx FIFO depth */
 795	if (gpriv->fdmode)
 796		cfpls = 7;	/* b111 - Max 64 bytes payload */
 797	else
 798		cfpls = 0;	/* b000 - Max 8 bytes payload */
 799
 800	cfg = (RCANFD_CFCC_CFTML(cftml) | RCANFD_CFCC_CFM(cfm) |
 801		RCANFD_CFCC_CFIM | RCANFD_CFCC_CFDC(cfdc) |
 802		RCANFD_CFCC_CFPLS(cfpls) | RCANFD_CFCC_CFTXIE);
 803	rcar_canfd_write(gpriv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX), cfg);
 804
 805	if (gpriv->fdmode)
 806		/* Clear FD mode specific control/status register */
 807		rcar_canfd_write(gpriv->base,
 808				 RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX), 0);
 809}
 810
 811static void rcar_canfd_enable_global_interrupts(struct rcar_canfd_global *gpriv)
 812{
 813	u32 ctr;
 814
 815	/* Clear any stray error interrupt flags */
 816	rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
 817
 818	/* Global interrupts setup */
 819	ctr = RCANFD_GCTR_MEIE;
 820	if (gpriv->fdmode)
 821		ctr |= RCANFD_GCTR_CFMPOFIE;
 822
 823	rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, ctr);
 824}
 825
 826static void rcar_canfd_disable_global_interrupts(struct rcar_canfd_global
 827						 *gpriv)
 828{
 829	/* Disable all interrupts */
 830	rcar_canfd_write(gpriv->base, RCANFD_GCTR, 0);
 831
 832	/* Clear any stray error interrupt flags */
 833	rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
 834}
 835
 836static void rcar_canfd_enable_channel_interrupts(struct rcar_canfd_channel
 837						 *priv)
 838{
 839	u32 ctr, ch = priv->channel;
 840
 841	/* Clear any stray error flags */
 842	rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
 843
 844	/* Channel interrupts setup */
 845	ctr = (RCANFD_CCTR_TAIE |
 846	       RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
 847	       RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
 848	       RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
 849	       RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
 850	rcar_canfd_set_bit(priv->base, RCANFD_CCTR(ch), ctr);
 851}
 852
 853static void rcar_canfd_disable_channel_interrupts(struct rcar_canfd_channel
 854						  *priv)
 855{
 856	u32 ctr, ch = priv->channel;
 857
 858	ctr = (RCANFD_CCTR_TAIE |
 859	       RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
 860	       RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
 861	       RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
 862	       RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
 863	rcar_canfd_clear_bit(priv->base, RCANFD_CCTR(ch), ctr);
 864
 865	/* Clear any stray error flags */
 866	rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
 867}
 868
 869static void rcar_canfd_global_error(struct net_device *ndev)
 870{
 871	struct rcar_canfd_channel *priv = netdev_priv(ndev);
 872	struct rcar_canfd_global *gpriv = priv->gpriv;
 873	struct net_device_stats *stats = &ndev->stats;
 874	u32 ch = priv->channel;
 875	u32 gerfl, sts;
 876	u32 ridx = ch + RCANFD_RFFIFO_IDX;
 877
 878	gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
 879	if ((gerfl & RCANFD_GERFL_EEF0) && (ch == 0)) {
 880		netdev_dbg(ndev, "Ch0: ECC Error flag\n");
 881		stats->tx_dropped++;
 882	}
 883	if ((gerfl & RCANFD_GERFL_EEF1) && (ch == 1)) {
 884		netdev_dbg(ndev, "Ch1: ECC Error flag\n");
 885		stats->tx_dropped++;
 886	}
 887	if (gerfl & RCANFD_GERFL_MES) {
 888		sts = rcar_canfd_read(priv->base,
 889				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
 890		if (sts & RCANFD_CFSTS_CFMLT) {
 891			netdev_dbg(ndev, "Tx Message Lost flag\n");
 892			stats->tx_dropped++;
 893			rcar_canfd_write(priv->base,
 894					 RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
 895					 sts & ~RCANFD_CFSTS_CFMLT);
 896		}
 897
 898		sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
 899		if (sts & RCANFD_RFSTS_RFMLT) {
 900			netdev_dbg(ndev, "Rx Message Lost flag\n");
 901			stats->rx_dropped++;
 902			rcar_canfd_write(priv->base, RCANFD_RFSTS(ridx),
 903					 sts & ~RCANFD_RFSTS_RFMLT);
 904		}
 905	}
 906	if (gpriv->fdmode && gerfl & RCANFD_GERFL_CMPOF) {
 907		/* Message Lost flag will be set for respective channel
 908		 * when this condition happens with counters and flags
 909		 * already updated.
 910		 */
 911		netdev_dbg(ndev, "global payload overflow interrupt\n");
 912	}
 913
 914	/* Clear all global error interrupts. Only affected channels bits
 915	 * get cleared
 916	 */
 917	rcar_canfd_write(priv->base, RCANFD_GERFL, 0);
 918}
 919
 920static void rcar_canfd_error(struct net_device *ndev, u32 cerfl,
 921			     u16 txerr, u16 rxerr)
 922{
 923	struct rcar_canfd_channel *priv = netdev_priv(ndev);
 924	struct net_device_stats *stats = &ndev->stats;
 925	struct can_frame *cf;
 926	struct sk_buff *skb;
 927	u32 ch = priv->channel;
 928
 929	netdev_dbg(ndev, "ch erfl %x txerr %u rxerr %u\n", cerfl, txerr, rxerr);
 930
 931	/* Propagate the error condition to the CAN stack */
 932	skb = alloc_can_err_skb(ndev, &cf);
 933	if (!skb) {
 934		stats->rx_dropped++;
 935		return;
 936	}
 937
 938	/* Channel error interrupts */
 939	if (cerfl & RCANFD_CERFL_BEF) {
 940		netdev_dbg(ndev, "Bus error\n");
 941		cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
 942		cf->data[2] = CAN_ERR_PROT_UNSPEC;
 943		priv->can.can_stats.bus_error++;
 944	}
 945	if (cerfl & RCANFD_CERFL_ADERR) {
 946		netdev_dbg(ndev, "ACK Delimiter Error\n");
 947		stats->tx_errors++;
 948		cf->data[3] |= CAN_ERR_PROT_LOC_ACK_DEL;
 949	}
 950	if (cerfl & RCANFD_CERFL_B0ERR) {
 951		netdev_dbg(ndev, "Bit Error (dominant)\n");
 952		stats->tx_errors++;
 953		cf->data[2] |= CAN_ERR_PROT_BIT0;
 954	}
 955	if (cerfl & RCANFD_CERFL_B1ERR) {
 956		netdev_dbg(ndev, "Bit Error (recessive)\n");
 957		stats->tx_errors++;
 958		cf->data[2] |= CAN_ERR_PROT_BIT1;
 959	}
 960	if (cerfl & RCANFD_CERFL_CERR) {
 961		netdev_dbg(ndev, "CRC Error\n");
 962		stats->rx_errors++;
 963		cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
 964	}
 965	if (cerfl & RCANFD_CERFL_AERR) {
 966		netdev_dbg(ndev, "ACK Error\n");
 967		stats->tx_errors++;
 968		cf->can_id |= CAN_ERR_ACK;
 969		cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
 970	}
 971	if (cerfl & RCANFD_CERFL_FERR) {
 972		netdev_dbg(ndev, "Form Error\n");
 973		stats->rx_errors++;
 974		cf->data[2] |= CAN_ERR_PROT_FORM;
 975	}
 976	if (cerfl & RCANFD_CERFL_SERR) {
 977		netdev_dbg(ndev, "Stuff Error\n");
 978		stats->rx_errors++;
 979		cf->data[2] |= CAN_ERR_PROT_STUFF;
 980	}
 981	if (cerfl & RCANFD_CERFL_ALF) {
 982		netdev_dbg(ndev, "Arbitration lost Error\n");
 983		priv->can.can_stats.arbitration_lost++;
 984		cf->can_id |= CAN_ERR_LOSTARB;
 985		cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC;
 986	}
 987	if (cerfl & RCANFD_CERFL_BLF) {
 988		netdev_dbg(ndev, "Bus Lock Error\n");
 989		stats->rx_errors++;
 990		cf->can_id |= CAN_ERR_BUSERROR;
 991	}
 992	if (cerfl & RCANFD_CERFL_EWF) {
 993		netdev_dbg(ndev, "Error warning interrupt\n");
 994		priv->can.state = CAN_STATE_ERROR_WARNING;
 995		priv->can.can_stats.error_warning++;
 996		cf->can_id |= CAN_ERR_CRTL;
 997		cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING :
 998			CAN_ERR_CRTL_RX_WARNING;
 999		cf->data[6] = txerr;
1000		cf->data[7] = rxerr;
1001	}
1002	if (cerfl & RCANFD_CERFL_EPF) {
1003		netdev_dbg(ndev, "Error passive interrupt\n");
1004		priv->can.state = CAN_STATE_ERROR_PASSIVE;
1005		priv->can.can_stats.error_passive++;
1006		cf->can_id |= CAN_ERR_CRTL;
1007		cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE :
1008			CAN_ERR_CRTL_RX_PASSIVE;
1009		cf->data[6] = txerr;
1010		cf->data[7] = rxerr;
1011	}
1012	if (cerfl & RCANFD_CERFL_BOEF) {
1013		netdev_dbg(ndev, "Bus-off entry interrupt\n");
1014		rcar_canfd_tx_failure_cleanup(ndev);
1015		priv->can.state = CAN_STATE_BUS_OFF;
1016		priv->can.can_stats.bus_off++;
1017		can_bus_off(ndev);
1018		cf->can_id |= CAN_ERR_BUSOFF;
1019	}
1020	if (cerfl & RCANFD_CERFL_OVLF) {
1021		netdev_dbg(ndev,
1022			   "Overload Frame Transmission error interrupt\n");
1023		stats->tx_errors++;
1024		cf->can_id |= CAN_ERR_PROT;
1025		cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
1026	}
1027
1028	/* Clear channel error interrupts that are handled */
1029	rcar_canfd_write(priv->base, RCANFD_CERFL(ch),
1030			 RCANFD_CERFL_ERR(~cerfl));
1031	stats->rx_packets++;
1032	stats->rx_bytes += cf->can_dlc;
1033	netif_rx(skb);
1034}
1035
1036static void rcar_canfd_tx_done(struct net_device *ndev)
1037{
1038	struct rcar_canfd_channel *priv = netdev_priv(ndev);
 
1039	struct net_device_stats *stats = &ndev->stats;
1040	u32 sts;
1041	unsigned long flags;
1042	u32 ch = priv->channel;
1043
1044	do {
1045		u8 unsent, sent;
1046
1047		sent = priv->tx_tail % RCANFD_FIFO_DEPTH;
1048		stats->tx_packets++;
1049		stats->tx_bytes += priv->tx_len[sent];
1050		priv->tx_len[sent] = 0;
1051		can_get_echo_skb(ndev, sent);
1052
1053		spin_lock_irqsave(&priv->tx_lock, flags);
1054		priv->tx_tail++;
1055		sts = rcar_canfd_read(priv->base,
1056				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
1057		unsent = RCANFD_CFSTS_CFMC(sts);
1058
1059		/* Wake producer only when there is room */
1060		if (unsent != RCANFD_FIFO_DEPTH)
1061			netif_wake_queue(ndev);
1062
1063		if (priv->tx_head - priv->tx_tail <= unsent) {
1064			spin_unlock_irqrestore(&priv->tx_lock, flags);
1065			break;
1066		}
1067		spin_unlock_irqrestore(&priv->tx_lock, flags);
1068
1069	} while (1);
1070
1071	/* Clear interrupt */
1072	rcar_canfd_write(priv->base, RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
1073			 sts & ~RCANFD_CFSTS_CFTXIF);
1074	can_led_event(ndev, CAN_LED_EVENT_TX);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1075}
1076
1077static irqreturn_t rcar_canfd_global_interrupt(int irq, void *dev_id)
1078{
1079	struct rcar_canfd_global *gpriv = dev_id;
1080	struct net_device *ndev;
1081	struct rcar_canfd_channel *priv;
1082	u32 sts, gerfl;
1083	u32 ch, ridx;
1084
1085	/* Global error interrupts still indicate a condition specific
1086	 * to a channel. RxFIFO interrupt is a global interrupt.
1087	 */
1088	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1089		priv = gpriv->ch[ch];
1090		ndev = priv->ndev;
1091		ridx = ch + RCANFD_RFFIFO_IDX;
1092
1093		/* Global error interrupts */
1094		gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
1095		if (unlikely(RCANFD_GERFL_ERR(gpriv, gerfl)))
1096			rcar_canfd_global_error(ndev);
1097
1098		/* Handle Rx interrupts */
1099		sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
1100		if (likely(sts & RCANFD_RFSTS_RFIF)) {
1101			if (napi_schedule_prep(&priv->napi)) {
1102				/* Disable Rx FIFO interrupts */
1103				rcar_canfd_clear_bit(priv->base,
1104						     RCANFD_RFCC(ridx),
1105						     RCANFD_RFCC_RFIE);
1106				__napi_schedule(&priv->napi);
1107			}
1108		}
1109	}
1110	return IRQ_HANDLED;
1111}
1112
1113static void rcar_canfd_state_change(struct net_device *ndev,
1114				    u16 txerr, u16 rxerr)
1115{
1116	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1117	struct net_device_stats *stats = &ndev->stats;
1118	enum can_state rx_state, tx_state, state = priv->can.state;
1119	struct can_frame *cf;
1120	struct sk_buff *skb;
1121
1122	/* Handle transition from error to normal states */
1123	if (txerr < 96 && rxerr < 96)
1124		state = CAN_STATE_ERROR_ACTIVE;
1125	else if (txerr < 128 && rxerr < 128)
1126		state = CAN_STATE_ERROR_WARNING;
1127
1128	if (state != priv->can.state) {
1129		netdev_dbg(ndev, "state: new %d, old %d: txerr %u, rxerr %u\n",
1130			   state, priv->can.state, txerr, rxerr);
1131		skb = alloc_can_err_skb(ndev, &cf);
1132		if (!skb) {
1133			stats->rx_dropped++;
1134			return;
1135		}
1136		tx_state = txerr >= rxerr ? state : 0;
1137		rx_state = txerr <= rxerr ? state : 0;
1138
1139		can_change_state(ndev, cf, tx_state, rx_state);
1140		stats->rx_packets++;
1141		stats->rx_bytes += cf->can_dlc;
1142		netif_rx(skb);
1143	}
1144}
1145
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1146static irqreturn_t rcar_canfd_channel_interrupt(int irq, void *dev_id)
1147{
1148	struct rcar_canfd_global *gpriv = dev_id;
1149	struct net_device *ndev;
1150	struct rcar_canfd_channel *priv;
1151	u32 sts, ch, cerfl;
1152	u16 txerr, rxerr;
1153
1154	/* Common FIFO is a per channel resource */
1155	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1156		priv = gpriv->ch[ch];
1157		ndev = priv->ndev;
1158
1159		/* Channel error interrupts */
1160		cerfl = rcar_canfd_read(priv->base, RCANFD_CERFL(ch));
1161		sts = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1162		txerr = RCANFD_CSTS_TECCNT(sts);
1163		rxerr = RCANFD_CSTS_RECCNT(sts);
1164		if (unlikely(RCANFD_CERFL_ERR(cerfl)))
1165			rcar_canfd_error(ndev, cerfl, txerr, rxerr);
1166
1167		/* Handle state change to lower states */
1168		if (unlikely((priv->can.state != CAN_STATE_ERROR_ACTIVE) &&
1169			     (priv->can.state != CAN_STATE_BUS_OFF)))
1170			rcar_canfd_state_change(ndev, txerr, rxerr);
1171
1172		/* Handle Tx interrupts */
1173		sts = rcar_canfd_read(priv->base,
1174				      RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
1175		if (likely(sts & RCANFD_CFSTS_CFTXIF))
1176			rcar_canfd_tx_done(ndev);
1177	}
 
1178	return IRQ_HANDLED;
1179}
1180
1181static void rcar_canfd_set_bittiming(struct net_device *dev)
1182{
1183	struct rcar_canfd_channel *priv = netdev_priv(dev);
 
1184	const struct can_bittiming *bt = &priv->can.bittiming;
1185	const struct can_bittiming *dbt = &priv->can.data_bittiming;
1186	u16 brp, sjw, tseg1, tseg2;
1187	u32 cfg;
1188	u32 ch = priv->channel;
1189
1190	/* Nominal bit timing settings */
1191	brp = bt->brp - 1;
1192	sjw = bt->sjw - 1;
1193	tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
1194	tseg2 = bt->phase_seg2 - 1;
1195
1196	if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1197		/* CAN FD only mode */
1198		cfg = (RCANFD_NCFG_NTSEG1(tseg1) | RCANFD_NCFG_NBRP(brp) |
1199		       RCANFD_NCFG_NSJW(sjw) | RCANFD_NCFG_NTSEG2(tseg2));
1200
1201		rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
1202		netdev_dbg(priv->ndev, "nrate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1203			   brp, sjw, tseg1, tseg2);
1204
1205		/* Data bit timing settings */
1206		brp = dbt->brp - 1;
1207		sjw = dbt->sjw - 1;
1208		tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
1209		tseg2 = dbt->phase_seg2 - 1;
1210
1211		cfg = (RCANFD_DCFG_DTSEG1(tseg1) | RCANFD_DCFG_DBRP(brp) |
1212		       RCANFD_DCFG_DSJW(sjw) | RCANFD_DCFG_DTSEG2(tseg2));
1213
1214		rcar_canfd_write(priv->base, RCANFD_F_DCFG(ch), cfg);
 
 
 
1215		netdev_dbg(priv->ndev, "drate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1216			   brp, sjw, tseg1, tseg2);
1217	} else {
1218		/* Classical CAN only mode */
1219		cfg = (RCANFD_CFG_TSEG1(tseg1) | RCANFD_CFG_BRP(brp) |
1220			RCANFD_CFG_SJW(sjw) | RCANFD_CFG_TSEG2(tseg2));
 
 
 
 
 
 
 
 
 
1221
1222		rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
1223		netdev_dbg(priv->ndev,
1224			   "rate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1225			   brp, sjw, tseg1, tseg2);
1226	}
1227}
1228
1229static int rcar_canfd_start(struct net_device *ndev)
1230{
1231	struct rcar_canfd_channel *priv = netdev_priv(ndev);
 
1232	int err = -EOPNOTSUPP;
1233	u32 sts, ch = priv->channel;
1234	u32 ridx = ch + RCANFD_RFFIFO_IDX;
1235
1236	rcar_canfd_set_bittiming(ndev);
1237
1238	rcar_canfd_enable_channel_interrupts(priv);
1239
1240	/* Set channel to Operational mode */
1241	rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1242			      RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_COPM);
1243
1244	/* Verify channel mode change */
1245	err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1246				 (sts & RCANFD_CSTS_COMSTS), 2, 500000);
1247	if (err) {
1248		netdev_err(ndev, "channel %u communication state failed\n", ch);
1249		goto fail_mode_change;
1250	}
1251
1252	/* Enable Common & Rx FIFO */
1253	rcar_canfd_set_bit(priv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX),
1254			   RCANFD_CFCC_CFE);
1255	rcar_canfd_set_bit(priv->base, RCANFD_RFCC(ridx), RCANFD_RFCC_RFE);
1256
1257	priv->can.state = CAN_STATE_ERROR_ACTIVE;
1258	return 0;
1259
1260fail_mode_change:
1261	rcar_canfd_disable_channel_interrupts(priv);
1262	return err;
1263}
1264
1265static int rcar_canfd_open(struct net_device *ndev)
1266{
1267	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1268	struct rcar_canfd_global *gpriv = priv->gpriv;
1269	int err;
1270
1271	/* Peripheral clock is already enabled in probe */
1272	err = clk_prepare_enable(gpriv->can_clk);
1273	if (err) {
1274		netdev_err(ndev, "failed to enable CAN clock, error %d\n", err);
1275		goto out_clock;
1276	}
1277
1278	err = open_candev(ndev);
1279	if (err) {
1280		netdev_err(ndev, "open_candev() failed, error %d\n", err);
1281		goto out_can_clock;
1282	}
1283
1284	napi_enable(&priv->napi);
1285	err = rcar_canfd_start(ndev);
1286	if (err)
1287		goto out_close;
1288	netif_start_queue(ndev);
1289	can_led_event(ndev, CAN_LED_EVENT_OPEN);
1290	return 0;
1291out_close:
1292	napi_disable(&priv->napi);
1293	close_candev(ndev);
1294out_can_clock:
1295	clk_disable_unprepare(gpriv->can_clk);
1296out_clock:
1297	return err;
1298}
1299
1300static void rcar_canfd_stop(struct net_device *ndev)
1301{
1302	struct rcar_canfd_channel *priv = netdev_priv(ndev);
 
1303	int err;
1304	u32 sts, ch = priv->channel;
1305	u32 ridx = ch + RCANFD_RFFIFO_IDX;
1306
1307	/* Transition to channel reset mode  */
1308	rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1309			      RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_CRESET);
1310
1311	/* Check Channel reset mode */
1312	err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1313				 (sts & RCANFD_CSTS_CRSTSTS), 2, 500000);
1314	if (err)
1315		netdev_err(ndev, "channel %u reset failed\n", ch);
1316
1317	rcar_canfd_disable_channel_interrupts(priv);
1318
1319	/* Disable Common & Rx FIFO */
1320	rcar_canfd_clear_bit(priv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX),
1321			     RCANFD_CFCC_CFE);
1322	rcar_canfd_clear_bit(priv->base, RCANFD_RFCC(ridx), RCANFD_RFCC_RFE);
1323
1324	/* Set the state as STOPPED */
1325	priv->can.state = CAN_STATE_STOPPED;
1326}
1327
1328static int rcar_canfd_close(struct net_device *ndev)
1329{
1330	struct rcar_canfd_channel *priv = netdev_priv(ndev);
1331	struct rcar_canfd_global *gpriv = priv->gpriv;
1332
1333	netif_stop_queue(ndev);
1334	rcar_canfd_stop(ndev);
1335	napi_disable(&priv->napi);
1336	clk_disable_unprepare(gpriv->can_clk);
1337	close_candev(ndev);
1338	can_led_event(ndev, CAN_LED_EVENT_STOP);
1339	return 0;
1340}
1341
1342static netdev_tx_t rcar_canfd_start_xmit(struct sk_buff *skb,
1343					 struct net_device *ndev)
1344{
1345	struct rcar_canfd_channel *priv = netdev_priv(ndev);
 
1346	struct canfd_frame *cf = (struct canfd_frame *)skb->data;
1347	u32 sts = 0, id, dlc;
1348	unsigned long flags;
1349	u32 ch = priv->channel;
1350
1351	if (can_dropped_invalid_skb(ndev, skb))
1352		return NETDEV_TX_OK;
1353
1354	if (cf->can_id & CAN_EFF_FLAG) {
1355		id = cf->can_id & CAN_EFF_MASK;
1356		id |= RCANFD_CFID_CFIDE;
1357	} else {
1358		id = cf->can_id & CAN_SFF_MASK;
1359	}
1360
1361	if (cf->can_id & CAN_RTR_FLAG)
1362		id |= RCANFD_CFID_CFRTR;
1363
1364	dlc = RCANFD_CFPTR_CFDLC(can_len2dlc(cf->len));
1365
1366	if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1367		rcar_canfd_write(priv->base,
1368				 RCANFD_F_CFID(ch, RCANFD_CFFIFO_IDX), id);
1369		rcar_canfd_write(priv->base,
1370				 RCANFD_F_CFPTR(ch, RCANFD_CFFIFO_IDX), dlc);
1371
1372		if (can_is_canfd_skb(skb)) {
1373			/* CAN FD frame format */
1374			sts |= RCANFD_CFFDCSTS_CFFDF;
1375			if (cf->flags & CANFD_BRS)
1376				sts |= RCANFD_CFFDCSTS_CFBRS;
1377
1378			if (priv->can.state == CAN_STATE_ERROR_PASSIVE)
1379				sts |= RCANFD_CFFDCSTS_CFESI;
1380		}
1381
1382		rcar_canfd_write(priv->base,
1383				 RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX), sts);
1384
1385		rcar_canfd_put_data(priv, cf,
1386				    RCANFD_F_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
1387	} else {
1388		rcar_canfd_write(priv->base,
1389				 RCANFD_C_CFID(ch, RCANFD_CFFIFO_IDX), id);
1390		rcar_canfd_write(priv->base,
1391				 RCANFD_C_CFPTR(ch, RCANFD_CFFIFO_IDX), dlc);
1392		rcar_canfd_put_data(priv, cf,
1393				    RCANFD_C_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
1394	}
1395
1396	priv->tx_len[priv->tx_head % RCANFD_FIFO_DEPTH] = cf->len;
1397	can_put_echo_skb(skb, ndev, priv->tx_head % RCANFD_FIFO_DEPTH);
1398
1399	spin_lock_irqsave(&priv->tx_lock, flags);
1400	priv->tx_head++;
1401
1402	/* Stop the queue if we've filled all FIFO entries */
1403	if (priv->tx_head - priv->tx_tail >= RCANFD_FIFO_DEPTH)
1404		netif_stop_queue(ndev);
1405
1406	/* Start Tx: Write 0xff to CFPC to increment the CPU-side
1407	 * pointer for the Common FIFO
1408	 */
1409	rcar_canfd_write(priv->base,
1410			 RCANFD_CFPCTR(ch, RCANFD_CFFIFO_IDX), 0xff);
1411
1412	spin_unlock_irqrestore(&priv->tx_lock, flags);
1413	return NETDEV_TX_OK;
1414}
1415
1416static void rcar_canfd_rx_pkt(struct rcar_canfd_channel *priv)
1417{
1418	struct net_device_stats *stats = &priv->ndev->stats;
 
1419	struct canfd_frame *cf;
1420	struct sk_buff *skb;
1421	u32 sts = 0, id, dlc;
1422	u32 ch = priv->channel;
1423	u32 ridx = ch + RCANFD_RFFIFO_IDX;
1424
1425	if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1426		id = rcar_canfd_read(priv->base, RCANFD_F_RFID(ridx));
1427		dlc = rcar_canfd_read(priv->base, RCANFD_F_RFPTR(ridx));
1428
1429		sts = rcar_canfd_read(priv->base, RCANFD_F_RFFDSTS(ridx));
1430		if (sts & RCANFD_RFFDSTS_RFFDF)
 
 
1431			skb = alloc_canfd_skb(priv->ndev, &cf);
1432		else
1433			skb = alloc_can_skb(priv->ndev,
1434					    (struct can_frame **)&cf);
1435	} else {
1436		id = rcar_canfd_read(priv->base, RCANFD_C_RFID(ridx));
1437		dlc = rcar_canfd_read(priv->base, RCANFD_C_RFPTR(ridx));
1438		skb = alloc_can_skb(priv->ndev, (struct can_frame **)&cf);
1439	}
1440
1441	if (!skb) {
1442		stats->rx_dropped++;
1443		return;
1444	}
1445
1446	if (id & RCANFD_RFID_RFIDE)
1447		cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
1448	else
1449		cf->can_id = id & CAN_SFF_MASK;
1450
1451	if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1452		if (sts & RCANFD_RFFDSTS_RFFDF)
1453			cf->len = can_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1454		else
1455			cf->len = get_can_dlc(RCANFD_RFPTR_RFDLC(dlc));
1456
1457		if (sts & RCANFD_RFFDSTS_RFESI) {
1458			cf->flags |= CANFD_ESI;
1459			netdev_dbg(priv->ndev, "ESI Error\n");
1460		}
1461
1462		if (!(sts & RCANFD_RFFDSTS_RFFDF) && (id & RCANFD_RFID_RFRTR)) {
1463			cf->can_id |= CAN_RTR_FLAG;
1464		} else {
1465			if (sts & RCANFD_RFFDSTS_RFBRS)
1466				cf->flags |= CANFD_BRS;
1467
1468			rcar_canfd_get_data(priv, cf, RCANFD_F_RFDF(ridx, 0));
1469		}
1470	} else {
1471		cf->len = get_can_dlc(RCANFD_RFPTR_RFDLC(dlc));
1472		if (id & RCANFD_RFID_RFRTR)
1473			cf->can_id |= CAN_RTR_FLAG;
 
 
1474		else
1475			rcar_canfd_get_data(priv, cf, RCANFD_C_RFDF(ridx, 0));
1476	}
1477
1478	/* Write 0xff to RFPC to increment the CPU-side
1479	 * pointer of the Rx FIFO
1480	 */
1481	rcar_canfd_write(priv->base, RCANFD_RFPCTR(ridx), 0xff);
1482
1483	can_led_event(priv->ndev, CAN_LED_EVENT_RX);
1484
1485	stats->rx_bytes += cf->len;
 
1486	stats->rx_packets++;
1487	netif_receive_skb(skb);
1488}
1489
1490static int rcar_canfd_rx_poll(struct napi_struct *napi, int quota)
1491{
1492	struct rcar_canfd_channel *priv =
1493		container_of(napi, struct rcar_canfd_channel, napi);
 
1494	int num_pkts;
1495	u32 sts;
1496	u32 ch = priv->channel;
1497	u32 ridx = ch + RCANFD_RFFIFO_IDX;
1498
1499	for (num_pkts = 0; num_pkts < quota; num_pkts++) {
1500		sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
1501		/* Check FIFO empty condition */
1502		if (sts & RCANFD_RFSTS_RFEMP)
1503			break;
1504
1505		rcar_canfd_rx_pkt(priv);
1506
1507		/* Clear interrupt bit */
1508		if (sts & RCANFD_RFSTS_RFIF)
1509			rcar_canfd_write(priv->base, RCANFD_RFSTS(ridx),
1510					 sts & ~RCANFD_RFSTS_RFIF);
1511	}
1512
1513	/* All packets processed */
1514	if (num_pkts < quota) {
1515		napi_complete(napi);
1516		/* Enable Rx FIFO interrupts */
1517		rcar_canfd_set_bit(priv->base, RCANFD_RFCC(ridx),
1518				   RCANFD_RFCC_RFIE);
 
1519	}
1520	return num_pkts;
1521}
1522
1523static int rcar_canfd_do_set_mode(struct net_device *ndev, enum can_mode mode)
1524{
1525	int err;
1526
1527	switch (mode) {
1528	case CAN_MODE_START:
1529		err = rcar_canfd_start(ndev);
1530		if (err)
1531			return err;
1532		netif_wake_queue(ndev);
1533		return 0;
1534	default:
1535		return -EOPNOTSUPP;
1536	}
1537}
1538
1539static int rcar_canfd_get_berr_counter(const struct net_device *dev,
1540				       struct can_berr_counter *bec)
1541{
1542	struct rcar_canfd_channel *priv = netdev_priv(dev);
1543	u32 val, ch = priv->channel;
1544
1545	/* Peripheral clock is already enabled in probe */
1546	val = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1547	bec->txerr = RCANFD_CSTS_TECCNT(val);
1548	bec->rxerr = RCANFD_CSTS_RECCNT(val);
1549	return 0;
1550}
1551
1552static const struct net_device_ops rcar_canfd_netdev_ops = {
1553	.ndo_open = rcar_canfd_open,
1554	.ndo_stop = rcar_canfd_close,
1555	.ndo_start_xmit = rcar_canfd_start_xmit,
1556	.ndo_change_mtu = can_change_mtu,
1557};
1558
 
 
 
 
1559static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch,
1560				    u32 fcan_freq)
1561{
 
1562	struct platform_device *pdev = gpriv->pdev;
1563	struct rcar_canfd_channel *priv;
1564	struct net_device *ndev;
1565	int err = -ENODEV;
1566
1567	ndev = alloc_candev(sizeof(*priv), RCANFD_FIFO_DEPTH);
1568	if (!ndev) {
1569		dev_err(&pdev->dev, "alloc_candev() failed\n");
1570		err = -ENOMEM;
1571		goto fail;
1572	}
1573	priv = netdev_priv(ndev);
1574
1575	ndev->netdev_ops = &rcar_canfd_netdev_ops;
 
1576	ndev->flags |= IFF_ECHO;
1577	priv->ndev = ndev;
1578	priv->base = gpriv->base;
1579	priv->channel = ch;
 
1580	priv->can.clock.freq = fcan_freq;
1581	dev_info(&pdev->dev, "can_clk rate is %u\n", priv->can.clock.freq);
1582
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1583	if (gpriv->fdmode) {
1584		priv->can.bittiming_const = &rcar_canfd_nom_bittiming_const;
1585		priv->can.data_bittiming_const =
1586			&rcar_canfd_data_bittiming_const;
1587
1588		/* Controller starts in CAN FD only mode */
1589		can_set_static_ctrlmode(ndev, CAN_CTRLMODE_FD);
 
 
1590		priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
1591	} else {
1592		/* Controller starts in Classical CAN only mode */
1593		priv->can.bittiming_const = &rcar_canfd_bittiming_const;
1594		priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
1595	}
1596
1597	priv->can.do_set_mode = rcar_canfd_do_set_mode;
1598	priv->can.do_get_berr_counter = rcar_canfd_get_berr_counter;
1599	priv->gpriv = gpriv;
1600	SET_NETDEV_DEV(ndev, &pdev->dev);
1601
1602	netif_napi_add(ndev, &priv->napi, rcar_canfd_rx_poll,
1603		       RCANFD_NAPI_WEIGHT);
 
 
1604	err = register_candev(ndev);
1605	if (err) {
1606		dev_err(&pdev->dev,
1607			"register_candev() failed, error %d\n", err);
1608		goto fail_candev;
1609	}
1610	spin_lock_init(&priv->tx_lock);
1611	devm_can_led_init(ndev);
1612	gpriv->ch[priv->channel] = priv;
1613	dev_info(&pdev->dev, "device registered (channel %u)\n", priv->channel);
1614	return 0;
1615
1616fail_candev:
1617	netif_napi_del(&priv->napi);
1618	free_candev(ndev);
1619fail:
 
1620	return err;
1621}
1622
1623static void rcar_canfd_channel_remove(struct rcar_canfd_global *gpriv, u32 ch)
1624{
1625	struct rcar_canfd_channel *priv = gpriv->ch[ch];
1626
1627	if (priv) {
1628		unregister_candev(priv->ndev);
1629		netif_napi_del(&priv->napi);
1630		free_candev(priv->ndev);
1631	}
1632}
1633
1634static int rcar_canfd_probe(struct platform_device *pdev)
1635{
1636	struct resource *mem;
1637	void __iomem *addr;
1638	u32 sts, ch, fcan_freq;
1639	struct rcar_canfd_global *gpriv;
1640	struct device_node *of_child;
1641	unsigned long channels_mask = 0;
1642	int err, ch_irq, g_irq;
 
1643	bool fdmode = true;			/* CAN FD only mode - default */
 
 
 
 
1644
1645	if (of_property_read_bool(pdev->dev.of_node, "renesas,no-can-fd"))
1646		fdmode = false;			/* Classical CAN only mode */
1647
1648	of_child = of_get_child_by_name(pdev->dev.of_node, "channel0");
1649	if (of_child && of_device_is_available(of_child))
1650		channels_mask |= BIT(0);	/* Channel 0 */
1651
1652	of_child = of_get_child_by_name(pdev->dev.of_node, "channel1");
1653	if (of_child && of_device_is_available(of_child))
1654		channels_mask |= BIT(1);	/* Channel 1 */
1655
1656	ch_irq = platform_get_irq(pdev, 0);
1657	if (ch_irq < 0) {
1658		dev_err(&pdev->dev, "no Channel IRQ resource\n");
1659		err = ch_irq;
1660		goto fail_dev;
1661	}
1662
1663	g_irq = platform_get_irq(pdev, 1);
1664	if (g_irq < 0) {
1665		dev_err(&pdev->dev, "no Global IRQ resource\n");
1666		err = g_irq;
1667		goto fail_dev;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1668	}
1669
1670	/* Global controller context */
1671	gpriv = devm_kzalloc(&pdev->dev, sizeof(*gpriv), GFP_KERNEL);
1672	if (!gpriv) {
1673		err = -ENOMEM;
1674		goto fail_dev;
1675	}
1676	gpriv->pdev = pdev;
1677	gpriv->channels_mask = channels_mask;
1678	gpriv->fdmode = fdmode;
 
 
 
 
 
 
 
 
 
 
 
 
 
1679
1680	/* Peripheral clock */
1681	gpriv->clkp = devm_clk_get(&pdev->dev, "fck");
1682	if (IS_ERR(gpriv->clkp)) {
1683		err = PTR_ERR(gpriv->clkp);
1684		dev_err(&pdev->dev, "cannot get peripheral clock, error %d\n",
1685			err);
1686		goto fail_dev;
1687	}
1688
1689	/* fCAN clock: Pick External clock. If not available fallback to
1690	 * CANFD clock
1691	 */
1692	gpriv->can_clk = devm_clk_get(&pdev->dev, "can_clk");
1693	if (IS_ERR(gpriv->can_clk) || (clk_get_rate(gpriv->can_clk) == 0)) {
1694		gpriv->can_clk = devm_clk_get(&pdev->dev, "canfd");
1695		if (IS_ERR(gpriv->can_clk)) {
1696			err = PTR_ERR(gpriv->can_clk);
1697			dev_err(&pdev->dev,
1698				"cannot get canfd clock, error %d\n", err);
1699			goto fail_dev;
1700		}
1701		gpriv->fcan = RCANFD_CANFDCLK;
1702
1703	} else {
1704		gpriv->fcan = RCANFD_EXTCLK;
1705	}
1706	fcan_freq = clk_get_rate(gpriv->can_clk);
1707
1708	if (gpriv->fcan == RCANFD_CANFDCLK)
1709		/* CANFD clock is further divided by (1/2) within the IP */
1710		fcan_freq /= 2;
1711
1712	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1713	addr = devm_ioremap_resource(&pdev->dev, mem);
1714	if (IS_ERR(addr)) {
1715		err = PTR_ERR(addr);
1716		goto fail_dev;
1717	}
1718	gpriv->base = addr;
1719
1720	/* Request IRQ that's common for both channels */
1721	err = devm_request_irq(&pdev->dev, ch_irq,
1722			       rcar_canfd_channel_interrupt, 0,
1723			       "canfd.chn", gpriv);
1724	if (err) {
1725		dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
1726			ch_irq, err);
1727		goto fail_dev;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1728	}
1729	err = devm_request_irq(&pdev->dev, g_irq,
1730			       rcar_canfd_global_interrupt, 0,
1731			       "canfd.gbl", gpriv);
 
 
1732	if (err) {
1733		dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
1734			g_irq, err);
1735		goto fail_dev;
1736	}
1737
1738	/* Enable peripheral clock for register access */
1739	err = clk_prepare_enable(gpriv->clkp);
1740	if (err) {
1741		dev_err(&pdev->dev,
1742			"failed to enable peripheral clock, error %d\n", err);
1743		goto fail_dev;
1744	}
1745
1746	err = rcar_canfd_reset_controller(gpriv);
1747	if (err) {
1748		dev_err(&pdev->dev, "reset controller failed\n");
1749		goto fail_clk;
1750	}
1751
1752	/* Controller in Global reset & Channel reset mode */
1753	rcar_canfd_configure_controller(gpriv);
1754
1755	/* Configure per channel attributes */
1756	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1757		/* Configure Channel's Rx fifo */
1758		rcar_canfd_configure_rx(gpriv, ch);
1759
1760		/* Configure Channel's Tx (Common) fifo */
1761		rcar_canfd_configure_tx(gpriv, ch);
1762
1763		/* Configure receive rules */
1764		rcar_canfd_configure_afl_rules(gpriv, ch);
1765	}
1766
1767	/* Configure common interrupts */
1768	rcar_canfd_enable_global_interrupts(gpriv);
1769
1770	/* Start Global operation mode */
1771	rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GMDC_MASK,
1772			      RCANFD_GCTR_GMDC_GOPM);
1773
1774	/* Verify mode change */
1775	err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
1776				 !(sts & RCANFD_GSTS_GNOPM), 2, 500000);
1777	if (err) {
1778		dev_err(&pdev->dev, "global operational mode failed\n");
1779		goto fail_mode;
1780	}
1781
1782	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1783		err = rcar_canfd_channel_probe(gpriv, ch, fcan_freq);
1784		if (err)
1785			goto fail_channel;
1786	}
1787
1788	platform_set_drvdata(pdev, gpriv);
1789	dev_info(&pdev->dev, "global operational state (clk %d, fdmode %d)\n",
1790		 gpriv->fcan, gpriv->fdmode);
1791	return 0;
1792
1793fail_channel:
1794	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
1795		rcar_canfd_channel_remove(gpriv, ch);
1796fail_mode:
1797	rcar_canfd_disable_global_interrupts(gpriv);
1798fail_clk:
1799	clk_disable_unprepare(gpriv->clkp);
 
 
 
1800fail_dev:
1801	return err;
1802}
1803
1804static int rcar_canfd_remove(struct platform_device *pdev)
1805{
1806	struct rcar_canfd_global *gpriv = platform_get_drvdata(pdev);
1807	u32 ch;
1808
1809	rcar_canfd_reset_controller(gpriv);
1810	rcar_canfd_disable_global_interrupts(gpriv);
1811
1812	for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1813		rcar_canfd_disable_channel_interrupts(gpriv->ch[ch]);
1814		rcar_canfd_channel_remove(gpriv, ch);
1815	}
1816
1817	/* Enter global sleep mode */
1818	rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
1819	clk_disable_unprepare(gpriv->clkp);
 
 
 
1820	return 0;
1821}
1822
1823static int __maybe_unused rcar_canfd_suspend(struct device *dev)
1824{
1825	return 0;
1826}
1827
1828static int __maybe_unused rcar_canfd_resume(struct device *dev)
1829{
1830	return 0;
1831}
1832
1833static SIMPLE_DEV_PM_OPS(rcar_canfd_pm_ops, rcar_canfd_suspend,
1834			 rcar_canfd_resume);
1835
1836static const struct of_device_id rcar_canfd_of_table[] = {
1837	{ .compatible = "renesas,rcar-gen3-canfd" },
 
 
1838	{ }
1839};
1840
1841MODULE_DEVICE_TABLE(of, rcar_canfd_of_table);
1842
1843static struct platform_driver rcar_canfd_driver = {
1844	.driver = {
1845		.name = RCANFD_DRV_NAME,
1846		.of_match_table = of_match_ptr(rcar_canfd_of_table),
1847		.pm = &rcar_canfd_pm_ops,
1848	},
1849	.probe = rcar_canfd_probe,
1850	.remove = rcar_canfd_remove,
1851};
1852
1853module_platform_driver(rcar_canfd_driver);
1854
1855MODULE_AUTHOR("Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>");
1856MODULE_LICENSE("GPL");
1857MODULE_DESCRIPTION("CAN FD driver for Renesas R-Car SoC");
1858MODULE_ALIAS("platform:" RCANFD_DRV_NAME);